WO2006060396A2 - Packaging for high power integrated circuits using supercritical fluid - Google Patents
Packaging for high power integrated circuits using supercritical fluid Download PDFInfo
- Publication number
- WO2006060396A2 WO2006060396A2 PCT/US2005/043139 US2005043139W WO2006060396A2 WO 2006060396 A2 WO2006060396 A2 WO 2006060396A2 US 2005043139 W US2005043139 W US 2005043139W WO 2006060396 A2 WO2006060396 A2 WO 2006060396A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- package
- supercritical fluid
- recited
- electronic device
- heat
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Definitions
- the field of the invention is the packaging of electronic devices such as semiconductors, and particularly, the cooling of such devices.
- Chips Modern digital and analog integrated circuits
- circuits are consuming ever- larger amounts of DC power as the number of transistors per unit area is increased in digital chips, and as the amount of output power required of analog chips (such as power amplifiers) is increased through the use of improved design techniques, more capable transistors, and new transistor materials (in the latter case: silicon germanium bipolar transistors; indium phosphide, gallium nitride, and silicon carbide transistors).
- the chips convert all or much of the DC power that they absorb from the power supply into heat: in the case of digital circuits, almost all of the DC input power becomes waste heat: and in the case of analog (i.e., amplifier) chips, 50-80% of the DC input power becomes waste heat.
- Silicon and indium phosphide chips can operate at temperatures up to approximately 85° C. Gallium nitride and silicon carbide chips can survive to much higher temperatures but still have a maximum operating temperature. The problem is that with ever-tighter packing of transistors on all of these chips, the power densities (heat loads) of these chips, measured in watts of power per square centimeter of chip area, are increasing very dramatically.
- a chip with thermal densities above 10 W/cm 2 was the norm; presently, even silicon chips have been designed with power densities of 350 W/cm 2 .
- a chip is bonded (soldered or epoxy-attached) into a package which contains a large metal mass, such that the heat flows from the back of the chip directly into the metal mass, and then into a finned radiator, over which cool air is blown to remove the heat, hi come cases, the lower temperature "sink” is a cold plate through which cold water, Freon, or other working fluid are passed as a transport fluid, hi fact, for each level of chip power density, there are a range of cooling options that best match the overall system design considerations.
- the chart in Fig. 1 illustrates this point. As the overall power density of the chip increases, the cooling options decrease, and at power densities above 100-200 W/cm 2 , the options become quite limited.
- Chip cooling by directly pumping a working fluid such as fluorocarbon onto the chip(s) has been developed and cutting microchannels in the back of the chips and pumping liquid through the microchannels has been developed in an effort to operate at these power densities.
- This invention is a completely self-contained and encapsulated "package" into which a high power device such as an integrated circuit (“chip”), can be installed to provide the necessary thermal and electrical environment to assure that the high power device works correctly.
- the packaging approach not only assures that DC electrical power will be delivered to the device and signals will be brought into and led from the device in a correct manner, but also that the operating temperature of the device will remain below its maximum survivable operating temperature.
- the cooling approach uses a non-electrically conductive working fluid to create an isothermal environment for the device inside the package and to transfer heat to a "cold plate” or “cold pipe".
- the working fluid is a supercritical fluid or mixture of supercritical fluids that is operated above its critical temperature and pressure, where its viscosity and surface tension are extremely low and its ability to carry heat away from the hot device is very high.
- An advantage of this invention is that it allows for direct device-side cooling of the device.
- the device is mounted to a substrate and an enclosed space is formed around the device which contains the working supercritical fluid.
- the much larger enclosure is cooled by more conventional means.
- This technique can be utilized with devices that are flip-chip attached or wirebonded to the substrate. Passivation of the device is not required with selection of the proper working fluid.
- Direct cooling is done in phase change cooling techniques such as theraiosyphons and microchannel flows.
- the use of a supercritical fluid eliminates the problems of vapor entrapment and thermal shock due to the incipience temperature drop that are seen with phase change cooling.
- This invention does not adversely affect the electrical performance of the device.
- a thermally conductive but electrically insulating supercritical fluid surrounds the interconnection between the device and the substrate.
- the dielectric constant of supercritical sulfur hexafluoride is close to that of air.
- This invention also offers some mechanical advantages over other thermal management methods.
- the number of thermal interfaces needed is reduced because the working fluid is in direct contact with the heat generating device.
- One of the issues with attachment of heat spreaders and heat sinks is the need to compensate for the coefficient of thermal expansion (CTE) mismatch between the chip, heat spreader, and the heat sink.
- CTE coefficient of thermal expansion
- thermally conductive adhesive must be used to transition between the heat spreader, which typically has a coefficient of thermal expansion (“CTE") matched to the power device, and the heat sink, which is typically a high CTE material.
- This interface increases the thermal resistance of the conduction path which in turn increases the junction temperature.
- the invention offers advantages for high shock and vibration environments, because the thermal path presented by the supercritical working fluid is not structural.
- This invention may easily be used in combination with other thermal management techniques.
- heat spreaders and heat sinks can be attached to the back of the chip or package while the heat is also removed from the top by the supercritical fluid.
- Chip level cooling techniques such as thermal vias, thinned chips, on-chip integration of Peltier devices, microchannels in the back of the chip may also be used in conjunction with the supercritical fluid.
- Fig. 1 is a graphic indication of the ranges of different cooling techniques
- FIG. 2 is a pictorial representation of a preferred embodiment of the invention.
- Fig 3 is a graphic representation of the phases a typical working fluid used in the embodiment of Fig 2 can have.
- This invention is a completely self-contained and encapsulated "package” into which a high power integrated circuit (“chip”) such as an amplifier, or an entire subsystem (such as a radar “transmit-receive” module), can be installed to provide the necessary thermal and electrical environment to assure that the chip or multi-chip subsystem works correctly.
- a high power integrated circuit such as an amplifier, or an entire subsystem (such as a radar “transmit-receive” module)
- the packaging approach not only assures that DC electrical power will be delivered to the chip(s) and AC signals will be brought into and led from the chip(s) in a correct manner, but also that the operating temperature of the chip(s) will remain below their maximum survivable operating temperature.
- a preferred embodiment of the invention includes a substrate 10 which supports on its top surface one or more devices.
- An enclosure 12 made of a heat conductive material such as aluminum is attached to the substrate 10 and it extends over the devices 18, 20 and 22 to form an enclosed space indicated generally at 14.
- the enclosure 12 has side walls 16 that extend away from the top surface of the substrate 10 and surround the supported devices 18, 20 and 22 and a top wall 24 that covers the enclosed space 14.
- a heat exchanger in the form of a pipe 26 is in thermal contact with the top wall 24 and a cooling fluid indicated by arrow 28 is pumped through the pipe 26 to maintain the temperature of the top wall 24 at a desired level.
- This invention does not rely on the change of phase of the working fluid, but instead on the fact that certain fluids, such as sulfur hexafluoride, can be driven into their "supercritical" range, where they have the following useful properties: 1) extremely low viscosity; 2) high thermal conductivity; 3) high heat capacity; 4) low surface tension; and 5) low dielectric constant. [0016]
- the advantage of using supercritical fluids to transport heat away from devices can be driven into their "supercritical" range, where they have the following useful properties: 1) extremely low viscosity; 2) high thermal conductivity; 3) high heat capacity; 4) low surface tension; and 5) low dielectric constant.
- a typical fluid in its supercritical region has a density 100 times that of it gaseous phase and of the same order of magnitude as its liquid phase.
- it has a viscosity ten times greater than its gaseous phase but one-tenth to one-twentieth that of its liquid phase and a high degree of "wettability" due to an extremely low surface tension and energy.
- the supercritical fluid's transport properties are similar to that of a gas but the density approaches that of a liquid.
- the thermodynamic characteristics of a supercritical fluid can potentially be exploited as well.
- the rightmost device 18 in Fig. 2 is an unpassivated wire-bonded chip mounted with its active or "top” surface face-up. Electrical connections are made with "wire bonds" from the chip pads to contact pads on the supporting substrate 10.
- Power and signal feeds to the contact pads on the chip can be by means of wire or ribbon bond 32, or a so- called chips first MCM overlay on the active chip surface.
- a unique feature of using a chemically inert supercritical working fluid as the heat transport mechanism is that unpassivated chips such as the IH-V compound semiconductors such as gallium arsenide and indium phosphide can be exposed to the working fluid directly without concern for corrosion caused by the fluid. Further, since the dielectric constant of such a working fluid can approach that of air (i.e., 1.0), the electrical performance of microwave and millimeter wave analog chips will not be compromised by the presence of the working fluid above the active surface of the analog chip.
- the leftmost device 20 is mounted to the substrate 10 such that its active surface is face-down, with electrical connections (signals, power, and ground) made between the contact pads on that chip and contact pads on the substrate 10 using solder balls or bumps, or gold balls 30.
- solder balls or bumps, or gold balls 30 are solder balls or bumps, or gold balls 30.
- no epoxy or other type of "underfill” is inserted between the chip 20 and the substrate 10.
- the space between the solder bumps or gold balls 30 is thus accessible to the working fluid and it becomes an integral part of the cooling approach for this system.
- Very tiny externally powered micro-pumps of either conventional or unconventional design, may be incorporated inside the enclosed space 14 to move the supercritical fluid.
- Microfluidic pumps of unconventional design such as a solid-state Micro-Electro-Mechanical System (MEMS) pump indicated at 22 may be employed to move fluid beneath the chip 20 as indicated by arrow 36.
- the purpose of the pump 22 is to transport a small quantity of fluid into the interstices between the gold or solder ball bonds 30 on one or two sides of chips mounted "face down", thus allowing heat to be carried away from the active surface of the chip and into the volume above all the chips.
- MEMS Micro-Electro-Mechanical System
- the system will function properly in essentially any position with respect to gravity.
- the embodiment shown in Fig. 2 depicts a completely closed and hermetic cooling implementation in which the flow of supercritical fluid is driven by the source of and sink for the heat (the chips and the heat exchanger respectively).
- Baffles 38 attached to the top 24 of the enclosure 12 are installed to create turbulence in the convective flow of the working fluid. This increases the transfer of heat from the working fluid to the heat-exchanging surface(s).
- Baffles of several different designs are possible, the shape, size, and position of which will depend on the characteristics of the selected supercritical working fluid.
- US Patent #6,799,587 describes a system of baffles designed for use in a supercritical fluid cleaning system that creates a relatively high velocity, cooled stream of supercritical fluid.
- the pressure buildup and burping action created by the baffles may be used to direct the high velocity, cooled fluid towards the hot chip(s) 18 and 20.
- the substrate 10 is a material comprised of alternate layers of metal 40 that provide circuitry for power and ground distribution to the chips, and for the distribution of AC electrical signals to and from the chips. Between the metal layers 40 are insulating dielectric layers 42.
- This "substrate" which comprises the floor of the package must be strong enough to withstand the bending forces that are exerted by the supercritical working fluid, since the interior space 14 must be pressurized to the supercritical pressure of the working fluid (e.g., 545 psi in the case of sulfur hexafluoride).
- the coefficient of thermal expansion of the substrate 10 must closely match that of the chip in order to reduce stress on the interconnection between the chip and the substrate 10 since underfill is not used. If, for example, the substrate is low- temperature or high-temperature cofired ceramic, the substrate may itself contribute to the removal of heat from the interior space 14 of the package.
- the potential heat removal efficacy of a single-chip or multichip package using a supercritical working fluid as described above is 80 watts.
- Supercritical sulfur hexafluoride is used as the working fluid in which the temperature at the devices 18 and 20 is maintained at 75 C, the fluid flow past the chips is 5 cc/minute, and the temperature at the heat exchanger 26 is 50 C.
- Heat removal can be increased by using other thermal management techniques in combination with the supercritical fluid. These include, for example, increasing the fluid flow by means of baffles 38 or active pumping of the fluid with pump 22, or by allowing the temperature at the chips to be higher. Also, thermal vias 25 may be formed through the substrate 10 at points beneath the heat producing device 20. These are metal throughholes that provide heat conductive paths through the substrate 10 at points where the temperature peaks. The higher heat conductivity of the vias 25 lowers the temperature at these points. [0023] Other working fluids having even better heat transfer characteristics may also be used.
- Possible alternative working fluids include but are not limited to engineered heat transfer fluids such as fluorocarbons sold under the trademark “Fluorinerts” which are inert, have higher density and thermal conductivity than sulfur hexafluoride, and are designed to cover a wide range of temperatures.
- Fluorinerts which are inert, have higher density and thermal conductivity than sulfur hexafluoride, and are designed to cover a wide range of temperatures.
- supercritical fluids are fluids that have a critical point 49 defined as the set of physical conditions where the properties of the liquid phase and the gas phase of the fluid become identical. This condition is true for single component as well as multi-component working fluids.
- a supercritical fluid state exists in a pressure/temperature region that resides above a critical temperature T c and above a critical pressure P c .
- a candidate fluid should have a critical temperature (T c ) that is lower than the maximum operating temperature allowable for the device being cooled and a critical pressure (P c ) that is practical to achieve in a commercial setting.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/720,383 US7642644B2 (en) | 2004-12-03 | 2005-11-30 | Packaging for high power integrated circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US63291704P | 2004-12-03 | 2004-12-03 | |
US60/632,917 | 2004-12-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006060396A2 true WO2006060396A2 (en) | 2006-06-08 |
WO2006060396A3 WO2006060396A3 (en) | 2006-10-12 |
Family
ID=36565636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/043139 WO2006060396A2 (en) | 2004-12-03 | 2005-11-30 | Packaging for high power integrated circuits using supercritical fluid |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2006060396A2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6709890B2 (en) * | 2000-02-15 | 2004-03-23 | Renesas Technology Corporation | Method of manufacturing semiconductor integrated circuit device |
-
2005
- 2005-11-30 WO PCT/US2005/043139 patent/WO2006060396A2/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6709890B2 (en) * | 2000-02-15 | 2004-03-23 | Renesas Technology Corporation | Method of manufacturing semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
WO2006060396A3 (en) | 2006-10-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7032392B2 (en) | Method and apparatus for cooling an integrated circuit package using a cooling fluid | |
US11594469B2 (en) | Semiconductor device and method of manufacture | |
US7002247B2 (en) | Thermal interposer for thermal management of semiconductor devices | |
US9741638B2 (en) | Thermal structure for integrated circuit package | |
Sekar et al. | A 3D-IC technology with integrated microchannel cooling | |
US7180179B2 (en) | Thermal interposer for thermal management of semiconductor devices | |
US7656028B2 (en) | System for controlling the temperature of an associated electronic device using an enclosure having a working fluid arranged therein and a chemical compound in the working fluid that undergoes a reversible chemical reaction to move heat from the associated electronic device | |
CN100499091C (en) | Method, device and system for cooling heat source | |
US7434308B2 (en) | Cooling of substrate using interposer channels | |
US8937383B2 (en) | Direct semiconductor contact ebullient cooling package | |
US20240363483A1 (en) | Semiconductor package structure | |
US7250576B2 (en) | Chip package having chip extension and method | |
US8335083B2 (en) | Apparatus and method for thermal management using vapor chamber | |
US20210195798A1 (en) | Full package vapor chamber with ihs | |
Karimi et al. | Review and assessment of pulsating heat pipe mechanism for high heat flux electronic cooling | |
US7642644B2 (en) | Packaging for high power integrated circuits | |
US8367478B2 (en) | Method and system for internal layer-layer thermal enhancement | |
WO2019194089A1 (en) | Electronic apparatus | |
Moon et al. | Application of aluminum flat heat pipe for dry cooling near the hot spot of a radar array with a multiscale structure | |
KR101489699B1 (en) | Heat dissipation on chip substrates | |
WO2006060396A2 (en) | Packaging for high power integrated circuits using supercritical fluid | |
US20230386960A1 (en) | Semiconductor package including lid with integrated heat pipe for thermal management and methods for forming the same | |
JPH06209060A (en) | Device and method for cooling semiconductor chip | |
Schulz-Harder et al. | DBC (direct bond copper) substrate with integrated flat heat pipe | |
Fodor et al. | Guidelines on thermal management solutions for modern packaging technologies-a review |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11720383 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 05825553 Country of ref document: EP Kind code of ref document: A2 |