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WO2005117024A1 - Memoire a semi-conducteurs integree pourvue d'un transistor de selection organique - Google Patents

Memoire a semi-conducteurs integree pourvue d'un transistor de selection organique Download PDF

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Publication number
WO2005117024A1
WO2005117024A1 PCT/DE2005/000926 DE2005000926W WO2005117024A1 WO 2005117024 A1 WO2005117024 A1 WO 2005117024A1 DE 2005000926 W DE2005000926 W DE 2005000926W WO 2005117024 A1 WO2005117024 A1 WO 2005117024A1
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WO
WIPO (PCT)
Prior art keywords
selection transistor
integrated semiconductor
semiconductor memory
memory
bit line
Prior art date
Application number
PCT/DE2005/000926
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German (de)
English (en)
Inventor
Hagen Klauk
Marcus Halik
Ute Zschieschang
Günter Schmid
Christine Dehm
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2005117024A1 publication Critical patent/WO2005117024A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/80—Array wherein the substrate, the cell, the conductors and the access device are all made up of organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the invention relates to an integrated semiconductor memory having a cell array comprising a plurality of memory cells arranged in rows and columns on a substrate, each of which has a memory element with two electrodes and an associated selection transistor.
  • DRAM dynamic random access memory
  • DRAM technology is based on the storage of electronic charges in a capacitive storage element, i.e. in a capacitor.
  • Each memory cell represents a memory unit (“bit”) and is formed by a capacitor and a selection transistor (a field effect transistor, FET).
  • FET field effect transistor
  • the task of the selection transistor is the electrical insulation of the individual memory cells from one another and from the periphery of the cell array; By switching the respective selection transistor, any cell can be specifically and individually accessed (“random access”).
  • the DRAM architecture is characterized by extremely small space requirements (less than one square micron per memory cell) and extremely low manufacturing costs (less than 10 ⁇ 8 euros per memory cell).
  • the decisive disadvantage of the DRAM concept is the volatility of the stored information, since the charge stored in the capacitor is so small (less than 500,000 electrons) that it Switching off the supply voltage after a short time (within a few milliseconds) is lost due to leakage currents within the cell field.
  • Nonvolatile memory which does not lose the stored information even after the supply voltage has been switched off for long periods (several years), is suitable for a wide range of applications (digital cameras, mobile phones, mobile navigation instruments, computer games, etc .) of interest and could also revolutionize the way computers are used, since it would not be necessary to start up the computer after switching it on (“instant-on computer”).
  • Existing non-volatile memory technologies include what are known as flash memories, in which the information is stored in the form of electronic charges in the gate dielectric of a silicon field-effect transistor and is detected as a change in the threshold voltage of the transistor. Since the electronic charge is "trapped" in the gate dielectric of the transistor, it is not lost even when the supply voltage is switched off.
  • a major disadvantage of flash technology are the relatively high write and erase voltages, which result from the need to safely and reproducibly inject the electronic charge to be stored into the gate dielectric or to withdraw it from there.
  • Other disadvantages are the significantly longer access times compared to the DRAM and the limited reliability due to the high load on the gate dielectric when writing and erasing.
  • the implementation of cells without a selection transistor has the essential advantage of a significantly smaller space requirement, which leads to a significantly higher integration density and a lower manufacturing effort per cell.
  • the use of a selection transistor makes reading out the stored information considerably easier and safer, and it is foreseeable that the first magnetoresistive memory products will be based on a structure with a selection transistor.
  • FIGS. 1 a - lf show six possible circuit diagrams of an optionally volatile or non-volatile memory cell with an optionally capacitive, resistive or memory element S based on another physical concept and a selection transistor T.
  • FIGS. La-lf differ in the arrangement and connection of the memory element S and the selection transistor T with a word line WL, a bit line BL, a digit line DL and a field plate FP. It should be noted here that the basic interconnections of a memory element with a selection transistor shown in FIGS. 1 a - 1 are known per se in the prior art:
  • FIG. 1 a shows that the drain connection of the selection transistor T is on the bit line BL and the memory element S lies between the source connection of the selection transistor T and a field plate FP.
  • the drain connection of the selection transistor T is on the bit line BL and the memory element is between the source connection of the selection transistor T and a digit line DL, which is led in parallel with the word line WL.
  • the drain connection of the selection transistor T is on the bit line BL and the memory element S is between the source connection of the selection transistor T and a digit line DL, which runs parallel to the bit line BL.
  • the source connection of the selection transistor T lies on a field plate FP and the memory element S lies between the drain connection of the selection transistor T and the bit line BL.
  • FIG. 1 shows that the source terminal of the selection transistor T is on a digit line DL and the memory element S is between the drain terminal of the selection transistor T and the bit line BL, the digit line DL running parallel to the word line WL.
  • the source connection of the selection transistor T is connected to a digit line and the memory element S lies between the drain connection of the selection transistor T and
  • Bit line BL Bit line BL, the digit line DL running parallel to the bit line BL.
  • the memory cell S is always selected via the word line WL, which is connected in each case to the gate electrode of the selection transistor T.
  • a suitable potential to the word line WL for example a negative potential if the selection transistor T is a p-type transistor with a negative threshold voltage
  • the selection transistor T is opened (electrically conductive) and the information stored in the memory element S can be transmitted through
  • Applying suitable potentials to bit line BL and digit line DL or field plate FP can be read out via the bit line in a read cycle or changed in a write or erase cycle.
  • An embodiment of the memory cell with a digit line DL has the advantage over an embodiment with a field plate FP that the potential on this line can be specifically changed for the cell that is currently being accessed. Designing an integrated semiconductor memory with FP field plate can lead to a smaller space requirement for the cell field.
  • bit line capacity An important criterion in the implementation of the memory cells is the bit line capacity, which should be as small as possible in the interest of fast access times.
  • the capacitance associated with the selection transistor T is greater or smaller than the capacitance associated with the memory element S is either shown in FIGS. 1 a - lc (in which the selection transistor T is located on the bit line BL) or the configurations in accordance with FIGS ld-lf (in which the memory element S lies between the bit line BL and the drain connection of the selection transistor T) has the lower bit line capacitance.
  • FIG. 2a shows a highly simplified circuit diagram of a cell array of an integrated semiconductor memory, which is designed according to FIG. 1b.
  • the digit line DL0 runs parallel to the word line WL0 (for simplification only the selection transistors and the memory elements of a 0th line are provided with reference numerals in FIG. 2a).
  • FIG. 2b shows a highly simplified circuit diagram of a cell field which is designed according to FIG. 1f.
  • the source connections of the selection transistors T01 - TOm are on digital lines DL0 - DLm and the memory elements S01 - SOm are each between the drain connection of the selection transistor and the associated bit line BL0 - BLm.
  • the digit lines DL0 - DLm run parallel to the bit lines BL0 - BLm.
  • FIGS. 2a-2b only show a section of a cell field consisting of m columns (bit lines) and n rows (word lines). The row direction is labeled x and the column direction is labeled y.
  • FIG. 3 shows a greatly simplified circuit diagram of a cell field consisting of m columns and n rows, which common bit lines ("shared bit lines") is executed.
  • the memory cells of the first, third, fifth, etc. column are each offset by one row compared to the memory cells of the zero, second, fourth column (y direction).
  • the circuit arrangement of the memory elements and the selection transistors corresponds to the arrangement according to FIG. 2b, the digit lines DLO, DL1 being replaced by bit lines BL1, BL3 etc.
  • an integrated semiconductor memory having a cell array composed of a plurality of memory cells arranged in rows and columns on a substrate, each of which has a memory element with two electrodes and an associated selection transistor, the control electrodes of the selection transistors of the individual lines by in the line direction current word lines and a controlled electrode of the selection transistors of the individual columns are either connected to a bit line running in the column direction, or to a digit line or to a field plate, and one electrode of each storage element is connected to the other controlled electrode of the associated selection transistor and the other electrode of each storage element is connected to either a bit line, a digit line or a field plate.
  • the integrated semiconductor memory is distinguished in that each memory cell has an organic one
  • the substrate does not need to be a silicon substrate but can consist of glass, a polymer film, a metal film covered with an insulating layer or also of paper and other substrates which do not contain silicon.
  • the selection transistors are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer is arranged above the gate electrode and the source and drain electrodes of the selection transistors are in direct contact with the gate dielectric.
  • the gate electrode of the selection transistor and the lower electrode of the memory element can have the same material.
  • the gate electrode of the selection transistor and the lower one Electrode of the memory element each consist of different materials.
  • the preferred exemplary embodiment can be designed such that the source and drain electrodes of the selection transistor and the upper electrode of the memory element have the same material.
  • the source and drain electrodes of the selection transistor on the one hand and the upper electrode of the memory element on the other hand consist of different materials.
  • FIGs. 2a and 2b highly simplified circuit diagrams of two cell "Feider consisting of mxn memory cells each designed according to Figures lb and 2f (already described above). 3 shows a simplified circuit diagram of a cell field, implemented with common bit lines (already described at the beginning);
  • FIGS. 4a-4f are schematic cross sections through differently designed memory cells according to the invention according to FIGS.
  • FIGS. Le and lf are schematic cross sections through differently designed memory cells according to the invention according to FIGS. Le and lf;
  • FIG. 6 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1b, 2a and 4b with a W / L ratio of the selection transistor from FIG. 1;
  • FIG. 7 shows a schematic layout layer of a section of a cell array with memory cells according to the invention according to FIGS. 1b, 2a and 4b with a W / L ratio of the selection transistor of approximately 10.
  • FIG. 8 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1f, 2b and 5c with a W / L ratio of the selection transistor from FIG. 1.
  • FIG. 9 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1f, 2b and 5c with a W / L ratio of approximately 10 and 10 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1c, 3 and 4f with a W / L ratio of the selection transistor from FIG. 1.
  • the memory element and the selection transistor of each memory cell are each with S and T, the bit line with BL, the word line with WL, the field plate with FP, the gate dielectric with GD, the organic semiconductor layer of the field effect transistor T with os and the organic active layer of the memory element S with as.
  • the selection transistors T of all the variants shown in FIGS. 4a-4f are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer os of the selection transistor T is arranged above its gate electrode and its source and drain electrodes are each in direct contact with the gate dielectric GD stand.
  • FIG. 4a shows a schematic cross section of the planar memory cell consisting of the memory element S with the organic active layer as and the selection transistor T with the organic active layer as according to the circuit shown in FIG. 1 a with a field plate FP, which here is the lowest metal layer ( Metal-0).
  • the field dielectric FD forms an insulation between the different metal layers, i. H. 4a shows that the source / drain contacts of the selection transistor T can consist of the same material as the upper electrode of the storage element S. This also applies to the variants according to FIGS 4b and 4c.
  • FIG. 4b shows a schematic cross section of an embodiment according to the invention of the circuit shown in FIG. naren memory cell using the same material for the implementation of the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore necessarily with a digit line DL run parallel to the word line WL.
  • FIGS. 1b and 1c shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using two different materials for realizing the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore with one alternatively parallel to the word line WL or parallel to the bit line BL digit line DL.
  • FIGS. 4d shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using two different materials for the implementation of the gate electrode of the selection transistor T and the upper electrode of the memory element S and therefore with one alternatively parallel to the word line WL or parallel to the bit line BL digit line DL.
  • the lower electrode of the memory element S can have the same material as the drain / source contacts of the selection transistor T.
  • 4e shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using four different materials, each for the implementation of the gate electrode and the source and drain contacts of the selection transistor T and of the upper and lower ones Electrode of the memory element S and therefore with a digit line DL, which is optionally implemented parallel to the word line WL or parallel to the bit line BL.
  • 4f shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS.
  • the embodiment according to FIG. 4f is particularly suitable for the realization of a cell field with common bit lines according to FIG. 3.
  • FIGS. 5a-5e each show a schematic cross section of memory cells designed according to the invention in accordance with the circuits in FIGS. Le and lf.
  • the selection transistor T is also integrated in an inverse-coplanar arrangement in the planar memory cells according to the invention shown in FIGS. 5a and 5e.
  • the reference numerals in Figures 5a-5e are the same as those used in Figures 4a-4f.
  • the digital line DL is optionally routed parallel to the word line WL or parallel to the bit line BL.
  • the source / drain electrode of the selection transistor T can consist of the same material as the upper electrode of the memory element S. According to FIG.
  • the upper electrode of the selection transistor T can consist of the same material as the lower electrode of the memory element S.
  • Die 5b-5e bit line BL is in an upper metallization layer and the word line WL is always in a lowermost metal layer (metal 0).
  • bit line is also in the lowest metal layer (metal 0).
  • planar semiconductor memory cells according to the invention shown in FIGS. 4a-4f and 5a-5e are suitable for realizing a cell field composed of a large number of rows and columns on a substrate.
  • planar memory cells each having a memory element S with an associated selection transistor T integrated in the same plane next to it, the control electrodes of the selection transistors of the individual rows by word lines WL running in the row direction and a controlled electrode of the selection transistors T of the individual columns either with an in Column direction running bit line BL or with a digit line DL or with a field plate FP and one electrode of each memory element with the other controlled electrode of the associated selection transistor T and the other electrode of each memory element S either with a bit line BL or with a digit line DL or is connected to a field plate FP.
  • each memory cell has an organic memory element S with an organic active layer as arranged between the two electrodes and a selection transistor T consisting of a field effect transistor with an organic semiconductor layer os, the selection transistors T and the memory elements S on the substrate, the does not have to be silicon, is integrated as planar elements and is arranged laterally next to one another in one plane.
  • FIGS. 4a-4f and 5a-5e requires the deposition and structuring of the following functional layers on the substrate (not shown).
  • optional layers are written in italics. 1. Metal-0 ⁇ DL or FP or DL; lower electrode of the memory element) 2. Metal-1 (WL and gate electrode of the selection transistor T; possibly DL or lower electrode of the memory element); 3. field dielectric FD (insulation of the various metal layers); 4. Gate dielectric GD (insulation between the gate electrode and the semiconductor layer of the selection transistor T); 5. Active layer as of the storage element S;
  • Metal-2 bit line BL or digit line DL, source and drain contacts of the selection transistor T; upper or, if applicable, lower electrode of the memory element S); 7. Organic semiconductor layer os of the selection transistor T; 8. Metal-3 [BL or DL, upper electrode of the storage element).
  • substrates are glass, polymer film, metal foil (covered with an insulating layer), paper and others
  • Suitable materials In particular, the use of silicon as a substrate is possible, but not necessary.
  • the layers metal-0, metal-1, metal-2 and metal-3 must be metallically conductive, i.e. by depositing inorganic metals (for example aluminum, copper, titanium, gold), conductive oxides (for example indium tin oxide) , or conductive polymers (for example polyaniline).
  • inorganic metals for example aluminum, copper, titanium, gold
  • conductive oxides for example indium tin oxide
  • conductive polymers for example polyaniline.
  • the gate dielectric and the field dielectric must have good insulator properties; inorganic insulators, such as silicon oxide and aluminum oxide, but in particular also insulating polymers, such as polyvinylphenol, are suitable for this.
  • a number of materials can be used as the organic semiconductor layer os for the selection transistor T, in particular pentazene, various oligothiophenes and polythiophene.
  • a number of approaches for capacitive as well as resistive memory effects are currently being discussed for the implementation of the active layer as of the memory element S.
  • All preferred exemplary embodiments of memory cells according to the invention shown in FIGS. 4 and 5 use a planar structure, that is to say the memory element and the selection transistor are integrated lying side by side in one plane on the substrate.
  • the planar Structure In comparison with a vertical structure, in which the memory element and the selection transistor lie - at least partially - one above the other, the planar Structure the advantage that it is much easier to implement from a technological perspective.
  • All of the memory cells shown in FIGS. 4 and 5 use a selection transistor which is manufactured in an inverse-coplanar ("inverted co-planar") design.
  • the organic semiconductor layer os is arranged on the top (above the gate electrode) (inversely to the ordinary silicon field effect transistor in which the gate electrode is arranged on the top), and the source and drain contacts are in direct contact with the gate dielectric GD (in contrast to the staggered version, in which the semiconductor layer is located between the gate dielectric and the source / drain contacts.
  • the inverse-coplanar version is the most frequently used design for organic transistors, but in principle all can be integrated into Fig. 1 implement circuits in memory cells according to the invention with organic selection transistors in any other design.
  • An important criterion in the design of the memory cell is the question of whether the same material is used for the implementation of the gate electrode of the selection transistor T and the lower electrode of the memory element S, or whether two different materials are used.
  • the realization of the memory cell is simpler if the same material (metal-1 in FIGS. 4b and 5c) is used for the gate electrode of the selection transistor and the lower electrode of the memory element, since in this case only one is used to implement both structures Process step becomes necessary. In certain cases, however, it may be necessary to design the gate electrode of the selection transistor T and the lower electrode of the memory element S with two different materials.
  • resistive memories which require the use of very specific materials for the lower electrode of the memory element, such as, for example, copper or indium tin oxide, are discussed in the literature.
  • materials may be unsuitable for the implementation of the gate electrode of the selection transistor and therefore the use of two different materials (metal-0, optimized for the implementation of the lower electrode of the memory element; metal -1, optimized for the implementation of the gate electrode of the selection transistor; see FIGS. 4a, 4c, 4e, 5a, 5d and 5e).
  • metal-0 optimized for the implementation of the lower electrode of the memory element
  • metal -1 optimized for the implementation of the gate electrode of the selection transistor
  • Similar considerations relate to the choice of materials for the implementation of the source and drain contacts of the selection transistor and the upper electrode of the memory element.
  • the realization of the memory cell is easier if the same material (metal-2 in Fig. 4a, 4b, 4c, 5a, 5d, 5d) is used, but in certain cases it may be necessary to use two different materials. In this case too, the designs shown in FIGS. 4 and 5 have to be slightly adapted.
  • FIG. 6 shows in the form of a schematic layout representation a section of a cell array according to the invention made of planar memory cells with circuit arrangements according to FIGS. 1b and 2a and a cross-sectional structure according to FIG. 4b.
  • the cell field shown consists of nine cells organized in three columns (bit lines BL1, BL2, BL3) and three rows (word lines WL1, WL2, WL3) and three digit lines (DL1, DL2, DL3).
  • the selection transistors of a first row of the cell array are each denoted by TU, T12, T13 and the associated memory elements of the first row of the cell array laterally integrated in the same plane are denoted by S11, S12 and S13.
  • W / L the ratio W / L of the channel width W to the channel length L of the selection transistor
  • W / L ratio the ratio W / L of the channel width W to the channel length L of the selection transistor.
  • This W / L ratio of the selection transistor decisively decides on its electrical resistance, that is to say on the amperage which, for a certain combination of gate Source voltage and drain-source voltage flow through the transistor (the current is proportional to the W / L ratio).
  • the design shown allows the implementation of any W / L ratio.
  • 7 shows a section of a cell array according to the invention from planar memory cells in the circuit arrangements according to FIGS.
  • the cell field shown consists of nine memory cells which are organized in three rows and three columns.
  • the channel width W results approximately from the length of the inner outline of the drain contact D, that is to say approximately 2a + b, and the channel length results approximately from the distance between the drain contact D and the source contact S.
  • FIGS. 8 and 9 show schematic layout representations of two cell arrays from planar memory cells according to the invention in accordance with the circuit arrangements in FIGS. 1f and 2b and the cross-sectional structure in accordance with FIG. 5c, the selection transistors in FIG. 8 having a W / L ratio of approximately 1 and in 9 have a W / L ratio of about 10. 8 and 9 also represent a cell array of nine memory cells, organized in three columns and three rows.
  • the selection transistors of a first row (WL1) are each with TU, T12, T13 and the memory elements of this row with S11, S12 and Denoted S13.
  • FIG. 10 schematically shows a cell array with planar memory cells according to the invention, which implement the circuits according to FIGS. 1c and 3 and have the cross-sectional structure according to FIG. 4f.
  • the W / L ratio of the selection transistors is 1.
  • each circuit according to FIGS. 1 a - 1 f and each embodiment of the memory cells according to the invention shown in the cross-sectional representations of FIGS. 4 a - 4 f and 5 a - 5 e can be implemented with any W / L ratio of the selection transistors, so that the in 6-10 are only examples.
  • a process for realizing the cell field shown in the layout of FIG. 6 is explained below as an example.
  • metal 1 active layer as of the memory element S, field dielectric FD, gate dielectric GD, metal 2 and organic semiconductor layer os of the selection transistor T made a chrome mask, which allows the structuring of the deposited layers by means of photolithographic processes.
  • a layer of aluminum, approximately 30 nm thick, is applied to a substrate, for example made of glass, which is structured by means of photolithography and wet-chemical etching in aqueous potassium hydroxide solution, around the first metal layer (metal-1; gate electrode of the selection transistor T; lower electrode of the memory element S; word line WL) to be defined.
  • a substrate for example made of glass, which is structured by means of photolithography and wet-chemical etching in aqueous potassium hydroxide solution, around the first metal layer (metal-1; gate electrode of the selection transistor T; lower electrode of the memory element S; word line WL) to be defined.
  • a suitable organic solvent for example propylene glycol monomethyl ether acetate, PGMEA
  • thermally crosslinked at approximately 200 ° C.
  • the gate dielectric GD is defined below, for example by spinning on and photolithographically structuring an approximately 100 nm thick layer of polyvinylphenol or by applying an approximately 3 nm thick electrically insulating molecular self-assembling monolayer (“seif asembling mono layer”; SAM).
  • Etching defines the second metal layer (metal-2; source and drain contacts of the selection transistor T; bit line BL).
  • an approximately 30 nm thick layer of pentazen is evaporated as the organic semiconductor layer os of the selection transistor and structured by means of photolithography (with the aid of a water-soluble photoresist) and plasma etching.
  • the invention provides a semiconductor memory in which an organic selection transistor, that is to say a field effect transistor with an organic semiconductor layer together with an organic memory element, that is to say an organic active layer arranged between two electrodes, with either capacitive, resistive or based on another physical concept electrical storage behavior can be integrated together to form a planar storage cell on any substrate, which preferably does not consist of silicon. It is particularly important that the selection transistor and memory element are arranged such that the gate electrode of the transistor is designed as a word line and the drain or source contact of the transistor or the electrodes of the memory element are designed either as a bit line, digit line or field plate. LIST OF REFERENCE NUMBERS

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Abstract

Mémoire à semi-conducteurs intégrée comportant un champ de cellules constitué d'une pluralité de cellules de mémoire disposées en lignes et en colonnes. Dans chaque cellule de mémoire, un transistor de sélection organique (T11, T12, T13) qui est un transistor à effet de champ pourvu d'une couche semi-conductrice organique (os) est intégré avec un élément (S11, S12, S13) de mémoire organique, c'est-à-dire une couche organique (as) placée entre deux électrodes possédant un comportement de mémoire électrique sélectivement capacitif ou résistif, pour produire une cellule de mémoire plane située sur un substrat quelconque, de préférence n'étant pas constitué de silicium. Les transistors de sélection (T11, T12, T13) et les éléments (S11, S12, S13) de mémoire de la mémoire à semi-conducteurs selon la présente invention sont ainsi disposés que l'électrode de grille des transistors de sélection (T11, T12, T13) se présente sous forme de ligne de mots (WL1, WL2, WL3) et le contact de drain ou de source des transistors de sélection (T11, T12, T13) ou les électrodes des éléments (S11, S12, S13) de mémoire se présentent sous forme soit de ligne de bits (BL1, BL2, BL3), soit de ligne de nombres, soit de magnétorésistance. Le rapport W/L de la largeur (W) de canal à la longueur (L) de canal des transistors de sélection peut être en principe ajusté de manière voulue.
PCT/DE2005/000926 2004-05-26 2005-05-20 Memoire a semi-conducteurs integree pourvue d'un transistor de selection organique WO2005117024A1 (fr)

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DE102004025676A DE102004025676B4 (de) 2004-05-26 2004-05-26 Integrierter Halbleiterspeicher mit organischem Auswahltransistor
DE102004025676.4 2004-05-26

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PCT/DE2005/000926 WO2005117024A1 (fr) 2004-05-26 2005-05-20 Memoire a semi-conducteurs integree pourvue d'un transistor de selection organique

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DE (1) DE102004025676B4 (fr)
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001073845A1 (fr) * 2000-03-28 2001-10-04 Koninklijke Philips Electronics N.V. Circuit integre a element de memoire programmable
US20030081450A1 (en) * 2001-10-25 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device for conducting data write operation by application of a magnetic field
WO2003046922A2 (fr) * 2001-11-16 2003-06-05 Infineon Technologies Ag Montage a semi-conducteurs avec transistors a base de semi-conducteurs organiques et de cellules de memoire d'ecriture-lecture non volatiles
WO2003052827A1 (fr) * 2001-12-18 2003-06-26 Matsushita Electric Industrial Co., Ltd. Memoire non volatile
US20030178660A1 (en) * 2002-03-22 2003-09-25 Gunter Schmid Semiconductor memory cell and semiconductor memory device
WO2004015778A1 (fr) * 2002-08-07 2004-02-19 Canon Kabushiki Kaisha Dispositif de memoire remanente
WO2005060001A1 (fr) * 2003-12-18 2005-06-30 Canon Kabushiki Kaisha Dispositif a memoire non volatile
WO2005064681A2 (fr) * 2003-12-22 2005-07-14 Koninklijke Philips Electronics N.V. Methode de fabrication d'un dispositif a memoire ferroelectrique remanente et dispositif a memoire ainsi produit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001073845A1 (fr) * 2000-03-28 2001-10-04 Koninklijke Philips Electronics N.V. Circuit integre a element de memoire programmable
US20030081450A1 (en) * 2001-10-25 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device for conducting data write operation by application of a magnetic field
WO2003046922A2 (fr) * 2001-11-16 2003-06-05 Infineon Technologies Ag Montage a semi-conducteurs avec transistors a base de semi-conducteurs organiques et de cellules de memoire d'ecriture-lecture non volatiles
WO2003052827A1 (fr) * 2001-12-18 2003-06-26 Matsushita Electric Industrial Co., Ltd. Memoire non volatile
US20040196688A1 (en) * 2001-12-18 2004-10-07 Matsushita Electric Industrial Co., Ltd. Non-volatile memory
US20030178660A1 (en) * 2002-03-22 2003-09-25 Gunter Schmid Semiconductor memory cell and semiconductor memory device
WO2004015778A1 (fr) * 2002-08-07 2004-02-19 Canon Kabushiki Kaisha Dispositif de memoire remanente
WO2005060001A1 (fr) * 2003-12-18 2005-06-30 Canon Kabushiki Kaisha Dispositif a memoire non volatile
WO2005064681A2 (fr) * 2003-12-22 2005-07-14 Koninklijke Philips Electronics N.V. Methode de fabrication d'un dispositif a memoire ferroelectrique remanente et dispositif a memoire ainsi produit

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