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WO2005015718A2 - Circuit de maintien du temps de retention, tout en reduisant les dimensions du condensateur de chargement et ameliorant l'efficacite d'une unite d'alimentation - Google Patents

Circuit de maintien du temps de retention, tout en reduisant les dimensions du condensateur de chargement et ameliorant l'efficacite d'une unite d'alimentation Download PDF

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Publication number
WO2005015718A2
WO2005015718A2 PCT/IB2004/003498 IB2004003498W WO2005015718A2 WO 2005015718 A2 WO2005015718 A2 WO 2005015718A2 IB 2004003498 W IB2004003498 W IB 2004003498W WO 2005015718 A2 WO2005015718 A2 WO 2005015718A2
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WO
WIPO (PCT)
Prior art keywords
converter
terminal
capacitor
voltage
diode
Prior art date
Application number
PCT/IB2004/003498
Other languages
English (en)
Other versions
WO2005015718A3 (fr
Inventor
Vijay Phadke
Original Assignee
Astec International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Astec International Limited filed Critical Astec International Limited
Priority to GB0601296A priority Critical patent/GB2420666B/en
Publication of WO2005015718A2 publication Critical patent/WO2005015718A2/fr
Publication of WO2005015718A3 publication Critical patent/WO2005015718A3/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0096—Means for increasing hold-up time, i.e. the duration of time that a converter's output will remain within regulated limits following a loss of input power
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates in general to power converter circuits and more particularly to a circuit that utilizes a boost converter front end to provide power factor correction.
  • a conventional AC to DC power converter typically includes a boost converter 15 front end for power factor correction of the input bulk voltage generated from the AC input power source and a downstream DC to DC converter to convert the unregulated bulk voltage into an output voltage that satisfies the voltage regulation and transient response requirements of the power converter.
  • the DC output voltage 20 generated by the downstream DC to DC converter is expected to stay in regulation for a predefined amount of time after the input power source has failed.
  • a bulk capacitor in the power converter typically provides the necessary temporary power for the downstream DC to DC converter as it discharges.
  • the minimum hold-up time is required to be the time 25 necessary to maintain voltage regulation for at least one missing AC cycle of the input AC power source.
  • this hold-up time is typically at least 16 mS for a 60Hz line frequency AC power source and 20 mS for a 50Hz line frequency AC power source.
  • FIG. 1 shows a prior art AC to DC power converter 10 that includes a bulk 30 capacitor Cl for providing the desired hold-up time.
  • the rectified input AC voltage is boosted by a power factor correcting boost converter, comprising an inductor LI, a switch SW1, a diode Dl, and a bulk capacitor Cl. This boosted bulk voltage across
  • PALOALTO 4073768V1 bulk capacitor Cl is input to the DC to DC converter.
  • the DC to DC converter responds to this falling voltage by expanding its duty cycle in order to maintain output voltage regulation.
  • the duty cycle 5 reaches its maximum limit and output voltage regulation is no longer maintained. This lowest operating voltage point determines how much energy in the bulk capacitor Cl can be utilized for hold-up.
  • Some power supply topologies, such as a flyback power converter can operate up to a very wide duty cycle, with certain penalties on performance.
  • Other topologies, 10 such as the forward converter, cannot operate over a very wide duty cycle since, for very wide duty cycle variations, the efficiency drops significantly due to high peak currents.
  • a typical value for a bulk capacitor Cl is 2350uF and is comprised of 5 electrolytic capacitors of 470uF each. 25 Typical efficiencies of 88% are obtained for such converters.
  • ZNS zero voltage switching
  • FIG. 2 shows another prior art AC to DC power converter 20 having three stages of power conversion, including a second stage buck converter between a front- 5 end boost converter and a downstream DC to DC converter.
  • the second stage buck converter comprises a switch SW2, a diode D3, an inductor L2, and a capacitor C2.
  • the buck converter operates to step down the bulk voltage on the bulk capacitor Cl to a much lower value.
  • the buck converter provides the downstream DC to DC converter with a well-regulated input voltage across capacitor C2.
  • the buck converter must operate at a duty cycle close to 50%, e.g. bucking the voltage from 400N to 200N, in order to enable a reduced bulk capacitor to be used, a large value is required for inductor L2 and capacitor C2.
  • FIG. 3 shows another prior art AC to DC power converter 30 that includes a 30 bulk capacitor C2 for providing the desired hold-up time.
  • Power converter 30 includes a front end power factor-correction first boost converter having an inductor LI, a switch SW1, a diode Dl, and a bulk capacitor Cl.
  • Power converter 30 generates a boosted bulk voltage across a capacitor Cl, and at the same time, charges an energy
  • a second boost converter includes an inductor L2, a switch SW2, and a diode D4 as boosting elements.
  • the control loop of the second boost converter is set at a much lower voltage regulation point than that of first boost converter stage.
  • this voltage regulation point is 5 set at a level that is marginally higher than the regulation break voltage point of a conventional DC to DC converter. For example, if the nominal bulk voltage is Nb and the regulation break voltage point of the conventional DC to DC converter is 0J5Nb, the voltage regulation point of the second boost converter is set at around 0.8Nb.
  • the second boost converter stage is always 10 off and does not generate any power dissipation.
  • bulk capacitor Cl in power converter 30 continues to discharge while providing hold-up power to the DC to DC converter.
  • the second boost converter starts to regulate using the energy from storage capacitor C2. Since this second boost converter stage can operate up to a 15 very wide duty cycle, it can regulate the voltage across bulk capacitor Cl until most of the energy in storage capacitor C2 is utilized.
  • power converter 30 provides an extended hold-up time while reducing the bulk capacitor size. Power converter 30 does, however, have several drawbacks as are illustrated with reference to FIGs. 3 and 4. 20 FIG.
  • FIG. 4 is a timing diagram for power converter 30 in FIG. 3 that illustrates the operation of converter 30 in more detail, where Nb is shown as Nbulk.
  • power converter 30 requires two sets of capacitors, bulk capacitor Cl for normal operation filtering and hold-up and capacitor C2 for energy storage during an extended hold-up period.
  • capacitor Cl and capacitor C2 do not share the power handling equally.
  • diode D3 adds an extra voltage drop in the path of capacitor C2, and thus power converter 30 functions less efficiently.
  • capacitor C2 will operate with capacitor Cl well, 30 since the rate of discharge of capacitor Cl is high and capacitor C2 effectively becomes parallel to capacitor Cl when it is discharging.
  • capacitor Cl still must be sized to handle most of the ripple current of the first boost converter stage.
  • the ripple is typically twice the line frequency, i.e.,
  • PALOALTO 4073768V1 100Hz for a 50Hz AC source line frequency and 120Hz for a 60Hz AC source.
  • the ripple current rating and operating life parameters for the converter set the minimum possible size of capacitor Cl in power converter 30.
  • Another drawback of power converter 30 is that it requires an extra storage 5 capacitor C2 which must be large enough to store enough energy to provide the required additional hold-up time.
  • Still another drawback of power converter 30 is that it does not reduce the operational range of the DC to DC converter less than for other prior art converters. As a result, power converter 30 does not provide any performance gain over prior art converters. 10 For example, a typical power factor corrected, 3KW power supply receiving input power from a standard AC outlet and configured as shown in FIG.
  • FIG. 5 shows a circuit diagram for a prior art AC-DC power converter 40 that provides line harmonic correction.
  • Power converter 40 comprises a power factor corrected flyback converter that switches directly on the rectified AC input pulses.
  • Power converter 100 includes a transformer Tl having a primary winding, a secondary winding, and an auxiliary winding, each 25 having a first and a second end.
  • the auxiliary winding provides the energy for recharging the capacitor Cl during each flyback cycle of the flyback converter 40.
  • the primary winding of transformer Tl in FIG. 5 is conventionally switched on and off at a predetermined frequency by means of a first switch SW1.
  • the control signal input to switch SW1 is typically a conventional pulse width 30 modulation (PWM) or power factor correction (PFC) type drive signal (details not shown).
  • PWM pulse width 30 modulation
  • PFC power factor correction
  • the secondary winding of transformer Tl is connected to a rectifying and filter circuit comprising a diode D3 and a capacitor C2, to produce the rated DC output voltage.
  • PALOALTO 4073768v1 The charging of capacitor Cl in power converter 40 to a predetermined voltage is controlled by the circuit comprising the auxiliary winding, and a resistor Rl connected in series with a second switch SW2 and a diode Dl between one end of the auxiliary winding and one terminal of capacitor Cl.
  • the other terminal of capacitor 5 Cl is connected to the second end of the auxiliary winding.
  • Diode D3 delivers power to a load as connected at the output terminals and stores energy in output capacitor C2.
  • switch SW1 is open
  • switch SW2 is turned on and capacitor Cl is charged to a predetermined voltage determined by the turns ratio between the primary winding and the auxiliary winding.
  • switch SW2 turns on only during the flyback period of converter 40.
  • the voltage on capacitor Cl is usually selected low (around 50N or so). In normal operation, when the instantaneous voltage of the rectified AC pulse is higher than the voltage at which capacitor Cl is charged, diode D2 is reverse biased. Capacitor Cl will continue to hold its charge during this time.
  • capacitor Cl When this instantaneous voltage falls below the capacitor Cl voltage near the "valley point" of the rectified AC pulse, 20 diode D2 becomes forward biased. As a result, capacitor Cl provides energy to transformer Tl to continue operation during this time. Capacitor Cl thus provides hold-up time during this period. Switch SW2 can also be held off when the charge on capacitor Cl is being used by converter 40 in order to reduce the peak currents in the transformer Tl . 25
  • capacitor Cl fails to provide the larger hold-up time required in most applications. If capacitor Cl is to provide a large hold-up time, then a large capacitor will be needed, since the voltage charge on capacitor Cl is very close to the voltage that exists at the bottom of the rectified pulse.
  • the circuit in FIG. 5 can be improved using an extra boost conversion stage as taught in FIG. 1 in such a way that it extends the hold-up time of the converter 40, while reducing the bulk capacitor size.
  • the additional stage would also improve the efficiency of the downstream DC to DC converter, while reducing the size of its
  • PALOALTO 4073768V1 output filter components PALOALTO 4073768V1 output filter components.
  • a circuit is therefore needed that will enable use of most of the energy stored in the bulk capacitor to thereby reduce bulk capacitor size requirements, while also 5 improving efficiency.
  • the present invention discloses a three-stage power converter that comprises a first boost converter stage, a second boost converter stage, and a third DC to DC converter stage, where the second boost converter provides a boosted voltage across 10 the second capacitor when the voltage across said bulk capacitor is below a predetermined voltage level, thereby causing the voltage on the second boost converter output to be regulated at said predetermined voltage level.
  • the second boost converter stage is turned off most of the time during normal operation through a diode in the second boost converter stage for extending the hold-up time while 15 reducing the size of the capacitor in the second boost converter stage. This is accomplished by setting the voltage regulation point of the second boost converter stage to a valley point of a low frequency ripple on a bulk voltage delivered by a bulk capacitor in the first booster stage given that the second stage would detect an over- voltage on the output.
  • the second boost stage will become active and will maintain the voltage level flat in the valley due to the fast control loop in the second boost converter stage.
  • the second boost converter or an intermediate converter boosts the falling voltage to maintain the DC input to the DC to DC converter 25 between a narrow operating range and increases the operating duty cycle, so as to increase efficiency, reduce peak current and voltage stresses, reduce the size of output filter components and reduce the size of the bulk capacitance by up to half.
  • the present invention solves the problem of bulk capacitor size and power efficiency in a power converter by providing a circuit that more efficiently enables a 30 significantly larger amount of the energy stored in the bulk capacitor to be used whenever there has been an input power failure. As a result, a much smaller bulk capacitor can be used to obtain the same hold-up time for the voltage output by the
  • PALOALTO 4073768V1 converter while achieving increased efficiency.
  • a much larger hold-up time can be attained for the same sized bulk capacitor.
  • An advantage of the inventive circuit is that it enables the converter to switch at a very high duty cycle, and thereby keep on delivering power to the converter's 5 output terminals until the bulk capacitor has discharged to a very low level.
  • Another advantage of the present invention is that it improves the efficiency of the DC to DC converter by reducing its input voltage operating range.
  • Another advantage of the present invention is that it reduces the peak current and voltage stresses on the DC to DC converter components. 10
  • Another advantage of the present invention is that it reduces the size of the output filter components because of a higher steady state duty cycle.
  • FIG. 1 is a schematic of a prior art AC to DC power converter that includes a bulk capacitor for providing a hold-up time
  • FIG. 2 shows a prior art AC to DC power converter having three stage conversion including a second stage buck converter between a front-end boost 20 converter and a DC to DC converter
  • FIG. 3 shows a prior art AC to DC power converter which includes a bulk capacitor for providing a hold-up time and which further includes a standby boost converter stage
  • FIG. 4 is a timing diagram that illustrates the operation of the power converter 25 30 of FIG.
  • FIG. 5 shows a circuit diagram for a prior art flyback converter that provides line harmonic correction and includes a capacitor that provides some hold-up time
  • FIG. 6 is a preferred embodiment of the circuit according to present invention for enabling the size of a power converter's bulk capacitor to be reduced while 30 providing improved efficiency
  • FIG. 7 is a timing diagram illustrating the regulation point of the second stage boost converter for the circuit embodiment shown in FIG. 6;
  • FIG. 8 is a timing diagram showing the voltage across the capacitor of the second stage converter in the circuit shown in FIG. 6;
  • FIG. 9 is a timing diagram illustrating the voltage across the bulk capacitor and the regulation point of the second stage boost converter for the circuit shown in FIG. 6 5 where the voltage regulation point of the second boost stage is set slightly below the lowest valley point of the line frequency ripple such that it will always be inactive in normal operation.
  • DETAILED DESCRIPTION OF THE INVENTION A preferred embodiment of a circuit according to the present invention is 10 shown at 100 in FIG. 6.
  • Converter 100 includes a first stage boost converter 110, a downstream DC to DC converter 130, and a second stage converter 120 inserted between the first stage boost converter 110 and the DC to DC converter 130.
  • a rectified input AC voltage is boosted by the first stage boost converter 110, comprising an inductor LI 112, a switch SW1 114, a diode Dl 116, and a bulk 15 capacitor Cl 118.
  • the first stage boost converter 110 provides a boosted bulk voltage across capacitor Cl 118.
  • the second stage converter 120 of converter 100 is preferably a boost converter comprising an inductor L2 122, a switch SW2 124, a diode D3 126, and a decoupling capacitor C2 128. As shown in FIG. 6, the DC to DC converter 130 is coupled between the output and the second stage boost converter 120.
  • the downstream DC to DC converter 130 includes a conventional power drive circuit coupled between the second stage boost converter 120 and the primary winding 136 of a transformer Tl 134.
  • the secondary winding 138 of transformer Tl 134 is connected to a conventional rectifier filter rail circuit to produce the rated DC output voltage.
  • Power converter 100 includes a diode D2 118 and diode D4 128.
  • Diode D2 25 118 is connected in parallel with the series combination of inductor LI 112 and diode Dl 116 of the first stage boost converter 110.
  • Diode D2 118 functions only during an inrush current condition that occurs when the power supply turns on, in order to avoid saturating inductor LI 112 at startup.
  • Diode D4 128 is a bypass diode connected in parallel with the series combination of inductor L2 122 and diode D3 126 of the 30 second stage converter 120. It functions to bypass the second stage converter 120 when the converter is not operating. In operation, after the input AC voltage fails, the bulk capacitor Cl 118 starts to discharge and the voltage across it starts to fall. The control signal input to switch
  • PALOALTO 4073768V1 SW1 114 is typically a conventional PWM or PFC type drive signal (details not shown).
  • the first stage boost converter 110 is PFC controlled.
  • the output DC voltage across capacitor Cl 118 typically exhibits a low frequency ripple due to the slow control loop of the first stage boost converter 110, which is designed to sense 5 voltage and current variation of an AC input line frequency of typically 50Hz or 60Hz and ignore the twice line frequency ripple.
  • a much smaller bulk capacitor can be used to obtain the same hold-up time for the voltage output by the converter.
  • the bulk voltage on Cl 118 has a considerable amount of low frequency ripple at higher loads. 10 As shown in FIG.
  • the voltage regulation point of the second stage boost converter 120 is preferably set in the valley point of the low frequency ripple on the bulk voltage delivered by capacitor Cl 118.
  • the second stage boost converter 120 is turned off by its control loop since it sees an overvoltage on its output.
  • Diode D4 128 provides a bypass current path 15 when the second stage boost converter 120 is not operating.
  • the second stage boost converter 120 will become active and will maintain the voltage level flat in the valley due to its fast control loop.
  • the resultant voltage across capacitor C2 128, which provides power to the downstream DC to DC converter stage 20 130, is shown in FIG. 8.
  • the voltage across capacitor C2 128 provided to the downstream DC to DC converter 130 always stays within a narrow band bounded by Nmax and Nmin. If the first stage boost converter 110 is subjected to step loads or line transients at the input, the voltage on the bulk capacitor Cl 118 can see an overvoltage. During 25 such short instances, the duty cycle of the DC to DC converter 130 can shrink and then recover. For normal operation, however, the input voltage span is quite narrow, thus, the DC to DC converter 130 can operate at close to its maximum duty cycle, thereby reducing peak current and voltage stresses. As a result, the present invention enables the size of the components of the conventional output rectifier filter rail 30 (details not shown) to be reduced. Thus, the circuit shown in FIG. 6 uses only one bulk capacitance Cl 118 which is rated to handle the required ripple current stress in worst case normal operation, while storing sufficient energy to provide the required hold-up time
  • capacitor C2 128 can be very small. Due to very low duty cycle for switch SW2 124, the ripple current stress on capacitor C2 128 is very small. As a result, capacitor C2 128 can be a small electrolytic capacitor or even a ceramic/plastic film capacitor. 5 For example, an exemplary power factor corrected, 3KW power supply, receiving input power from a standard AC outlet, as shown in FIG.
  • the circuit shown in FIG. 6 enables the DC to 15 DC converter 130 to operate over a narrow range, thereby increasing efficiency 0.8% for the exemplary circuit as compared to the highest efficiency obtained with the prior art converters shown in FIGs. 1, 2, 3, and 5.
  • modern AC to DC and DC to DC power supplies require ever increasing power density, thereby requiring increasingly higher switching frequencies 20 in order to reduce the size of the components.
  • the second stage boost converter 120 shown in FIG. 6 comprised of inductor L2 122, switch SW2 124, and diode D3 126, operates only during the hold-up time, experiments conducted by the inventor demonstrated that if the switching frequency is high enough, e.g., 300 kHz used experimentally, a small value of capacitor C2 128 is sufficient.
  • the voltage regulation point of the second stage boost converter may alternatively be set slightly below the lowest valley point of the line frequency ripple, such that the second stage boost converter is always inactive in normal operation.
  • This mode of operation is illustrated in the timing diagram shown in FIG. 9.
  • the second stage boost converter 120 starts to regulate only after the AC input fails and the bulk voltage across capacitor Cl 118 drops to the regulation point of the second stage boost converter 128.
  • a difference between this alternative mode of operation and the operation of the circuit in FIG. 3 is that the circuit in FIG. 6
  • PALOALTO 4073768V1 requires only one bulk capacitance Cl 118 instead of the two energy storage capacitors required by the circuit shown in FIG. 3.
  • another capacitor, C2 128, is required in the circuit in FIG. 6, the second stage converter 120 requires only a very small electrolytic capacitor or even a very small ceramic/plastic film capacitor for 5 C2 128 for decoupling.
  • the value of capacitor C2 128 is 2JuF, which is substantially below the 470uF value for the energy storage capacitor C2 128 that is used in the circuits in FIGs. 2 and FIG. 3, as described above.
  • the circuit shown in FIG. 6 reduces the bulk capacitance size, saves valuable space in a high power density power supply, and reducing cost significantly, while increasing 10 efficiency.
  • the mode of operation for the present invention that works best depends on the requirements of a particular application. Typical requirements are minimizing power loss, minimizing bulk capacitor size, or maximizing the hold-up time, or a combination thereof.
  • the second stage boost converter shown in the embodiment in FIG. 6 is preferably a discontinuous mode design. Alternatively, a suitable continuous inductor current design may be used. For an embodiment having a discontinuous inductor current converter for the second stage boost converter 120, a low cost, fast recovery diode could be used for diode D3 126. In the mode of operation wherein the second 20 boost stage switching occurs only in the valley of low frequency ripple, as illustrated in FIG. 7, the losses for such conversion would be very low.
  • switch SW2 124, inductor L2 122, and diode D3 126 in the second stage boost converter 120 could be very small.
  • the present invention provides the required hold-up time while 25 reducing the bulk capacitance and improving the efficiency of the DC to DC conversion.
  • the present invention provides the advantage of reducing the size of the output filter components, transformers, 30 rectifiers, etc.
  • the present invention could be used in any power supply which uses a first stage boost converter.
  • the second stage converter 120 is not limited to a boost converter topology.
  • in place of the second stage boost in place of the second stage boost
  • PALOALTO 4073768V1 converter 120 a buck-boost converter could be used in such a way that it normally bucks down the output voltage of the first stage boost converter to a lower value.
  • this alternative second stage provides a regulated, narrow band DC voltage to the downstream DC to DC converter 130.
  • this alternative circuit can switch and become a boost converter to boost the falling voltage and maintain the regulated DC input to the DC to DC converter 130.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Ce circuit utilise la plus grande partie de l'énergie stockée dans le condensateur de chargement d'une unité d'alimentation à convertisseur de courant alternatif en courant continu ou de courant continu en courant continu au moyen d'un convertisseur intermédiaire monté entre un convertisseur d'appoint de premier étage et un convertisseur CC-CC. Lorsque la tension de chargement commence à tomber pendant le temps de rétention, le convertisseur intermédiaire élève la tension en chute afin de maintenir l'entrée de CC réglé dans le convertisseur CC-CC, tout en réduisant la plage de fonctionnement et en augmentant le facteur d'utilisation, de façon à améliorer l'efficacité, réduire la sollicitation par les courants et tensions de crête, réduire la taille des composants de filtrage de sortie et réduire de moitié les dimensions du condensateur du chargement.
PCT/IB2004/003498 2003-08-08 2004-08-06 Circuit de maintien du temps de retention, tout en reduisant les dimensions du condensateur de chargement et ameliorant l'efficacite d'une unite d'alimentation WO2005015718A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0601296A GB2420666B (en) 2003-08-08 2004-08-06 A circuit for maintaining hold-up time while reducing bulk capacitor size and improving efficiency in a power supply

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US49353703P 2003-08-08 2003-08-08
US60/493,537 2003-08-08

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WO2005015718A2 true WO2005015718A2 (fr) 2005-02-17
WO2005015718A3 WO2005015718A3 (fr) 2006-08-17

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GB2436176A (en) * 2006-03-10 2007-09-19 Commergy Technologies Ltd Power converter with a buck power factor correction stage
US20120039095A1 (en) * 2010-08-12 2012-02-16 Samsung Electro-Mechanics Co., Ltd. Boost converter
CN103190200A (zh) * 2010-11-03 2013-07-03 皇家飞利浦电子股份有限公司 用于驱动负载尤其是led单元的驱动器设备和驱动方法
CN106300982A (zh) * 2015-06-05 2017-01-04 台达电子工业股份有限公司 具有延长维持时间功能的电源供应装置
WO2022098148A1 (fr) * 2020-11-05 2022-05-12 엘지이노텍 주식회사 Convertisseur à pont complet à décalage de phase

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