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WO2005091974A2 - Procedes d'optimisation de la gravure d'un substrat dans un systeme de traitement au plasma - Google Patents

Procedes d'optimisation de la gravure d'un substrat dans un systeme de traitement au plasma Download PDF

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Publication number
WO2005091974A2
WO2005091974A2 PCT/US2005/007886 US2005007886W WO2005091974A2 WO 2005091974 A2 WO2005091974 A2 WO 2005091974A2 US 2005007886 W US2005007886 W US 2005007886W WO 2005091974 A2 WO2005091974 A2 WO 2005091974A2
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WO
WIPO (PCT)
Prior art keywords
hard mask
layer
etchant
barrier layer
barrier
Prior art date
Application number
PCT/US2005/007886
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English (en)
Other versions
WO2005091974A3 (fr
WO2005091974A9 (fr
Inventor
Jisoo Kim
Binet Worsham
Bi-Ming Yen
Peter K. Loewenhardt
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Lam Research Corporation
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Filing date
Publication date
Application filed by Lam Research Corporation filed Critical Lam Research Corporation
Priority to JP2007503965A priority Critical patent/JP5134363B2/ja
Priority to KR1020067019324A priority patent/KR101221158B1/ko
Priority to CN2005800085422A priority patent/CN1997771B/zh
Publication of WO2005091974A2 publication Critical patent/WO2005091974A2/fr
Publication of WO2005091974A9 publication Critical patent/WO2005091974A9/fr
Publication of WO2005091974A3 publication Critical patent/WO2005091974A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Definitions

  • the present invention relates in general to substrate manufacturing technologies and in particular to methods for the optimization of substrate etching in a plasma processing system.
  • a substrate e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing
  • plasma is often employed.
  • the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit.
  • the substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited (deposition) in order to form electrical components thereon.
  • a substrate is coated with a thin film of hardened emulsion (i.e., such as a photoresist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing components of the underlying layer to become exposed.
  • the substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck or pedestal.
  • Appropriate etchant source are then flowed into the chamber and struck to form a plasma to etch exposed areas of the substrate.
  • FIG. 1 a simplified diagram of plasma processing system components is shown.
  • an appropriate set of gases is flowed into chamber 102 through an inlet 108 from gas distribution system 122.
  • These plasma processing gases may be subsequently ionized to form a plasma 110, in order to process (e.g., etch or deposition) exposed areas of substrate 114, such as a semiconductor substrate or a glass pane, positioned with edge ring 115 on an electrostatic chuck 116.
  • liner 117 provides a thermal barrier between the plasma and the plasma processing chamber, as well as helping to optimize plasma 110 on substrate 114.
  • Gas distribution system 122 is commonly comprised of compressed gas cylinders 124a-f containing plasma processing gases (e.g., C 4 F 8 , C 4 F 6 , CHF 3 , CH2F 3 , CF 4 , HBr, CH 3 F, C 2 F 4 , N 2 , O 2 , Ar, Xe, He, H 2) NH 3 , SF 6 , BC1 3 , Cl 2 , WF 6 , etc.). Gas cylinders 124a- f may be further protected by an enclosure 128 that provides local exhaust ventilation.
  • plasma processing gases e.g., C 4 F 8 , C 4 F 6 , CHF 3 , CH2F 3 , CF 4 , HBr, CH 3 F, C 2 F 4 , N 2 , O 2 , Ar, Xe, He, H 2
  • Gas cylinders 124a- f may be further protected by an enclosure 128 that provides local exhaust ventilation.
  • Mass flow controllers 126a-f are commonly a self-contained devices (consisting of a transducer, control valve, and control and signal-processing electronics) commonly used in the semiconductor industry to measure and regulate the mass flow of gas to the plasma processing system.
  • Injector 109 introduces plasma processing gases 124 as an aerosol into chamber 102.
  • Induction coil 131 is separated from the plasma by a dielectric window 104, and generally induces a time-varying electric current in the plasma processing gases to create plasma 110.
  • the window both protects induction coil from plasma 110, and allows the generated RF field to penetrate into the plasma processing chamber.
  • matching network 132 Further coupled to induction coil 131 at leads 130a-b is matching network 132 that may be further coupled to RF generator 138.
  • Matching network 132 attempts to match the impedance of RF generator 138, which typically operates at 13.56 MHz and 50 ohms, to that of the plasma 110.
  • some type of cooling system is coupled to the chuck in order to achieve thermal equilibrium once the plasma is ignited.
  • the cooling system itself is usually comprised of a chiller that pumps a coolant through cavities in within the chuck, and helium gas pumped between the chuck and the substrate.
  • the helium gas also allows the cooling system to rapidly control heat dissipation. That is, increasing helium pressure subsequently also increases the heat transfer rate.
  • Most plasma processing systems are also controlled by sophisticated computers comprising operating software programs. In a typical operating environment, manufacturing process parameters (e.g., voltage, gas flow mix, gas flow rate, pressure, etc.) are generally configured for a particular plasma processing system and a specific recipe.
  • dielectric layers are electrically connected by a conductive plug filling a via hole.
  • a conductive plug filling a via hole.
  • an opening is formed in a dielectric layer, usually lined with a TaN or TiN barrier, and then subsequently filled with a conductive material (e.g., aluminum (Al), copper (Cu), etc.) that allows electrical contact between two sets of conductive patterns.
  • a conductive material e.g., aluminum (Al), copper (Cu), etc.
  • CMP chemical mechanical polishing
  • a blanket layer of silicon nitride is then deposited to cap the copper.
  • via-first there are generally three commonly used approaches for manufacturing dual damascene substrates: via-first, trench-first, and self-align.
  • the substrate is first coated with photoresist and then the vias are lithographically patterned.
  • an anisotropic etch cuts through the surface cap material and etches down through the low-k layer of the substrate, and stops on a silicon nitride barrier, just above the underlying metal layer.
  • the via photoresist layer is stripped, and the trench photoresist is applied and lithographically patterned.
  • the via may be covered by an organic ARC plug, in order to prevent the lower portion via from being over-etched during the trench etch process.
  • a second anisotropic etch then cuts through the surface cap material and etches the low-k material down to a desired depth. This etch forms the trench.
  • the photoresist is then stripped and the Silicon Nitride barrier at the bottom of the via is opened with a very soft, low-energy etch that will not cause the underlying copper to sputter into the via.
  • the trench and via are filled with a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) and polished by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • An alternate methodology is trench-first.
  • the substrate is coated with photoresist and a trench lithographic pattern is applied.
  • An anisotropic dry etch then cuts through the surface hard mask (again typically SiN, TiN or TaN) followed by stripping the photoresist.
  • Another photoresist is applied over the trench hard mask and then the vias are lithographically patterned.
  • a second anisotropic etch then cuts through cap layer and partially etches down into the low-k material. This etch forms the partial vias.
  • the photoresist is then stripped for trench etch over the vias with the hard mask.
  • the trench etch then cuts through the cap layer and partially etches the low-k material down to desired depth.
  • trench-first methodology also requires near-perfect trench-to-via alignment in order to properly etch the via.
  • Yet another methodology is called self-align.
  • This method combines the oxide etch steps but requires two separate ILD (interlevel dielectric) depositions with an intervening nitride mask and etch step.
  • the lower (via) dielectric is deposited with a nitride etch stop on both top and bottom.
  • the top nitride is masked and etched to form a via hard mask. This requires a special nitride etch process.
  • the top (line) dielectric is deposited.
  • the trench mask is aligned with the via openings that have been etched in the nitride, and both the trench and vias are etched in both layers of oxide with one etch step.
  • FIG. 2A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step.
  • terms such as "above” and "below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
  • a layer 208 comprising a semiconductor, such as SiO 2 .
  • a barrier layer 204 typically comprising nitride or carbide (e.g., SiN, SiC, etc.).
  • Dual damascene substrates further comprise a set of metal layers including Ml 209a-b, typically comprising aluminum or copper.
  • a intermediate dielectric (IMD) layer 206 comprising a low-k material (e.g., SiOC, etc.).
  • IMD layer 206 there may be placed a cap layer 203, typically comprising SiO .
  • a trench mask layer 202 typically comprising TiN, SiN, or TaN.
  • FIG. 2B shows a somewhat idealized cross-sectional view of the layer stack of
  • FIG. 2A after photoresist layer 220 and a BARC layer 222 is further added.
  • FIG. 2C shows a somewhat idealized cross-sectional view of the layer stack of
  • FIG. 2B after photoresist layer 220 and BARC layer 212 have been processed through lithography.
  • a photoresist mask pattern is created with a set of trenches 214a- b.
  • FIG. 2D shows the cross-sectional view of the layer stack of FIG. 2C after trench mask layer 201 has been processed in the plasma system, further extending trench 214a- b to cap layer 203.
  • FIG. 2E shows the cross-sectional view of the layer stack of FIG. 2D, after photoresist layer 220 and a BARC layer 212 are removed.
  • FIG. 2F shows the cross-sectional view of the layer stack of FIG. 2E after a second photoresist layer 216 and a BARC layer 218 are disposed, in order to create a second metal layer and a via connecting it to the first metal layer 209a-b.
  • FIG. 2G shows the cross-sectional view of the layer stack of FIG. 2F after the photoresist layer has been opened and an etch has been performed to partially etch into IMD layer 206 to create a via.
  • FIG. 2H shows the cross-sectional view of the layer stack of FIG. 2G after photoresist layer 216 and BARC layer 218 have been stripped, and an additional etch process has been performed to extend the trench to a desired depth and etch through a via stopping on barrier layer 204.
  • the barrier layer 204 is etched through using, for example CH 2 F 2 ,
  • a chemical mechanical polish process has been performed to polish the layer stack down to cap layer 203, and a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) has been deposited to contact the existing Ml metal material.
  • a conductive material e.g., aluminum (Al), Copper (Cu), etc.
  • the process of removing photoresist and BARC can often damage low-k material in the substrate.
  • low-k material consists of a large concentration of carbon and hydrogen, which helps to improve mechanical strength to current flow and minimizes cross talk between conductor lines.
  • oxygen used in conventional photoresist stripping processes may react with the carbon in the photoresist to create volatile CO gas and substantially reduces the carbon concentration in exposed areas. Since, lowering carbon content may also substantially increase the corresponding k value, photoresist removal may detrimentally increase the RC time delay.
  • FIG. 3 A the a cross-sectional view of a layer stack, as shown in FIG. 2, in which fencing 302 has occurred.
  • FIG. 3B the a cross-sectional view of a layer stack, as shown in FIG. 2, in which corner erosion 304 has occurred.
  • the invention relates, in one embodiment, to a method of etching a substrate in a plasma processing system.
  • the substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer.
  • the method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.
  • FIG. 1 illustrates a simplified diagram of plasma processing system components
  • FIG. 2A illustrates an idealized cross-sectional view of a layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step;
  • FIG. 2B shows a somewhat idealized cross-sectional view of the layer stack of
  • FIG. 2A after a first photoresist layer and a first BARC layer are added;
  • FIG. 2C shows a somewhat idealized cross-sectional view of the layer stack of
  • FIG. 2B after the first photoresist layer and the first BARC layer have been processed through lithography
  • FIG. 2D shows the cross-sectional view of the layer stack of FIG. 2C after a trench mask layer has been processed
  • FIG. 2E shows the cross-sectional view of the layer stack of FIG. 2D, after the first photoresist layer and the first BARC layer are removed;
  • FIG. 2F shows the cross-sectional view of the layer stack of FIG. 2E after a second photoresist layer and a second BARC layer are disposed;
  • FIG. 2G shows the cross-sectional view of the layer stack of FIG. 2F after the second photoresist layer has been opened and an etch has been performed to partially etch into the IMD layer to create a via;
  • FIG. 2H shows the cross-sectional view of the layer stack of FIG. 2G after the second photoresist layer and second BARC layer have been stripped
  • FIG. 21 shows the cross-sectional view of the layer stack of FIG. 2H in which a barrier layer is etched
  • FIG. 2J shows the cross-sectional view of the layer stack of FIG. 2H in which a chemical mechanical polish process has been performed to polish the layer stack down to a cap layer;
  • FIG. 3 A shows the a cross-sectional view of a layer stack in which fencing has occurred
  • FIG. 3B shows the a cross-sectional view of a layer stack in which corner erosion has occurred
  • FIG. 4A a layer stack in which a set of three hard masks, comprised of two different barrier materials, has been deposited and patterned on the cap layer, according to one embodiment of the current invention
  • FIG. 4B shows the layer stack of FIG. 4A, in which a via has been etched using an appropriate etchant, according to one embodiment of the current invention
  • FIG. 4C shows the layer stack of FIG. 4B, in which mask 1 is removed using an appropriate etchant, according to one embodiment of the current invention
  • FIG. 4D shows the layer stack of FIG. 4C, in which mask 2 is removed using an appropriate etchant, according to one embodiment of the current invention
  • FIG. 4E shows the layer stack of FIG. 4D, in which a barrier has been etched using an appropriate etchant, according to one embodiment of the current invention
  • FIG. 4F shows the layer stack of FIG. 4E, in which a barrier has been added to the trench or via using an appropriate process, according to one embodiment of the current invention
  • FIG. 4G shows the layer stack of FIG. 4E, in which the trench or via has been filled and the top layer stack has been polished using an appropriate process, according to one embodiment of the current invention
  • FIG. 5A shows a simplified process in which a substrate is etched with a set of hard masks, according to one embodiment of the invention.
  • FIG. 5B shows a simplified process in which a substrate with a second barrier layer is etched with a set of hard masks, according to one embodiment of the invention.
  • the process of removing photoresist and BARC can often damage low-k material in the substrate.
  • dual damascene substrate manufacturing approaches require photoresist to be applied over a hard mask in order to lithographically pattern the underlying substrate, and also exposing the low-k material to oxygen.
  • laying down a set of hard masks above the low-k material will allow a via or trench to be etched without exposing the low-k material to oxygen used in conventional photoresist stripping processes.
  • inspection of the set of hard masks may further minimize misalignment issues present with trench-first and dual hard mask dual-damascene methodologies.
  • the masks are substantially comprised of metal materials.
  • a set of three masks and cap layer (or total four masks) is used.
  • the set of masks is comprised of different alternating mask materials.
  • the set of multiple masks may be used with dual damascene approaches to substrate manufacturing.
  • a substrate in a non-obvious fashion, is configured with a mask or cap layer (e.g., TEOS, etc.) deposited between a set of hard masks and the low-k dielectric material.
  • the cap layer and the set of hard masks are further comprised of a set of different alternating barrier materials, wherein a set of etchants may be selected whereby each individual etchant may possess a low selectivity to a particular type of barrier material, but a high selectivity to the remaining materials.
  • etchants such as C 4 F 6 and C 4 F 8 have a low selectivity to (and hence will tend to etch) TEOS, but a high selectivity to (and hence will tend not to etch) SiN or SiC.
  • etchants such as CF 4 , CHF 3 , CH 3 F, and CH 2 F 2 have a low selectivity to SiN or SiC, but have a high selectivity to TEOS.
  • the set of hard masks may then be patterned using traditional photoresist methods to create a hole for the via or trench.
  • An anisotropic etch profile in the dielectric may then be achieved by using the appropriate set of etchants, such as based on fluorine chemistry as previously described.
  • FIGS. 4A-F illustrate an idealized cross-sectional view of a layer stack, representing the layers of an exemplar semiconductor IC, in which a set of hard masks is employed to create a hole for a via or trench, as used in a dual-damascene manufacturing method, according to one embodiment of the current invention.
  • FIG. 4A shows a layer stack in which a set of three hard masks, comprised of two different barrier materials, has been deposited and patterned on the cap layer, according to one embodiment of the current invention.
  • a layer 408 comprising SiO 2 .
  • a barrier layer 404a typically comprising nitride or carbide (e.g., SiN, SiC, etc.), and possessing a thickness of about 700A.
  • Dual damascene substrates further comprise a set of metal layers including Ml 409a-b, typically comprising aluminum or copper.
  • a intermediate dielectric (IMD) layer 406, comprising a low-k material (e.g., SiOC, etc.), and possessing a thickness of about lO.OOOA.
  • IMD intermediate dielectric
  • cap layer 403a typically comprising TEOS, and possessing a thickness of about 500A.
  • cap layer 403 there may be disposed the set of hard masks that have been patterned using an appropriate method.
  • Mask 3 404b comprises SiC or SiN, and has a thickness of about 500A.
  • Mask 2 403b comprises TEOS, and has a thickness of about 2000A.
  • Mask 1 404c comprises Sic or SiN, and has a thickness of about 500A.
  • FIG. 4B shows the layer stack of FIG. 4A, in which via 410 has been etched using an appropriate etchant, such as C 4 F 6 and C 4 F 8j which has a low selectivity to the TEOS material, comprising mask 2 403b and the cap layer 403a, but a high selectivity to SiN or SiC, comprising mask 1 404c and mask 3 404b.
  • the initial profile of via 410 may thereby be defined by pattern of mask 3 404b.
  • FIG. 4C shows the layer stack of FIG. 4B, in which mask 1 404c, comprising
  • SiN or SiC is removed using an appropriate etchant, such as CF 4 and CHF 3> which has a low selectivity to SiN or SiC, but has a high selectivity to TEOS.
  • an appropriate etchant such as CF 4 and CHF 3> which has a low selectivity to SiN or SiC, but has a high selectivity to TEOS.
  • the removal process also transfers a trench pattern onto mask 3 404b. Since the thickness of low-k material 406 (10,000A) is considerably greater than that of mask 1 404c (500A), only a small amount of the low-k material is removed due to the ion bombardment of the etchant.
  • FIG. 4D shows the layer stack of FIG. 4C, in which mask 2 403b, comprising
  • FIG. 4E shows the layer stack of FIG.
  • barrier 404a has been etched using an appropriate etchant, such as CF 4 and CHF 3; which has a low selectivity to SiN or SiC, but has a high selectivity to TEOS.
  • an appropriate etchant such as CF 4 and CHF 3; which has a low selectivity to SiN or SiC, but has a high selectivity to TEOS.
  • FIG. 4F shows the layer stack of FIG. 4E, in which a TaN or TiN barrier 414 has been added to the trench or via using an appropriate process, such as plasma vapor deposition.
  • FIG. 4G shows the layer stack of FIG. 4E, in which the trench or via has been filled with copper, or another appropriate conductive material, and the top layer stack has been polished using an appropriate process, such as chemical mechanical polishing.
  • a substrate is introduced in a plasma processing system, the substrate having a semi-conductor layer, a first barrier layer disposed above the semiconductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer, at step 502.
  • the substrate is then alternatively etched with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer, and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer, at step 502.
  • a substrate is introduced in a plasma processing system, the substrate having a semi-conductor layer, a first barrier layer disposed above the semiconductor layer, a low-k layer disposed above the first barrier layer, a second barrier layer disposed above the low-k layer, a third hard mask layer disposed above the second barrier layer, a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer, at step 506.
  • the substrate is then alternatively etched with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer, and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer and the second barrier layer, at step 508.
  • Advantages of the invention include the optimization of substrate etching in a plasma processing system. Additional advantages may include the minimization of photoresist damage due to exposure to oxygen-based etchants, minimization of RC delay on the substrate, elimination of a plug step during a dual damascene manufacturing process, minimization of trench and via faceting and fencing during the etch process, and minimization of trench and via misalignment during the etch process.

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  • Drying Of Semiconductors (AREA)

Abstract

La présente invention se rapporte à un procédé de gravure d'un substrat dans un système de traitement au plasma. Le substrat comporte une couche semi-conductrice, une première couche barrière disposée au-dessus de la couche semi-conductrice, une couche à faible coefficient k disposée au-dessus de la première couche barrière, une troisième couche de masque dur disposée au-dessus de la couche à faible coefficient k; une deuxième couche de masque dur disposée au-dessus de la troisième couche de masque dur et une première couche de masque dur disposée au-dessus de la deuxième couche de masque dur. Ce procédé consiste à graver alternativement le substrat avec un premier agent de gravure et un second agent de gravure, ledit premier agent de gravure ayant une faible sélectivité par rapport à la matière du premier masque dur de la première couche de masque dur, à la matière du troisième masque dur de la troisième couche de masque dur, et à la matière de ladite première couche barrière, mais une forte sélectivité par rapport à une deuxième matière de masque dur de la seconde couche de masque dur; et ledit second agent de gravure ayant une forte sélectivité par rapport à la matière du premier masque dur de la première couche de masque dur, à la troisième matière de masque dur de la troisième couche de masque dur et à la matière de la première couche barrière, et le premier agent de gravure ayant une faible sélectivité par rapport à la deuxième matière de masque dur de la deuxième couche de masque dur.
PCT/US2005/007886 2004-03-19 2005-03-09 Procedes d'optimisation de la gravure d'un substrat dans un systeme de traitement au plasma WO2005091974A2 (fr)

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JP2007503965A JP5134363B2 (ja) 2004-03-19 2005-03-09 プラズマ加工システムによる基板エッチング法
KR1020067019324A KR101221158B1 (ko) 2004-03-19 2005-03-09 플라즈마 프로세싱 시스템에서의 기판 에칭의 최적화 방법
CN2005800085422A CN1997771B (zh) 2004-03-19 2005-03-09 等离子体处理系统中基片蚀刻的方法

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US10/804,430 US7078350B2 (en) 2004-03-19 2004-03-19 Methods for the optimization of substrate etching in a plasma processing system
US10/804,430 2004-03-19

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US20050205519A1 (en) 2005-09-22
WO2005091974A3 (fr) 2006-09-21
CN1997771A (zh) 2007-07-11
TWI352388B (en) 2011-11-11
CN1997771B (zh) 2010-11-10
TW200601452A (en) 2006-01-01
WO2005091974A9 (fr) 2005-11-24
JP2007529905A (ja) 2007-10-25
KR101221158B1 (ko) 2013-01-18
KR20060127209A (ko) 2006-12-11
US7078350B2 (en) 2006-07-18
JP5134363B2 (ja) 2013-01-30

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