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WO2005091366A3 - Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben - Google Patents

Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben

Info

Publication number
WO2005091366A3
WO2005091366A3 PCT/DE2005/000477 DE2005000477W WO2005091366A3 WO 2005091366 A3 WO2005091366 A3 WO 2005091366A3 DE 2005000477 W DE2005000477 W DE 2005000477W WO 2005091366 A3 WO2005091366 A3 WO 2005091366A3
Authority
WO
WIPO (PCT)
Prior art keywords
coupling substrate
production method
semiconductor chips
semiconductor module
associated production
Prior art date
Application number
PCT/DE2005/000477
Other languages
English (en)
French (fr)
Other versions
WO2005091366A2 (de
Inventor
Georg Meyer-Berg
Original Assignee
Infineon Technologies Ag
Georg Meyer-Berg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Georg Meyer-Berg filed Critical Infineon Technologies Ag
Publication of WO2005091366A2 publication Critical patent/WO2005091366A2/de
Publication of WO2005091366A3 publication Critical patent/WO2005091366A3/de
Priority to US11/532,321 priority Critical patent/US7498674B2/en

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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Die Erfindung betrifft ein Halbleitermodul (4) mit einem Kopplungssubstrat (1) und Verfahren zur Herstellung derselben. Das Kopplungssubstrat (1) dient der internen elektrischen Kopplung integrierter Schaltung benachbarter Halbleiterchips (2, 3). Die Halbleiterchips (2, 3) weisen integrierte Schaltungen auf und sind auf einer Trägerstruktur angeordnet. Die Halbleiterchips (2, 3) stehen extern mit Außenkontakten (22) in Verbindung. Das Kopplungssubstrat (1) überlappt Randbereiche (6, 7) der benachbarten Halbleiterchips (2, 3).
PCT/DE2005/000477 2004-03-18 2005-03-16 Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben WO2005091366A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/532,321 US7498674B2 (en) 2004-03-18 2006-09-15 Semiconductor module having a coupling substrate, and methods for its production

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004013681.5 2004-03-18
DE102004013681A DE102004013681B3 (de) 2004-03-18 2004-03-18 Halbleitermodul mit einem Kopplungssubstrat und Verfahren zur Herstellung desselben

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/532,321 Continuation US7498674B2 (en) 2004-03-18 2006-09-15 Semiconductor module having a coupling substrate, and methods for its production

Publications (2)

Publication Number Publication Date
WO2005091366A2 WO2005091366A2 (de) 2005-09-29
WO2005091366A3 true WO2005091366A3 (de) 2006-03-16

Family

ID=34964926

Family Applications (1)

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PCT/DE2005/000477 WO2005091366A2 (de) 2004-03-18 2005-03-16 Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben

Country Status (4)

Country Link
US (1) US7498674B2 (de)
CN (1) CN100517703C (de)
DE (1) DE102004013681B3 (de)
WO (1) WO2005091366A2 (de)

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US8227904B2 (en) * 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US9070644B2 (en) 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
DE102013106965B4 (de) * 2013-03-15 2021-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Die-Package und Verfahren zum Bilden desselben
US10038259B2 (en) 2014-02-06 2018-07-31 Xilinx, Inc. Low insertion loss package pin structure and method
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US11056373B2 (en) * 2015-07-21 2021-07-06 Apple Inc. 3D fanout stacking
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10177107B2 (en) 2016-08-01 2019-01-08 Xilinx, Inc. Heterogeneous ball pattern package
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
US11177201B2 (en) * 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
KR102538704B1 (ko) * 2018-12-04 2023-06-01 에스케이하이닉스 주식회사 플렉시블 브리지 다이를 포함한 스택 패키지
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR102674087B1 (ko) * 2019-09-06 2024-06-12 에스케이하이닉스 주식회사 전자기간섭 차폐층을 포함하는 반도체 패키지
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
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Also Published As

Publication number Publication date
DE102004013681B3 (de) 2005-11-17
CN1961426A (zh) 2007-05-09
WO2005091366A2 (de) 2005-09-29
CN100517703C (zh) 2009-07-22
US7498674B2 (en) 2009-03-03
US20070080442A1 (en) 2007-04-12

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