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WO2005088687A1 - Method for manufacturing gallium nitride semiconductor substrate - Google Patents

Method for manufacturing gallium nitride semiconductor substrate Download PDF

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Publication number
WO2005088687A1
WO2005088687A1 PCT/JP2005/003606 JP2005003606W WO2005088687A1 WO 2005088687 A1 WO2005088687 A1 WO 2005088687A1 JP 2005003606 W JP2005003606 W JP 2005003606W WO 2005088687 A1 WO2005088687 A1 WO 2005088687A1
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Prior art keywords
layer
substrate
gallium nitride
based semiconductor
film
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PCT/JP2005/003606
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French (fr)
Japanese (ja)
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Chiaki Sasaoka
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Nec Corporation
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to a method for manufacturing a gallium nitride based semiconductor substrate.
  • the present invention relates to a method for manufacturing a gallium nitride-based semiconductor substrate by forming a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth.
  • Group III nitride semiconductors represented by gallium nitride can emit blue-violet light with high efficiency, and light-emitting diodes (LEDs) and laser diodes (LDs) in the blue-violet region. ) Has attracted attention as a material. Above all, LDs in the blue-violet region are expected as light sources for large-capacity optical disk devices, and in recent years, high-output gallium nitride semiconductor LDs for writing light sources have been actively developed. At the same time, the development of high-frequency transistors that use gallium nitride-based semiconductors for the operating layer, taking advantage of the excellent electronic conduction characteristics exhibited by gallium nitride-based semiconductors, is also underway.
  • gallium nitride-based semiconductor devices have been mainly manufactured by using a group III nitride semiconductor layer hetero-grown on a base substrate of sapphire or SiC.
  • the reason is that it was difficult to obtain a good quality GaN single crystal substrate. Therefore, a wurtzite GaN (0001) layer is grown on a sapphire substrate or a SiC substrate using a two-step growth method, and the resulting GaN (0001) layer is used as a substrate by epitaxy growth of a group III nitride semiconductor layer.
  • a device structure has been manufactured.
  • the lattice constant of the underlying substrate and that of GaN are significantly different. It was known.
  • the thermal conductivity of the sapphire substrate is low, the heat dissipation characteristics of the device fabricated on it are poor, and the orientation of the cleavage (cleavage) plane differs between the GaN layer and the sapphire substrate. Difficulties in forming a mirror end face using cleavage are also difficult.Furthermore, since sapphire itself is an insulator, it is not possible to manufacture a back electrode type device. It was an essential problem.
  • a high-quality low-dislocation GaN substrate can be manufactured by a GaN thick film growth technique using HVPE (hydride vapor phase epitaxy) (for example, see Japanese Patent Application Laid-Open No. H10-287497). Reference).
  • HVPE hydrogen vapor phase epitaxy
  • a GaN substrate with good thermal and electrical conduction characteristics instead of a sapphire substrate, improvement of heat radiation characteristics and realization of back electrode type LD are expected. Therefore, in the future, a group III nitride semiconductor device using a GaN substrate manufactured by a thick film growth technique is considered to be the mainstream.
  • the mainstream GaN substrate manufacturing technology is to deposit a 300-m or more thick GaN layer on a single-crystal substrate such as sapphire or GaAs as an undersubstrate by HVPE, and then remove the undersubstrate. By removing it, a freestanding GaN substrate is obtained.
  • a single-crystal substrate such as sapphire or GaAs
  • HVPE high vacuum chemical vapor deposition
  • thermal and chemical stability of single crystal substrate during HVPE growth Is the key.
  • Sapphire substrates and SiC substrates which are generally used as base substrates for GaN growth, are chemically stable and hard. There was a problem that peeling could not be easily achieved.
  • a peeling method using a laser has also been proposed, but it has been difficult to peel the GaN layer over a large area without cracking the thick GaN layer.
  • GaAs is used as the base substrate, separation from the thick GaN layer can be easily performed.
  • thermal decomposition of GaAs occurs, so it is necessary to protect the backside and side edges other than the growth surface.
  • the GaAs material itself contains highly toxic As as a main component, it is not necessarily preferred as an undersubstrate in terms of environmental friendliness.
  • the Si substrate is thermally stable at the GaN growth temperature, and furthermore, the cost is low, the material itself has low toxicity, and a large-diameter wafer with good crystallinity is available. Has the advantage of In addition, since Si can be selectively removed easily by polishing or etching, it is promising as a base substrate material for producing a freestanding GaN substrate.
  • each of these methods has been proposed as a technique that can be applied effectively when the thickness of the gallium nitride-based semiconductor layer grown on the Si substrate is as thin as several zm.
  • a thick gallium nitride-based semiconductor layer having a film thickness exceeding several hundred m is deposited on a Si substrate.
  • the following problems occur.
  • pinholes are likely to occur in the buffer layer due to surface defects and foreign substances attached to the surface.
  • the reaction between Ga and Si occurs.However, the thickness of the gallium nitride based semiconductor layer to be grown is several m.
  • the reaction region that proceeds during growth is local near the pinhole and does not spread to the entire surface of the substrate.
  • the surrounding substrate Si and the deposited GaN layer are further melted back by the Ga / Si melt generated due to the local reaction near the pinhole, resulting in a reaction.
  • the expansion of the area progresses at an accelerated rate.
  • the GaZSi reaction associated with meltback affects the entire surface of the substrate, increasing the thickness of the grown film and causing a greater problem. Since it is difficult to completely suppress the generation of pinholes in the buffer layer due to surface defects and foreign substances adhering to the surface, if pinholes occur, the meltback reaction that occurs later
  • the means of suppressing the expansion is an effective solution to the problem of crystal degradation.
  • the present invention solves the above-mentioned problems, and an object of the present invention is to use a Si substrate as a base substrate and form a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth. At the time of formation, gallium nitride based materials that can effectively avoid the above crystal degradation and exhibit good crystallinity It is an object of the present invention to provide a method for manufacturing a semiconductor substrate.
  • the present inventor When forming a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth, the present inventor has replaced the conventionally used Si (ll) Balta substrate with a carrier gallium nitride-based semiconductor layer. , SiO film
  • a method for manufacturing a gallium nitride-based semiconductor substrate that is effective in the first embodiment of the present invention is a method for manufacturing a gallium nitride-based semiconductor substrate
  • a method of manufacturing a gallium nitride-based semiconductor substrate comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
  • a method for producing a gallium nitride based semiconductor substrate according to the second aspect of the present invention is a method for producing a gallium nitride based semiconductor substrate
  • a method for manufacturing a gallium nitride-based semiconductor substrate according to a third aspect of the present invention is a method for manufacturing a gallium nitride-based semiconductor substrate
  • the laminated structure of the Si (111) layer and the buffer layer on the first dielectric layer is partially left, and in other regions, the stacked structure of the Si (111) layer and the buffer layer is removed. Remove the laminated structure of
  • a method of manufacturing a gallium nitride-based semiconductor substrate comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
  • the thickness of the Si (ll) layer is in the range of: Lm or less.
  • the buffer layer is a gallium nitride based semiconductor layer containing at least A1.
  • the dielectric material of the first dielectric layer is desirably selected from a group of dielectric materials represented by SiON.
  • the dielectric material of the second dielectric layer be selected from the group of dielectric materials represented by SiON.
  • a substrate having in-plane anisotropy having a different thermal expansion coefficient from that of the Si (111) substrate can be used.
  • a Si (100) substrate can be used as the carrier substrate.
  • the gallium nitride-based semiconductor layer can be easily removed from the gallium nitride-based semiconductor layer by polishing or etching.
  • FIG. 1 is a cross-sectional view showing a series of steps in order for a method of depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 1.
  • FIG. 2 is a cross-sectional view showing a series of steps in order of a method of depositing a thick GaN by HVPE growth on a Si (111) Balta substrate described in Example 1.
  • FIG. 3 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 2.
  • FIG. 4 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 3.
  • FIG. 5 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 4. The meanings of the symbols shown in each figure are listed below.
  • a method for manufacturing a gallium nitride based semiconductor substrate according to the present invention will be described in detail below.
  • the first feature of the manufacturing method according to the present invention is that when a thick gallium nitride-based semiconductor layer is formed on a Si (111) surface by vapor phase growth, a Si (llll) Balta substrate conventionally used Instead, a first dielectric layer such as a SiO film is formed on the carrier substrate, and a first dielectric layer is formed on the first dielectric layer.
  • the SOI substrate a SiO (111) layer of a thin film
  • a first dielectric layer such as a film
  • physical separation between the two is achieved, and the amount of Si involved in the GaZSi meltback reaction is limited. Therefore, when a thick gallium nitride based semiconductor layer is formed by vapor phase growth, the SOI substrate is also heated to its growth temperature. It must function as a physical separation layer that prevents mass transfer between them. Therefore, the film thickness of the first dielectric layer is, for example, when the Si (ll) Balta substrate or the Si (100) Balta substrate is used as the carrier substrate, the upper Si (ll) Select a thickness range that is sufficient to prevent the supply of Si to the layer.
  • the thin Si (ll) layer is laminated on the carrier substrate via the first dielectric layer, the thin Si (llll) is used as the first dielectric layer. It is preferable to use a dielectric material represented by SiON, such as SiO, which has a high adhesion to ()). that time,
  • the desired function as a physical separation layer is sufficiently exhibited.
  • the total amount of Si involved in the GaZSi meltback reaction is reduced by reducing the thickness of the thin Si (111) layer itself, which is laminated on the first dielectric layer. Restrict. Therefore, it is desirable that the thickness of the thin Si (111) layer itself be selected in a range of 1 ⁇ m or less, preferably in a range of 0.2 / zm or less. When the thickness of the Si (lll) layer is reduced to 0.2 ⁇ m or less, for example, even if a pinhole is present in the buffer layer in the process of growing a GaN film having a thickness of 300 m or more, this pinhole is removed.
  • the inventors of the present invention have clarified that the amount of Si supplied from the Si (111) layer to the GaN layer via the Si layer is small, and often causes a GaZSi meltback reaction.
  • the thickness of the Si (lll) layer increases, the amount of Si supplied to the GaN layer through this pinhole increases, and the effect of suppressing the GaZSi meltback reaction gradually decreases.
  • the thickness of the Si (lll) layer is in the range of 1 m or less, it has a significant suppression effect as compared with the case where the Si (lll) Balta substrate is used.
  • the SOI substrate it was also found that the thickness of the thin Si (ll) layer was sufficient if it had a thickness of 0: m in order to function as an underlying substrate.
  • the method of manufacturing the SOI substrate itself is such that a thin film of Si ( 111)
  • a thin film of Si ( 111) There is no particular limitation as long as a structure in which layers are stacked is achieved. For example, after bonding a Si (ll) Balta substrate on a carrier substrate via a first dielectric layer by a bonding method, the upper Si (ll) Balta substrate is polished to obtain a desired Si (llll) substrate. ), And a method of forming a Si (111) layer having a thickness of at least Lm or less can be used.
  • the Si (111) Balta substrate surface force is subjected to deep ion implantation of oxygen ions, followed by an annealing treatment so that the surface of the Si (111) Balta substrate is exposed.
  • a structure in which a thin Si (111) layer is left on the outermost surface may be used.
  • a Si (100) Balta substrate is used as a carrier substrate, and a Si (ll) Balta substrate is bonded and bonded through a first dielectric layer, and the Si (100) Balta substrate is polished and bonded onto the Si (100) Balta substrate.
  • an SOI substrate having a structure in which a thin Si (ll) layer is stacked via a first dielectric layer can be used.
  • various substrates can be used as a carrier substrate used for producing an SOI substrate, but the substrate is inexpensive, is suitable for bonding and bonding, and has a large area. It is desirable to use a readily available Si Balta substrate for the carrier substrate.
  • a buffer layer is formed using the thin Si (111) layer as a base substrate.
  • This buffer layer prevents stress distortion at the interface due to the lattice constant difference between the gallium nitride based semiconductor grown on it and the underlying substrate Si (ll), and the introduction of defects such as mis'fit dislocations due to this stress distortion. Has a function to avoid. Therefore, for the buffer layer, an m-group nitride semiconductor having high lattice constant matching with the target gallium nitride-based semiconductor and having higher shear stress than the target gallium nitride-based semiconductor is selected. Furthermore, the m-nitride semiconductor itself used as this buffer layer is heated during the deposition of a thick gallium nitride-based semiconductor layer.
  • the melt back reaction hardly occur at the interface between the underlying substrate and Si (111).
  • Al and In have melting points significantly higher than Ga, and are less likely to cause a melt-back reaction when they come in contact with Si at high temperatures. Therefore, among the III-nitride semiconductors, the content ratio of Al and In is high, the content ratio of Ga is low, and the lattice constant of the III-nitride semiconductor is consistent with the lattice constant of the target gallium nitride-based semiconductor. It is preferable to select a range ⁇ .
  • the group III nitride semiconductor for the buffer layer satisfying the above requirements A1N, an AlGaInN mixed crystal partially containing Ga or In instead of A1 constituting A1N, or Grids can be mentioned.
  • the content ratio of Ga and In in the AlGaInN mixed crystal used as the buffer layer, y, 1-x-y is determined by the relaxation action of the strain stress caused by the lattice constant difference between Si and GaN. Select a range that is not significantly worse than Alternatively, in the AlGaInN superlattice, the averaged lattice constant is selected to be substantially the same as the lattice constant of an A1GaInN mixed crystal having a composition suitably usable as the buffer layer. Also contacts the Si (l l l) layer
  • the Ga / Si meltback reaction occurs at the interface due to Ga contained in the Al Ga In N mixed crystal.
  • the Ga content ratio y is selected so that the progress does not remarkably progress.
  • the thickness of the buffer layer itself is not less than 0.02 ⁇ m and not more than 2 ⁇ m. It is desirable to select a thickness within a range, for example, about 0.2 m. Since the buffer layer itself has a role of separating the gallium nitride based semiconductor grown thereon and Si (ll) of the underlying substrate, it is not desirable to select an excessively thin film thickness. It is preferable to select the above.
  • a substrate in which a thin Si (ll 1) layer is laminated on a carrier substrate via a first dielectric layer is used. Then, a process of depositing a thick gallium nitride-based semiconductor layer via a buffer layer is selected. Since the thickness of the buffer layer is small, fine pinholes and the like may be included in the buffer layer due to external factors such as deposits on the surface of the Si (111) layer. At this time, a thin Si (111) layer should be used even if a GaZSi melt-back reaction occurs locally through a pinhole in the buffer layer during the deposition of the thick gallium nitride based semiconductor layer. Thus, the effect of limiting the supply amount of Si and suppressing the reaction from proceeding at an accelerated rate can be obtained.
  • the second embodiment of the present invention when depositing a thick gallium nitride based semiconductor layer on a thin Si (ll) layer via a buffer layer, the surface of the buffer layer is partially covered. A second dielectric layer is formed. At this time, the growth of the gallium nitride-based semiconductor layer starts from the surface of the buffer layer, which is not covered with the second dielectric layer, and is used for the buffer layer. The crystal growth proceeds in the same plane orientation as the group III nitride semiconductor such as A1N. Therefore, as the second dielectric layer, a dielectric material that does not cause the formation of a growth nucleus of a gallium nitride-based semiconductor on its surface is used.
  • the second dielectric layer is stable under HVPE growth conditions and exhibits the function of covering the surface of the buffer layer.
  • the first group III nitride semiconductor film used for the buffer layer It is also necessary that there is no danigami reaction between the two.
  • the dielectric material for the second dielectric layer that satisfies these three requirements, for example, SiO, SiN, aluminum oxide (Al 2 O 3), SiO N, or the like can be used.
  • a laminated film combining these can be exemplified.
  • a dielectric material represented by SiO N such as SiO 2 also for the second dielectric layer.
  • an opening provided in the second dielectric layer covering the buffer layer must be formed. It must be provided with a high areal density.
  • the Group III element material and the nitrogen material that pour down onto the surface of the second dielectric layer diffuse on the surface of the second dielectric layer, and grow the gallium nitride based semiconductor on the surface of the buffer layer in the opening. Need to reach the surface.
  • the average distance between the openings on the surface of the second dielectric layer is about the same as or similar to the average distance at which the surface diffusion of the group III element material and the nitrogen material is possible. , It is preferred to choose shorter.
  • the openings provided in the second dielectric layer are regularly arranged over the entire surface of the substrate. At least in each partial area of the substrate surface, the openings are densely packed so that the area ratio (average opening ratio) of the openings Z (opening and covering area), averaged within each small area, is constant. Provide with high areal density It is necessary.
  • a method of arranging a stripe-shaped second dielectric layer at a constant pitch with an opening having a desired width therebetween by pattern etching can be used. At this time, the pitch interval was selected to be within a range of 10 m or less, and the width of the stripe-shaped second dielectric layer was determined by the area ratio (average opening ratio) of the opening Z (the opening and the covering region).
  • the range of 1Z10 or more and 4Z10 or less is desirable to select the range of 1Z10 or more and 4Z10 or less.
  • the lateral growth of the gallium nitride-based semiconductor shows crystal orientation anisotropy. Therefore, when the growth plane orientation of the gallium nitride-based semiconductor layer is (0001), the stripe of the stripe-shaped opening is stripped.
  • the direction (longitudinal direction) is preferably selected to be 11 20> or 1 100> in the axial direction.
  • the thickness of the second dielectric layer is relatively increased with respect to the width of the stripe-shaped opening, and the depth of the groove structure is increased. If it exceeds ⁇ , it is difficult in some cases to make lateral growth from a gallium nitride based semiconductor grown in a facet shape as a starting point. Therefore, it is desirable that the ratio of the thickness of the second dielectric layer to the width of the stripe-shaped opening (depth Z width ratio of the groove structure) is 1Z1 or less, preferably 0.2Z10-2Z10. .
  • the surface of the buffer layer directly in contact with the gallium nitride-based semiconductor layer grown as a thick film is only a portion exposed to the opening. Therefore, when fine pinholes are included in the buffer layer, the melt-back reaction of GaZSi occurs locally through the pinholes in the buffer layer during the deposition of the thick gallium nitride based semiconductor layer. Is limited to the surface of the opening. Therefore, the effect of reducing the total number of locations where the melt back reaction of GaZSi occurs locally as the area ratio (average opening ratio) of the openings Z (the opening and the covering region) decreases is obtained.
  • the surface of the buffer layer which is partially in contact with the gallium nitride-based semiconductor layer to be formed into a thick film by using the second dielectric layer, is partially covered with the opening. Only the parts that are exposed to the public are limited.
  • the first The laminated structure of the Si (111) layer and the buffer layer on the dielectric layer is partially left, and in other regions, the laminated structure of the Si (111) layer and the buffer layer is removed, and the first dielectric layer is removed. By exposing the surface, the surface of the buffer layer directly in contact with the gallium nitride based semiconductor layer to be grown thick is limited.
  • the exposed first dielectric layer uses a dielectric material that does not cause formation of a growth nucleus of a gallium nitride-based semiconductor on its surface.
  • the first dielectric layer is stable under HVPE growth conditions, and does not cause a dangling reaction with the first group III nitride semiconductor film used for the buffer layer. Is also necessary.
  • Dielectric materials for the first dielectric layer that satisfy these three requirements include, for example, SiO, SiN, and aluminum- ⁇ .
  • oxide film Al 2 O 3
  • SiO N SiO N
  • the first dielectric layer is represented by SiON, including SiO.
  • a dielectric material is used.
  • a thick gallium nitride-based semiconductor layer in the initial stage of growth, deposition does not occur on a region where the first dielectric layer is exposed, but is partially left.
  • the surface force of the buffer layer grows, and crystal growth proceeds, followed by lateral growth.
  • the thickness of the grown film is increased, and at the same time, the upper surface of the exposed region of the first dielectric layer is covered by the lateral growth layer.
  • the growth of the semiconductor layer proceeds.
  • a thick gallium nitride based semiconductor layer having a flat surface over the entire substrate can be obtained when growing a thick film having a certain film thickness or more.
  • the Group III element material and the nitrogen material that pour onto the surface of the first dielectric layer diffuse on the surface of the first dielectric layer, and grow the gallium nitride based semiconductor on the surface of the buffer layer in the remaining part. Need to reach the surface.
  • the average interval is preferably selected to be equal or shorter.
  • the remaining portion of the buffer layer is regularly arranged over the entire surface of the substrate. At least, in each partial area on the substrate surface, the area ratio of the residual portion Z (the residual portion and the exposed region), It is necessary to provide the remaining portion of the buffer layer with a dense area density so that the average residual ratio is constant.
  • the pitch interval was selected to be within 10 m or less, and the width of the remaining portion of the laminated structure of the striped Si (ll) layer and the buffer layer was determined by the area ratio of the remaining portion Z (the remaining portion and the exposed region). It is desirable to select (average residual ratio) to be in the range of 1Z10 or more and 4Z10 or less.
  • the lateral growth in the gallium nitride-based semiconductor exhibits crystal orientation anisotropy. Therefore, when the growth plane orientation of the gallium nitride-based semiconductor layer is (0001), the direction of the stripe of the stripe-shaped residual portion ( The longitudinal direction is preferably selected in the axial direction of 11-20> or 1-100>.
  • the ratio of the thickness of the laminated structure of the Si (111) layer and the buffer layer to the width of the exposed stripe region is It is desirable to select a value within the range of 1Z1 or less, preferably 0.2Z10-2Z10.
  • the thickness of the laminated structure of the thin Si (ll) layer and the buffer layer is selected to be not more than 0.2 m, preferably not more than 0.2 m
  • the width of the stripe-shaped exposed area can be selected in the range of 1 ⁇ m to 10 m.
  • the buffer layer covers the lower surface of the Si (111) layer in the remaining portion of the laminated structure of the Si (111) layer and the buffer layer. That is, when depositing a thick gallium nitride-based semiconductor layer by vapor phase growth, the deposited gallium nitride-based semiconductor does not directly contact the surface of the underlying Si (ll) layer. At this time, the width of the exposed groove is also fine, and since the Si (111) layer and the buffer layer to be etched are made of different materials, both can be masked and removed at the same time.
  • Use of a chlorine-based dry etching method is suitable as a means having selectivity in which the dielectric layer is not etched.
  • the gallium nitride-based semiconductor layer which is grown as a thick film is directly The surface of the buffer layer in contact is limited to the remaining portion of the laminated structure of the etched Si (ll) layer and the buffer layer. Further, the thin Si (ll 1) layer involved in the melt back reaction of GaZSi is also limited to the remaining portion. In other words, when a fine pinhole is included in the buffer layer, a GaZSi melt-back reaction occurs locally through the pinhole in the buffer layer while depositing the thick gallium nitride based semiconductor layer. Is limited to this residual surface.
  • the effect is obtained that the total number of locations where the meltback reaction of GaZSi occurs locally also decreases.
  • the thin Si (ll) layer is adopted and the area of the remaining Si (ll) layer itself is also limited, the supply amount of Si is further limited, and the reaction proceeds at an accelerated rate.
  • an SOI substrate is used to deposit a thick gallium nitride-based semiconductor layer having a flat surface over the entire substrate surface. Is separated from the thick gallium nitride-based semiconductor layer to form a gallium nitride-based semiconductor free-standing substrate. At this time, the first dielectric layer and the thin Si (ll) layer exist in the interface region between the thick gallium nitride based semiconductor layer and the SOI substrate, and these can be selectively dissolved. Separation can be performed by etching using an etching solution.
  • An example of an etchant that can be used for this selective etching process is a hydrofluoric / nitric acid solution.
  • the carrier substrate constituting the SOI substrate is not dissolved by the selective etching process, the first dielectric layer constituting the interface region and the thin Si (ll) layer constituting the interface region are formed. If gallium nitride-based semiconductor layers can be dissolved and removed, it is possible to separate a thick gallium nitride-based semiconductor layer.
  • a substrate made of a material different from a thin Si (ll) layer may be used as a carrier substrate constituting an SOI substrate to be used.
  • a Si Balta substrate having a plane orientation different from that of the Si (111) layer can be used.
  • a substrate having a different in-plane anisotropy of the thermal expansion coefficient as compared with the thin Si (ll) layer can be used.
  • a Si Balta substrate having a plane orientation different from that of a thin Si (ll) layer for example, a Si (100) substrate
  • the crystal orientation contained in the plane is different, and the in-plane anisotropy of the thermal thermal expansion coefficient is obtained. Sex is different.
  • the laminated structure of the Si (111) layer and the buffer layer is etched, and the boundary region between the thick gallium nitride based semiconductor layer and the SOI substrate is formed. It only accounts for a part.
  • the laminated structure portion of the etched Si (111) layer and the buffer layer, the interface between the Si (111) layer and the buffer layer Alternatively, delamination may occur at the interface between the first dielectric film and the thin Si (111) layer.
  • cooling is performed even if there is a difference in the in-plane anisotropy of the thermal expansion coefficient between the Si (ll) layer of the thin film and the carrier substrate. In the interim, spontaneous separation often does not occur.
  • strain stress is accumulated in the plane, and for example, the first dielectric film and the thin film Strain stress is applied to the Si (111) layer in the in-plane direction.
  • selective etching is performed on the first dielectric film and the thin Si (ll) layer, the effect of promoting the lateral etching of these layered portions is exhibited due to the internal strain stress. Sometimes.
  • FIG. 1 shows the manufacturing process of the first embodiment according to the method for manufacturing a gallium nitride based semiconductor substrate according to the first embodiment of the present invention
  • FIG. 2 shows a gallium nitride based semiconductor substrate using a conventional method. The manufacturing process of a conductive substrate is shown.
  • a 2-inch Si (111) SOI substrate manufactured by a bonding method is used as a substrate. That is, the Si (ll) SOI substrate is formed on a 2-inch Si (111) Balta substrate 101 having a thickness of 300 m by a SiO film 102 having a thickness of 100 nm.
  • Si (111) layer 103 is bonded to the substrate via the second layer.
  • the Si (111) layer 103 on the surface side is thinned to a thickness of 0: m by polishing, and the surface is made into a Si (ll) surface by mirror polishing.
  • a 2-inch Si (111) Balta substrate 201 is used as a substrate.
  • a sample A is prepared by depositing a 0.1-nm thick A1N film 104 on the Si (lll) layer 103 on the surface of the Si (lll) SOI substrate by the following procedure and conditions. After RCA cleaning of the SOI substrate, it is introduced into the MOCVD growth equipment, and the temperature is raised to 1050 ° C in a mixed atmosphere of hydrogen and nitrogen. After heating, NH
  • TMA trimethylaluminum
  • sample A was cooled to room temperature, and a sample A in which an A1N film for a buffer layer was formed on the Si (111) surface was taken out from the MOCVD apparatus.
  • an A1N film 202 having a thickness of 0.2 ⁇ m is deposited on the Si (ll) surface of the Si (ll) Balta substrate 201 in the same procedure and under the same conditions, thereby preparing a sample B.
  • 300 / zm thick undoped GaN thick films 105 and 203 were deposited on the A1N films 104 and 202, respectively. After the deposition of the GaN thick film, it is cooled to room temperature and taken out of the HVPE equipment. Then, the substrate was immersed in a hydrofluoric-nitric acid solution to dissolve the substrate Si, and a 300-m thick undoped GaN film was separated.
  • the GaN thick film 203 produced on the sample B the GaN film was polycrystallized by the melt back reaction of Ga and Si, and became fine fragments after dissolution of the Si substrate.
  • the GaN thick film 105 formed on the sample A did not become fine or broken after the dissolution of the Si substrate, and a freestanding GaN substrate was obtained.
  • the first dielectric layer in this example, silicon
  • Si (lll) thin layer formed via an oxide film as a substrate is verified.
  • FIG. 3 shows a manufacturing process of Example 2 by a method of manufacturing a gallium nitride-based semiconductor substrate according to the second embodiment of the present invention. Also in the manufacturing process of Example 2 shown in FIG. 3, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as a substrate. Further, the SOI substrate used in the second embodiment also has a Si (ll) layer 303 laminated on a 300-m thick 2-inch Si (111) bulk substrate 301 via a lOOnm thick SiO film 302.
  • the Si (111) layer 303 on the front side is thinned to a thickness of 0.1 ⁇ m by polishing, and its surface is made into a Si (111) surface by mirror polishing.
  • an A1N film 304 having a thickness of 0.2 m is deposited as a buffer layer under the conditions described in the first embodiment.
  • a 300 nm thick SiO film is deposited on the surface of the A1N film 304 for the buffer layer, and patterned by photolithography.
  • a periodic SiO stripe 'mask pattern 305 On the surface of the A1N film 304 for the buffer layer, a periodic SiO stripe 'mask pattern 305
  • the sample C on which was formed was introduced into the HVPE apparatus, and an undoped GaN thick film 306 of 300 m was deposited under the same conditions as those of the GaN thick film forming step described in Example 1. Thereafter, the substrate Si was dissolved in a hydrofluoric / nitric acid solution to dissolve the substrate Si, and a 300-m thick undoped GaN thick film was separated to obtain a freestanding GaN substrate.
  • GaN is growing on the surface of the IN film. Therefore, the surface area of the exposed A1N film is as small as 2Z10 on the entire surface of the substrate, and the number of pinholes in the A1N film formed in that region also decreases at that ratio. As a result, the probability of a Ga-Si reaction occurring due to pinholes in the A1N film present in the opening is reduced, and the number of pit-like defects is correspondingly reduced. It is understood that a reduction in
  • FIG. 4 shows a manufacturing process of Example 3 by a method of manufacturing a gallium nitride-based semiconductor substrate according to the third embodiment of the present invention. Also in the manufacturing process of the third embodiment shown in FIG. 4, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as a substrate. This SOI substrate was manufactured by the manufacturing method described in Example 1, and a 300 / zm-thick 2-inch Si (111) nonolec substrate 401 / 0.1-m thick SiO film 402 / 0.1-m-thick Si ( 111) Layer 403
  • an A1N film 404 having a thickness of 0 is deposited as a buffer layer under the conditions described in the first embodiment.
  • a resist is applied to the surface of the A1N film 404 and patterned by photolithography to form an 8 ⁇ m wide opening between stripes on the entire surface of the substrate, and a resist stripe is formed at a 10 ⁇ m pitch. did.
  • the resist stripe as an etching mask and chlorine-based dry etching, select the A1N film 404 and the ZSi layer 403 in the opening until the SiO layer 402 in the SOI substrate is exposed.
  • the sample on which the periodic AlNZSi (llll) stripe' pattern 405 was formed was introduced into an HVPE apparatus, and the same step as the GaN thick film forming step described in Example 1 ' Under the conditions, a 300-m thick undoped GaN thick film 406 was deposited. Then, the substrate Si was immersed in a hydrofluoric-nitric acid solution to dissolve the substrate Si, and a undoped GaN thick film of 300 m was separated to obtain a freestanding GaN substrate.
  • GaN growth starts from the A1N film 404 for the buffer layer, which has been etched into a periodic stripe pattern.
  • traces of reaction between Ga and Si were found at several locations corresponding to the periodic AlNZSi (111) stripe pattern 405. .
  • the surface area of the remaining A1N film as a result of etching processing in a periodic stripe 'pattern shape is as small as 2Z10 on the entire surface of the substrate, and the surface area of the A1N film formed in that region is small.
  • the number of pinholes also decreased at that rate.
  • the total amount of the Si layer 403 remaining on the same surface is also reduced to 2Z10. Therefore, the probability of the reaction between Ga and Si caused by the pinhole in the A1N film present in the stripe 'pattern portion is reduced, and at the same time, the reaction between Ga and Si is stopped at an early stage. As a result, it was understood that although a local reaction of Ga and Si occurred in the early stage of the growth of the GaN thick film 406, it self-stopped at an early stage and led to a pit-like defect on the surface. Is done.
  • FIG. 5 shows a manufacturing process of Example 4 in which the method for manufacturing a gallium nitride based semiconductor substrate according to the third embodiment of the present invention is applied. Also in the manufacturing process of Example 4 shown in FIG. 5, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as the substrate.
  • the SOI substrate used in the present embodiment 4 also has a Si (ll) layer 503 on a 2-inch Si (100) NOREK substrate 501 having a thickness of 300 m via a SiO film 502 having a thickness of 100 nm.
  • the Si (111) layer 503 on the front side is thinned to a thickness of 0.1 ⁇ m by polishing, and the surface is mirror-polished to the Si (111) plane.
  • An A1N film 504 having a thickness of 0.2 m is deposited as a buffer layer on the Si (ll) layer 503 on the surface of the Si (ll) SOI substrate under the conditions described in the first embodiment.
  • a resist is applied to the surface of the A1N film 504 and patterned by photolithography to form openings of 8 ⁇ m width between stripes on the entire surface of the substrate. Were fabricated at a pitch of 10 m. Using the resist stripe as an etching mask and chlorine-based dry etching, the A1N film 504 in the opening is exposed until the SiO layer 502 in the SOI substrate is exposed.
  • the ZSi layer 503 was selectively removed to form a stripe-shaped AlNZSi (111) 505.
  • the sample on which the periodic AlNZSi (11 1) stripe “pattern 505” was formed was introduced into an HVPE apparatus, and described in Example 1.
  • An undoped GaN thick film 506 of 300 m was deposited under the same conditions as those of the GaN thick film forming step. After the GaN thick film is deposited, it is cooled down to room temperature and taken out of the HVPE apparatus, and unlike the third embodiment, spontaneous peeling between the GaN thick film 506 and the Si (100) Balta substrate 501 occurs during the cooling process. Had occurred. As a result, the substrate Si is immersed in hydrofluoric-nitric acid solution A freestanding GaN substrate was obtained without any dissolving operation.
  • the self-standing GaN substrate made of the GaN thick film 506 manufactured in Example 4 also has a pit-shaped surface within 2 inches. No defects were observed. Also in the fourth embodiment, the growth of GaN is started with the A1N film 504 for the buffer layer, which is etched in a periodic stripe pattern pattern. Further, when the back surface of the obtained free-standing GaN substrate was observed in detail, traces of reaction between Ga and Si were found at several portions corresponding to the periodic AlNZSi (ll) stripe pattern 505.
  • Example 4 the separation between the GaN thick film 506 and the Si (100) Balta substrate 501, which occurred during the cooling process after the growth of the GaN thick film, was caused by the separation between GaN and Si. It is understood that this is caused by the strain stress caused by the difference in thermal expansion coefficient.
  • the Si (111) Balta substrate used in Example 3 and the Si (100) Balta substrate used in Example 4 have different crystal orientations.
  • the crystal orientation of the GaN thick film growing from the A1N film of the buffer layer formed in Example 3 is the same in Example 3 and Example 4. That is, in Example 3 and Example 4, there is a difference in strain stress caused by a difference in thermal expansion coefficient between GaN and Si due to a difference in crystal orientation of the Si Balta crystal used.
  • Example 3 the strain stress caused by the difference in the thermal expansion coefficient between GaN and Si is due to the periodic etching of the AlNZSi (lll) stripe that forms the boundary region between the two. Although it does not reach the threshold value that causes peeling in the pattern portion, in Example 4, it is understood that the strain stress exceeds the threshold value that causes peeling in the AIN / Si (111) stripe / pattern portion.
  • the A1N film is used as the buffer layer in order to alleviate the problem of crystal growth caused by the lattice constant difference between Si and GaN.
  • the effect as a buffer layer for this purpose is not impaired! / In the range, Al Ga In N mixed crystal containing Ga or In or a superlattice or a superlattice is used for the buffer layer instead of A1.
  • the effects of the present invention are exhibited.
  • the content ratio y, 1- ⁇ -y of Ga and In in the AlGaInN mixed crystal used as the buffer layer is determined by the effect of relaxing the strain stress caused by the lattice constant difference between Si and GaN.
  • the averaged lattice constant is selected to be substantially the same as the lattice constant of an AlGaInN mixed crystal having a composition suitably usable as the buffer layer.
  • the Ga content ratio y is selected so that the GaZSi melt-back reaction does not significantly proceed at the interface due to Ga contained in the AlGaInN mixed crystal in contact with the Si (ll) layer.
  • Examples 14 to 14 the example in which the thick group III nitride semiconductor layer to be manufactured is GaN is described.
  • the first problem to be solved in the present invention is the suppression of the Ga / Si meltback reaction.A1 and In have a much higher reactivity to cause meltback when in contact with Si than Ga does. Low.
  • the thick III-nitride semiconductor layer is made of Al In GaN mixed crystal instead of GaN, the Ga content ratio is slightly reduced.
  • the formed thick group III nitride semiconductor layer is
  • Examples 14 to 14 the example in which the thick group III nitride semiconductor layer to be manufactured is Andoop GaN was described.
  • a conductive substrate used for manufacturing the above-described LED or LD, or a semi-insulating substrate used for manufacturing a high-frequency transistor silicon, magnesium, Doping with impurities such as oxygen. Even when these impurities are doped at a high concentration, in the process of producing a thick group III nitride semiconductor layer, the impurities originate from the Si (lll) layer via pinholes in the buffer layer. The influence of the GaZSi meltback reaction by Si and Ga exists.
  • impurities doped at a high concentration do not have the effect of significantly reducing the frequency of the GaZSi melt-back reaction itself at the interface that occurs at the early stage of growth. Therefore, it is clear that the present invention is effective even when the impurity is highly doped.
  • Oxygen ions are implanted into the Si (111) substrate from the surface and then annealed, and the Si (111) Balta substrate ZSiO film ZSi (ll)
  • Example 2 a first III nitride semiconductor film used as a buffer layer, here, an SiO film was used as a second dielectric layer partially covering the surface of the A1N film.
  • the second dielectric layer is stable under HVPE growth conditions, exhibits a function of covering the surface of the buffer layer, and has a function to cover the first group III nitride semiconductor film used for the buffer layer. In addition, it is necessary to prevent the dangling reaction from occurring. In addition to the SiO film, these two
  • the first group III nitride semiconductor film used as the buffer layer was etched into a periodic stripe pattern, and the first III nitride semiconductor film was striped.
  • a mode in which the growth of a thick group III nitride semiconductor layer is selectively started from the group III nitride semiconductor film is used.
  • the first group III nitride semiconductor film exposed on the surface is As the dielectric layer, it is more preferable to select a material that does not easily generate crystal nuclei of a group III nitride semiconductor on its surface.
  • a gallium nitride-based semiconductor free-standing substrate can be easily and simply used by using an inexpensive, large-area Si substrate as a base substrate. It can be manufactured with high productivity.

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Abstract

A substrate is provided by stacking a first dielectric layer (102) and an Si (111) layer (103) on a bulk substrate (101). On the Si layer (103), a buffer layer (104) and a thick film gallium nitride semiconductor layer (105) are deposited. A gallium nitride semiconductor substrate is manufactured by using the thick film gallium nitride semiconductor layer. The bulk substrate (101) and the Si layer (103) are physically separated by providing the first dielectric layer (102), and a quantity of Si which relates to Ga/Si melt back reaction is limited. As a result, crystal deterioration can be effectively prevented from expanding, and the gallium nitride semiconductor substrate having excellent crystallinity can be manufactured.

Description

明 細 書  Specification
窒化ガリウム系半導体基板の作製方法  Manufacturing method of gallium nitride based semiconductor substrate
技術分野  Technical field
[0001] 本発明は、窒化ガリウム系半導体基板の作製方法に関する。特には、 Si (l l l)面 上に気相成長によって厚膜の窒化ガリウム系半導体層を形成することで、窒化ガリウ ム系半導体基板を作製する方法に関する。 背景技術  The present invention relates to a method for manufacturing a gallium nitride based semiconductor substrate. In particular, the present invention relates to a method for manufacturing a gallium nitride-based semiconductor substrate by forming a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth. Background art
[0002] 窒化ガリウムに代表される III族窒化物半導体は、高効率の青紫色発光が可能であ り、青紫色領域の発光ダイオード（light emitting diode, LED)やレーザーダイォ ード (laser diode, LD)用材料として、注目を浴びてきた。なかでも、青紫色領域の LDは、大容量光ディスク装置の光源として期待され、近年、書き込み光源用の高出 カ窒化ガリウム系半導体 LDの開発が勢力的に進められている。カロえて、窒化ガリウ ム系半導体の示す、優れた電子伝導特性を生かし、動作層に窒化ガリウム系半導体 を利用する高周波トランジスタの開発も、同時に進められている。  [0002] Group III nitride semiconductors represented by gallium nitride can emit blue-violet light with high efficiency, and light-emitting diodes (LEDs) and laser diodes (LDs) in the blue-violet region. ) Has attracted attention as a material. Above all, LDs in the blue-violet region are expected as light sources for large-capacity optical disk devices, and in recent years, high-output gallium nitride semiconductor LDs for writing light sources have been actively developed. At the same time, the development of high-frequency transistors that use gallium nitride-based semiconductors for the operating layer, taking advantage of the excellent electronic conduction characteristics exhibited by gallium nitride-based semiconductors, is also underway.
[0003] これら窒化ガリウム系半導体デバイスは、従来、主に、サファイアまたは SiCを下地 基板とし、その上にヘテロ成長させた III族窒化物半導体層を利用して作製されてい る。その理由は、良質な GaN単結晶基板の入手が困難であったためである。従って 、サファイア基板や SiC基板上に 2段階成長法を用いてウルッ鉱型 GaN (0001)層 を成長させ、得られる GaN (0001)層を基板として、 III族窒化物半導体層のェピタキ シャル成長によって、素子構造が作製されてきた。これらサファイア基板や SiC基板 を下地基板に用いる場合、下地基板と GaNの格子定数が大きく異なるため、ヘテロ 成長させた GaN層に高密度の転位が導入され、良質な結晶を得る上での障害とな つていた。加えて、サファイア基板の熱伝導度が低いため、その上に作製されている 素子の放熱特性が悪いこと、劈開（へキカイ）面の配向が GaN層とサファイア基板と で異なり、 LD作製時、劈開 (へキカイ)を利用するミラー端面形成が困難であること、 更には、サファイア自体、絶縁体であるため、裏面電極型素子の作製が不可能であ ることも、サファイア基板の利用に伴う本質的な問題であった。 [0004] 一方、近年、 HVPE (hydride vapor phase epitaxy)を用いる GaN厚膜成長 技術によって、良質な低転位 GaN基板の作製が可能であることも報告されている（例 えば、特開平 10— 287497号公報を参照)。サファイア基板に代えて、熱伝導特性、 電気伝導特性の良好な GaN基板を用いることにより、放熱特性の改善、裏面電極型 LDの実現等が期待される。従って、将来的には、厚膜成長技術により作製される Ga N基板を利用した、 III族窒化物半導体素子が主流になると考えられる。 [0003] Conventionally, these gallium nitride-based semiconductor devices have been mainly manufactured by using a group III nitride semiconductor layer hetero-grown on a base substrate of sapphire or SiC. The reason is that it was difficult to obtain a good quality GaN single crystal substrate. Therefore, a wurtzite GaN (0001) layer is grown on a sapphire substrate or a SiC substrate using a two-step growth method, and the resulting GaN (0001) layer is used as a substrate by epitaxy growth of a group III nitride semiconductor layer. A device structure has been manufactured. When these sapphire substrates and SiC substrates are used for the underlying substrate, the lattice constant of the underlying substrate and that of GaN are significantly different. It was known. In addition, since the thermal conductivity of the sapphire substrate is low, the heat dissipation characteristics of the device fabricated on it are poor, and the orientation of the cleavage (cleavage) plane differs between the GaN layer and the sapphire substrate. Difficulties in forming a mirror end face using cleavage are also difficult.Furthermore, since sapphire itself is an insulator, it is not possible to manufacture a back electrode type device. It was an essential problem. On the other hand, in recent years, it has been reported that a high-quality low-dislocation GaN substrate can be manufactured by a GaN thick film growth technique using HVPE (hydride vapor phase epitaxy) (for example, see Japanese Patent Application Laid-Open No. H10-287497). Reference). By using a GaN substrate with good thermal and electrical conduction characteristics instead of a sapphire substrate, improvement of heat radiation characteristics and realization of back electrode type LD are expected. Therefore, in the future, a group III nitride semiconductor device using a GaN substrate manufactured by a thick film growth technique is considered to be the mainstream.
[0005] 現在、主流となって ヽる GaN基板作製技術は、下地基板のサファイア、 GaAsなど の単結晶基板上に HVPE法により 300 m以上の厚膜 GaN層を堆積させ、その後、 下地基板を除去することにより自立 GaN基板を得るものである。 HVPEによる GaN 基板作製においては、（1)単結晶基板と厚膜 GaN層の剥離、（2) HVPE成長時に おける、単結晶基板の熱的および化学的安定性、の二点の課題をいかに解決する かが鍵となる。 GaN成長用下地基板として一般的に利用されて ヽるサファイア基板、 SiC基板は、化学的に安定であり、かつ硬いために、化学エッチングや研磨によって 、 GaNZサファイア、あるいは、 GaNZSiC構造から下地基板の剥離を容易に達成 できないという問題があった。サファイア基板の場合には、レーザーを用いた剥離法 も提案されているが、大面積にわたり、厚膜 GaN層の割れなしに剥離することは困難 であった。また、 GaAsを下地基板とする場合、厚膜 GaN層との剥離は、容易に行う ことが可能である。しかしながら、典型的な HVPE法による GaNの成長温度（一 100 0°C)では、 GaAsの熱分解が生じるため、成長面以外の裏面、側端面を保護する必 要がある。さらに、 GaAs材料自体、毒性の高い Asを主な成分として含むため、対環 境性の点で、必ずしも好ま 、下地基板ではな 、。  [0005] At present, the mainstream GaN substrate manufacturing technology is to deposit a 300-m or more thick GaN layer on a single-crystal substrate such as sapphire or GaAs as an undersubstrate by HVPE, and then remove the undersubstrate. By removing it, a freestanding GaN substrate is obtained. How to solve two issues in GaN substrate fabrication by HVPE: (1) separation of single crystal substrate and thick GaN layer, and (2) thermal and chemical stability of single crystal substrate during HVPE growth Is the key. Sapphire substrates and SiC substrates, which are generally used as base substrates for GaN growth, are chemically stable and hard. There was a problem that peeling could not be easily achieved. For a sapphire substrate, a peeling method using a laser has also been proposed, but it has been difficult to peel the GaN layer over a large area without cracking the thick GaN layer. Also, when GaAs is used as the base substrate, separation from the thick GaN layer can be easily performed. However, at the typical HVPE growth temperature of GaN (100 ° C), thermal decomposition of GaAs occurs, so it is necessary to protect the backside and side edges other than the growth surface. Furthermore, since the GaAs material itself contains highly toxic As as a main component, it is not necessarily preferred as an undersubstrate in terms of environmental friendliness.
[0006] 素子作製工程において、窒化ガリウム系半導体層のへテロ成長用の下地基板とし て、 Si (111)を用いる事例も提案されている（特開平 8— 56015号公報、特開平 11— 40850号公報を参照)。その際、 Si下地基板と GaNの格子定数差に起因する結晶 成長上の問題を克服する手段として、 A1N緩衝層を用いることが有用であることも例 示されている（特開平 11 40850号公報を参照)。また、 Si基板は、 GaN成長温度 において熱的に安定であり、更には、入手コストが低いこと、材料自体毒性が低いこ と、結晶性のよい大口径ウェハが入手可能であることなど、多くの利点を有す。加え て、研磨やィ匕学エッチングにより、容易に Siを選択的に除去することが可能であるた め、自立 GaN基板作製のための下地基板材料として有望である。 [0006] In the device fabrication process, there has been proposed a case in which Si (111) is used as an undersubstrate for hetero-growth of a gallium nitride-based semiconductor layer (JP-A-8-56015, JP-A-11-40850). Reference). At that time, it has been shown that it is useful to use an A1N buffer layer as a means for overcoming the problem of crystal growth caused by the lattice constant difference between the Si base substrate and GaN (Japanese Patent Application Laid-Open No. 11 40850). See). In addition, the Si substrate is thermally stable at the GaN growth temperature, and furthermore, the cost is low, the material itself has low toxicity, and a large-diameter wafer with good crystallinity is available. Has the advantage of In addition In addition, since Si can be selectively removed easily by polishing or etching, it is promising as a base substrate material for producing a freestanding GaN substrate.
発明の開示  Disclosure of the invention
[0007] 窒化ガリウム系半導体を成長する場合、 Siを基板として用いる際には、 Gaと Siに因 る反応に起因する結晶劣化、 GaNと Siの熱膨張係数差に起因するクラッキング発生 が問題となる。これらの問題を解決する技術として、 Gaと Siに因る反応を抑制する目 的で、 Si基板表面を炭化して、 SiC組成の緩衝層を設ける手法 (特開平 8— 56015号 公報）、クラッキング発生を回避する目的で、 AlGalnN超格子を緩衝層として用いる 手法 (特開平 11 40850号公報)などが提案されている。しかし、これらの手法は、い ずれも、 Si基板上に成長される窒化ガリウム系半導体層の膜厚が数； z mと薄い場合 に、有効に適用可能な技術として提案されたものである。一方、膜厚は数百 mを超 える、厚膜の窒化ガリウム系半導体層を Si基板上に堆積する場合には、次のような問 題が生じる。例えば、上記 SiC組成の緩衝層形成時、表面欠陥や表面に付着した異 物に起因して、緩衝層にピンホールが生じやすい。この緩衝層内のピンホールを介 して、 Gaと Si基板表面との直接的な接触が生じると、 Gaと Siの反応が起こるが、成長 される窒化ガリウム系半導体層の膜厚が数 m程度と薄い場合には、成長中に進行 する反応領域は、ピンホール近傍の局所的なものであり、基板全面に波及することは ない。一方、厚膜 GaNを堆積する場合、当初、ピンホール近傍における局所的な反 応に伴って生じた Ga/Si融液により、周囲の基板 Siおよび堆積した GaN層がさらに メルトバックする結果、反応領域の拡大が加速度的に進行する。そのため、メルトバッ クに伴った、 GaZSi反応は、基板全面に影響を及ぼすことになり、成長される膜厚が 増すとともに、より大きな問題となる。表面欠陥や表面に付着した異物に起因する、 緩衝層内のピンホール発生を完全に抑制することは困難であるため、仮に、ピンホー ル発生が生じた際、その後に引き起こされる、メルトバック反応の拡大を抑制する手 段は、前記結晶劣化の問題に対する、有効な解決手段となる。  [0007] In growing a gallium nitride based semiconductor, when Si is used as a substrate, crystal degradation due to a reaction due to Ga and Si, and cracking due to a difference in thermal expansion coefficient between GaN and Si are problematic. Become. Techniques for solving these problems include a technique of carbonizing the Si substrate surface to provide a buffer layer having a SiC composition with the aim of suppressing the reaction caused by Ga and Si (Japanese Patent Laid-Open No. 8-56015), For the purpose of avoiding generation, a method using an AlGalnN superlattice as a buffer layer (JP-A-11 40850) has been proposed. However, each of these methods has been proposed as a technique that can be applied effectively when the thickness of the gallium nitride-based semiconductor layer grown on the Si substrate is as thin as several zm. On the other hand, when a thick gallium nitride-based semiconductor layer having a film thickness exceeding several hundred m is deposited on a Si substrate, the following problems occur. For example, when forming a buffer layer having the above-described SiC composition, pinholes are likely to occur in the buffer layer due to surface defects and foreign substances attached to the surface. When direct contact between Ga and the Si substrate surface occurs through the pinholes in the buffer layer, the reaction between Ga and Si occurs.However, the thickness of the gallium nitride based semiconductor layer to be grown is several m. If the thickness is as thin as possible, the reaction region that proceeds during growth is local near the pinhole and does not spread to the entire surface of the substrate. On the other hand, when depositing thick-film GaN, the surrounding substrate Si and the deposited GaN layer are further melted back by the Ga / Si melt generated due to the local reaction near the pinhole, resulting in a reaction. The expansion of the area progresses at an accelerated rate. As a result, the GaZSi reaction associated with meltback affects the entire surface of the substrate, increasing the thickness of the grown film and causing a greater problem. Since it is difficult to completely suppress the generation of pinholes in the buffer layer due to surface defects and foreign substances adhering to the surface, if pinholes occur, the meltback reaction that occurs later The means of suppressing the expansion is an effective solution to the problem of crystal degradation.
[0008] 本発明は前記の課題を解決するもので、本発明の目的は、 Si基板を下地基板とし て用い、 Si(l l l)面上に気相成長によって厚膜の窒化ガリゥム系半導体層を形成す る際、上記結晶劣化の拡大を有効に回避でき、良質な結晶性を示す窒化ガリウム系 半導体基板の作製を可能とする方法を提供することにある。 [0008] The present invention solves the above-mentioned problems, and an object of the present invention is to use a Si substrate as a base substrate and form a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth. At the time of formation, gallium nitride based materials that can effectively avoid the above crystal degradation and exhibit good crystallinity It is an object of the present invention to provide a method for manufacturing a semiconductor substrate.
[0009] 本発明者は、 Si(lll)面上に気相成長によって厚膜の窒化ガリウム系半導体層を 形成する際、従来用いていた Si(lll)バルタ基板に代えて、担体基板上に、 SiO膜  When forming a thick gallium nitride-based semiconductor layer on a Si (ll) surface by vapor phase growth, the present inventor has replaced the conventionally used Si (ll) Balta substrate with a carrier gallium nitride-based semiconductor layer. , SiO film
2 などの誘電体層と、この誘電体層上に Si(lll)層が積層された、 SOI(silicon on insulator)基板を利用し、力！]えて、 Si (111)層表面上に緩衝層を設け、厚膜の窒化 ガリウム系半導体層を形成することにより、 GaZSiメルトバック反応に起因する結晶 劣化の拡大、ならびにピット上の表面欠陥の生成を有効に回避できることを見出した 。本発明は、この知見に基づき、完成に至ったものである。  Using a dielectric layer such as 2 and a SOI (silicon on insulator) substrate with a Si (lll) layer laminated on this dielectric layer, force! In addition, by providing a buffer layer on the surface of the Si (111) layer and forming a thick gallium nitride-based semiconductor layer, the crystal degradation caused by the GaZSi melt-back reaction expands and surface defects on pits are generated. Has been found that can be effectively avoided. The present invention has been completed based on this finding.
[0010] すなわち、本発明の第一の形態に力かる窒化ガリウム系半導体基板の作製方法は 窒化ガリウム系半導体基板を作製する方法であって、 That is, a method for manufacturing a gallium nitride-based semiconductor substrate that is effective in the first embodiment of the present invention is a method for manufacturing a gallium nitride-based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si(lll)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si(lll)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (ll) layer on the substrate surface;
緩衝層の堆積後、厚膜の窒化ガリウム系半導体層を堆積する工程とを 少なくとも有し、  Depositing a thick gallium nitride-based semiconductor layer after depositing the buffer layer,
前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法である。  A method of manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[0011] また、本発明の第二の形態に力かる窒化ガリウム系半導体基板の作製方法は、 窒化ガリウム系半導体基板を作製する方法であって、 [0011] Further, a method for producing a gallium nitride based semiconductor substrate according to the second aspect of the present invention is a method for producing a gallium nitride based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si(lll)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si(lll)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (ll) layer on the substrate surface;
緩衝層の堆積後、前記緩衝層の表面を部分的に被覆する第二の誘電体層を形成 する工程と、  Forming a second dielectric layer that partially covers the surface of the buffer layer after depositing the buffer layer;
前記第二の誘電体層による部分的被覆後、厚膜の窒化ガリウム系半導体層を堆積 する工程とを  Depositing a thick gallium nitride based semiconductor layer after the partial coating with the second dielectric layer.
少なくとも有し、 前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法である。 At least have A method of manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[0012] さらに、本発明の第三の形態に力かる窒化ガリウム系半導体基板の作製方法は、 窒化ガリウム系半導体基板を作製する方法であって、  Further, a method for manufacturing a gallium nitride-based semiconductor substrate according to a third aspect of the present invention is a method for manufacturing a gallium nitride-based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si (l l l)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si (l l l)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (l l l) layer on the substrate surface;
緩衝層の堆積後、前記第一の誘電体層上の前記 Si ( 111 )層と緩衝層との積層構 造を部分的に残し、他の領域では、前記 Si (111)層と緩衝層との積層構造を除去し After the deposition of the buffer layer, the laminated structure of the Si (111) layer and the buffer layer on the first dielectric layer is partially left, and in other regions, the stacked structure of the Si (111) layer and the buffer layer is removed. Remove the laminated structure of
、第一の誘電体層表面を露出させる工程と、 Exposing the surface of the first dielectric layer,
前記 Si (l l l)層と緩衝層との積層構造の部分的除去後、厚膜の窒化ガリウム系半 導体層を堆積する工程とを  Depositing a thick gallium nitride-based semiconductor layer after partially removing the stacked structure of the Si (ll) layer and the buffer layer.
少なくとも有し、  At least have
前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法である。  A method of manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[0013] 上記の三種の形態を有する本発明の窒化ガリウム系半導体基板の作製方法にお いて、  [0013] In the method for manufacturing a gallium nitride-based semiconductor substrate of the present invention having the above three forms,
前記 Si (l l l)層の厚さを、： L m以下の範囲に選択することが好ましい。また、前記 緩衝層は、少なくとも A1を含む窒化ガリウム系半導体層であることが好ましい。一方、 前記第一の誘電体層の誘電体材料は、 SiO Nで示される誘電体材料の群から選 択することが望ましい。同様に、前記第二の誘電体層の誘電体材料も、 SiO Nで示 される誘電体材料の群から選択することが望ま ヽ。  It is preferable to select the thickness of the Si (ll) layer in the range of: Lm or less. Further, it is preferable that the buffer layer is a gallium nitride based semiconductor layer containing at least A1. On the other hand, the dielectric material of the first dielectric layer is desirably selected from a group of dielectric materials represented by SiON. Similarly, it is desirable that the dielectric material of the second dielectric layer be selected from the group of dielectric materials represented by SiON.
[0014] なお、本発明の窒化ガリウム系半導体基板の作製方法において、  In the method for manufacturing a gallium nitride based semiconductor substrate of the present invention,
前記担体基板として、 Si (111)基板とは異なる熱膨張係数の面内異方性を有する 基板を用いることができる。例えば、前記担体基板として、 Si (100)基板を用いること ができる。  As the carrier substrate, a substrate having in-plane anisotropy having a different thermal expansion coefficient from that of the Si (111) substrate can be used. For example, a Si (100) substrate can be used as the carrier substrate.
[0015] 本発明により、研磨やィ匕学エッチングによって、窒化ガリウム系半導体層から容易 に除去することができ、また、安価に入手可能な Si基板を下地基板として利用し、 Si ( According to the present invention, the gallium nitride-based semiconductor layer can be easily removed from the gallium nitride-based semiconductor layer by polishing or etching.
Ο Ο
111)面上に気相成長によって厚膜の窒化ガリウム系半導体層を形成する際、 Gaと Si1—に〇因る反応に起因する結晶劣化の影響を局所的な範囲に抑制することが可能とな When forming a thick gallium nitride based semiconductor layer by vapor phase growth on the (111) plane, it is possible to suppress the effect of crystal degradation caused by the reaction caused by Ga and Si What
1—  1—
る。結果として、本発明にかかる窒化ガリウム系半導体基板の作製方法を利用するこ とで、安価で、大面積の Si基板を下地基板として利用し、例えば、良質な GaN自立 基板を簡便、かつ高 、生産性で作製することが可能となる。  The As a result, by using the method for manufacturing a gallium nitride-based semiconductor substrate according to the present invention, a low-cost, large-area Si substrate is used as a base substrate. It can be manufactured with productivity.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
016] [図 1]図 1は、実施例 1に記載する、 SOI基板上への HVPE成長による厚膜 GaNの堆 積方法に関して、一連の工程を順に示す断面図である。 [FIG. 1] FIG. 1 is a cross-sectional view showing a series of steps in order for a method of depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 1.
[図 2]図 2は、実施例 1に記載される、 Si (111)バルタ基板上への HVPE成長による 厚膜 GaNの堆積方法に関して、一連の工程を順に示す断面図である。  [FIG. 2] FIG. 2 is a cross-sectional view showing a series of steps in order of a method of depositing a thick GaN by HVPE growth on a Si (111) Balta substrate described in Example 1.
[図 3]図 3は、実施例 2に記載する、 SOI基板上への HVPE成長による厚膜 GaNの堆 積方法に関して、一連の工程を順に示す断面図である。  [FIG. 3] FIG. 3 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 2.
[図 4]図 4は、実施例 3に記載する、 SOI基板上への HVPE成長による厚膜 GaNの堆 積方法に関して、一連の工程を順に示す断面図である。  [FIG. 4] FIG. 4 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 3.
[図 5]図 5は、実施例 4に記載する、 SOI基板上への HVPE成長による厚膜 GaNの堆 積方法に関して、一連の工程を順に示す断面図である。 以下に、各図中に示す符 号の有する意味を列記する。  [FIG. 5] FIG. 5 is a cross-sectional view showing a series of steps in order of a method for depositing a thick-film GaN by HVPE growth on an SOI substrate described in Example 4. The meanings of the symbols shown in each figure are listed below.
Si (111)バルタ基板  Si (111) Balta substrate
102 SiO膜  102 SiO film
2  2
103 Si (l l l)層  103 Si (l l l) layer
104 A1N膜  104 A1N film
105 HVPE成長 GaN厚膜  105 HVPE growth GaN thick film
201 Si (111)バルタ基板  201 Si (111) Balta substrate
202 A1N膜  202 A1N film
203 HVPE成長 GaN厚膜  203 HVPE growth GaN thick film
301 Si (111)バルタ基板  301 Si (111) Balta substrate
302 SiO膜  302 SiO film
2  2
303 Si (l l l)層 304 A1N膜 303 Si (lll) layer 304 A1N film
305 SiOストライプ.マスクパターン  305 SiO stripe mask pattern
2  2
306 HVPE成長 GaN厚膜  306 HVPE growth GaN thick film
401 Si (111)バルタ基板  401 Si (111) Balta substrate
402 SiO膜  402 SiO film
2  2
403 Si (l l l)層  403 Si (l l l) layer
404 A1N膜  404 A1N film
405 AlNZSi (111)ストライプ 'パターン  405 AlNZSi (111) stripe 'pattern
406 HVPE成長 GaN厚膜  406 HVPE growth GaN thick film
501 Si (100)バルタ基板  501 Si (100) Balta substrate
502 SiO膜  502 SiO film
2  2
503 Si (l l l)層  503 Si (l l l) layer
503 A1N膜  503 A1N film
505 AlNZSi (111)ストライプ 'パターン  505 AlNZSi (111) stripe 'pattern
506 HVPE成長 GaN厚膜  506 HVPE growth GaN thick film
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0018] 本発明にかかる窒化ガリウム系半導体基板の作製方法について、以下に詳しく説 明する。  A method for manufacturing a gallium nitride based semiconductor substrate according to the present invention will be described in detail below.
[0019] 本発明にかかる作製方法の第一の特徴は、 Si (111)面上に気相成長によって厚 膜の窒化ガリウム系半導体層を形成する際、従来用いていた Si(l l l)バルタ基板に 代えて、担体基板上に、 SiO膜などの第一の誘電体層と、この第一の誘電体層上に  The first feature of the manufacturing method according to the present invention is that when a thick gallium nitride-based semiconductor layer is formed on a Si (111) surface by vapor phase growth, a Si (llll) Balta substrate conventionally used Instead, a first dielectric layer such as a SiO film is formed on the carrier substrate, and a first dielectric layer is formed on the first dielectric layer.
2  2
薄膜の Si (l l l)層が積層された、 SOI基板を利用する点にある。また、前記薄膜の S 1 (111)層の表面に緩衝層を形成した上で、気相成長によって厚膜の窒化ガリウム系 半導体層を形成している。  The point is that an SOI substrate on which a thin Si (ll) layer is laminated is used. After forming a buffer layer on the surface of the S 1 (111) layer of the thin film, a thick gallium nitride based semiconductor layer is formed by vapor phase growth.
[0020] SOI基板ではなぐ Siバルタ基板を用いる場合には、緩衝層中に存在するピンホー ルを介した、 GaZSiメルトバック反応が起こった際、 Siが基板側から継続的に供給さ れる。そのため、 GaZSiメルトバック反応が加速度的に進行することにある。  [0020] When a Si Balta substrate is used instead of an SOI substrate, Si is continuously supplied from the substrate side when a GaZSi meltback reaction occurs via a pinhole present in the buffer layer. Therefore, the GaZSi meltback reaction proceeds at an accelerated rate.
[0021] 一方、前記 SOI基板においては、薄膜の Si (111)層と下の担体基板との間に SiO 膜などの第一の誘電体層を設けることで、両者間の物理的な分離を図り、 GaZSiメ ルトバック反応に関与する Si量を制限している。そのため、気相成長によって厚膜の 窒化ガリウム系半導体層を形成する際、 SOI基板も、その成長温度まで加熱された 状態となるが、この加熱状態においても、第一の誘電体層は、両者間での物質移動 を妨げる、物理的な分離層として機能する必要がある。従って、第一の誘電体層の 膜厚は、例えば、担体基板として、 Si(lll)バルタ基板や Si(100)バルタ基板を用 いる際にも、該 Si基板から、上層の Si(lll)層への Siの供給を防止できるに十分な 膜厚範囲に選択する。 On the other hand, in the SOI substrate, a SiO (111) layer of a thin film By providing a first dielectric layer such as a film, physical separation between the two is achieved, and the amount of Si involved in the GaZSi meltback reaction is limited. Therefore, when a thick gallium nitride based semiconductor layer is formed by vapor phase growth, the SOI substrate is also heated to its growth temperature. It must function as a physical separation layer that prevents mass transfer between them. Therefore, the film thickness of the first dielectric layer is, for example, when the Si (ll) Balta substrate or the Si (100) Balta substrate is used as the carrier substrate, the upper Si (ll) Select a thickness range that is sufficient to prevent the supply of Si to the layer.
[0022] また、該第一の誘電体層を介して、薄膜の Si(lll)層が担体基板上に積層する構 造とするので、該第一の誘電体層として、薄膜の Si(lll)に対する密着性に富む、 S iOを始めとする、 SiO Nで示される誘電体材料を用いることが好ましい。その際、 [0022] Further, since the thin Si (ll) layer is laminated on the carrier substrate via the first dielectric layer, the thin Si (llll) is used as the first dielectric layer. It is preferable to use a dielectric material represented by SiON, such as SiO, which has a high adhesion to ()). that time,
2 2
第一の誘電体層の膜厚は、少なくとも、 lOOnm程度であっても、所望とする物理的な 分離層としての機能は十分に発揮される。  Even if the thickness of the first dielectric layer is at least about 100 nm, the desired function as a physical separation layer is sufficiently exhibited.
[0023] 力！]えて、本発明においては、前記第一の誘電体層上に積層されている、薄膜の Si ( 111)層自体の膜厚も薄くすることで、 GaZSiメルトバック反応に関与する Siの総量 を制限して 、る。従って、薄膜の Si ( 111)層自体の膜厚は、 1 μ m以下の範囲、好ま しくは、 0. 2 /zm以下の範囲に選択することが望ましい。 Si(lll)層の膜厚が 0. 2μ m以下と薄くなると、例えば、 300 m以上の厚膜 GaNを成長する過程において、緩 衝層中にピンホールが存在しても、このピンホールを介して、 Si (111)層から GaN層 へと供給される Si量は少なく、 GaZSiメルトバック反応を引き起こすに至らな 、ことが 多いことが、本発明者の検討により解明された。 Si(lll)層の膜厚が増すとともに、こ のピンホールを介して、 Si(lll)層力 GaN層へと供給される Si量は増し、次第に、 GaZSiメルトバック反応の抑制効果は低減する。その際に、 Si(lll)層の膜厚が 1 m以下の範囲であれば、 Si(lll)バルタ基板を用いた場合と比較し、なお、有意 な抑制効果を有している。一方、 SOI基板を用いる際、薄膜の Si(lll)層は、下地 基板としの機能を有する上では、その膜厚が 0.： mもあれば、十分であることも判 明した。 [0023] Power! In the present invention, the total amount of Si involved in the GaZSi meltback reaction is reduced by reducing the thickness of the thin Si (111) layer itself, which is laminated on the first dielectric layer. Restrict. Therefore, it is desirable that the thickness of the thin Si (111) layer itself be selected in a range of 1 μm or less, preferably in a range of 0.2 / zm or less. When the thickness of the Si (lll) layer is reduced to 0.2 μm or less, for example, even if a pinhole is present in the buffer layer in the process of growing a GaN film having a thickness of 300 m or more, this pinhole is removed. The inventors of the present invention have clarified that the amount of Si supplied from the Si (111) layer to the GaN layer via the Si layer is small, and often causes a GaZSi meltback reaction. As the thickness of the Si (lll) layer increases, the amount of Si supplied to the GaN layer through this pinhole increases, and the effect of suppressing the GaZSi meltback reaction gradually decreases. . At this time, when the thickness of the Si (lll) layer is in the range of 1 m or less, it has a significant suppression effect as compared with the case where the Si (lll) Balta substrate is used. On the other hand, when the SOI substrate was used, it was also found that the thickness of the thin Si (ll) layer was sufficient if it had a thickness of 0: m in order to function as an underlying substrate.
[0024] SOI基板自体の作製方法は、担体基板上に第一の誘電体層を介して、薄膜の Si ( 111)層が積層された構造が達成される限り、特に制限はない。例えば、担体基板上 に第一の誘電体層を介して、 Si(l l l)バルタ基板を張り合せ法により接合した上で、 上層の Si (l l l)バルタ基板を研磨して、所望の Si (l l l)面を有し、少なくとも膜厚が ： L m以下の Si (111)層とする手法が利用できる。あるいは、担体基板として、 Si(l l 1)バルタ基板を選択する際には、この Si (111)バルタ基板表面力 酸素イオンを深 くイオン注入し、その後、ァニール処理を施しことで、基板表面下に SiO層領域を形 [0024] The method of manufacturing the SOI substrate itself is such that a thin film of Si ( 111) There is no particular limitation as long as a structure in which layers are stacked is achieved. For example, after bonding a Si (ll) Balta substrate on a carrier substrate via a first dielectric layer by a bonding method, the upper Si (ll) Balta substrate is polished to obtain a desired Si (llll) substrate. ), And a method of forming a Si (111) layer having a thickness of at least Lm or less can be used. Alternatively, when a Si (ll 1) Balta substrate is selected as the carrier substrate, the Si (111) Balta substrate surface force is subjected to deep ion implantation of oxygen ions, followed by an annealing treatment so that the surface of the Si (111) Balta substrate is exposed. Form SiO layer area
2  2
成し、最表面に薄 、Si ( 111)層が残される構造を利用することもできる。  Alternatively, a structure in which a thin Si (111) layer is left on the outermost surface may be used.
[0025] 特に、前記担体基板上に第一の誘電体層を介して、 Si(l l l)バルタ基板を張り合 せ法により接合する手法を用いる場合、張り合せ接合が可能である限り、種々の担体 基板を利用することが可能である。例えば、担体基板として、 Si (100)バルタ基板を 用い、第一の誘電体層を介して、 Si (l l l)バルタ基板を張り合せ接合し、研磨によつ て、 Si (100)バルタ基板上に第一の誘電体層を介して、薄膜の Si(l l l)層が積層さ れた構造した SOI基板を利用することもできる。このように、本発明においては、 SOI 基板を作製する際に用いる担体基板として、種々の基板が利用可能であるが、安価 であり、また、張り合せ接合に適しており、かつ大面積の基板が容易に入手可能な Si バルタ基板を担体基板に利用することが望まし 、。 [0025] In particular, when using a technique of bonding a Si (ll) Balta substrate by a bonding method via the first dielectric layer on the carrier substrate, various methods are used as long as the bonding can be performed. It is possible to use a carrier substrate. For example, a Si (100) Balta substrate is used as a carrier substrate, and a Si (ll) Balta substrate is bonded and bonded through a first dielectric layer, and the Si (100) Balta substrate is polished and bonded onto the Si (100) Balta substrate. Alternatively, an SOI substrate having a structure in which a thin Si (ll) layer is stacked via a first dielectric layer can be used. As described above, in the present invention, various substrates can be used as a carrier substrate used for producing an SOI substrate, but the substrate is inexpensive, is suitable for bonding and bonding, and has a large area. It is desirable to use a readily available Si Balta substrate for the carrier substrate.
[0026] 次いで、薄膜の Si (111)層を下地基板として、緩衝層を形成する。この緩衝層は、 その上に成長する窒化ガリウム系半導体と、下地基板の Si (l l l)との格子定数差に 起因する界面での応力歪み、この応力歪みによるミス'フィット転位などの欠陥導入を 回避する機能を有する。従って、緩衝層には、目的とする窒化ガリウム系半導体と格 子定数の整合性が高ぐ同時に、目的の窒化ガリウム系半導体よりも剪断応力に優 れる m族窒化物半導体を選択する。さら〖こは、この緩衝層として利用する m族窒化物 半導体自体が、厚膜の窒化ガリウム系半導体層を堆積する工程中、その加熱条件下 Next, a buffer layer is formed using the thin Si (111) layer as a base substrate. This buffer layer prevents stress distortion at the interface due to the lattice constant difference between the gallium nitride based semiconductor grown on it and the underlying substrate Si (ll), and the introduction of defects such as mis'fit dislocations due to this stress distortion. Has a function to avoid. Therefore, for the buffer layer, an m-group nitride semiconductor having high lattice constant matching with the target gallium nitride-based semiconductor and having higher shear stress than the target gallium nitride-based semiconductor is selected. Furthermore, the m-nitride semiconductor itself used as this buffer layer is heated during the deposition of a thick gallium nitride-based semiconductor layer.
、下地基板の Si (111)との界面において、メルトバック反応を引き起こし難いことも必 要である。具体的には、 III族（13族)金属のうち、 Al、 Inは、 Gaよりも有意に高い融点 を有し、高温下において、 Siと接触した際、メルトバック反応をより引き起こし難い。従 つて、 III族窒化物半導体のうち、 Al、 Inの含有比率が高ぐ Gaの含有比率は低ぐか つ、その格子定数は、目的とする窒化ガリウム系半導体の格子定数と整合性が高い 範囲に選択することが好ま ヽ。 In addition, it is necessary that the melt back reaction hardly occur at the interface between the underlying substrate and Si (111). Specifically, of the Group III (Group 13) metals, Al and In have melting points significantly higher than Ga, and are less likely to cause a melt-back reaction when they come in contact with Si at high temperatures. Therefore, among the III-nitride semiconductors, the content ratio of Al and In is high, the content ratio of Ga is low, and the lattice constant of the III-nitride semiconductor is consistent with the lattice constant of the target gallium nitride-based semiconductor. It is preferable to select a range ヽ.
[0027] 前記要件を満足する緩衝層用の III族窒化物半導体としては、 A1N、この A1Nを構 成する A1に代えて、部分的に Gaや Inを含む Al Ga In N混晶、もしくは超格子を 挙げることができる。その際、緩衝層として利用する、 Al Ga In N混晶中の Ga、 I nの含有比率 y、 1 - x - yを、 Siと GaNの格子定数差に起因する歪み応力の緩和作用 力 A1Nよりも大きく劣らない範囲に選択する。あるいは、 Al Ga In N超格子に おいて、その平均された格子定数を、前記緩衝層として好適に利用可能な組成の A1 Ga In N混晶が示す格子定数と同程度に選択する。また、 Si(l l l)層と接するAs the group III nitride semiconductor for the buffer layer satisfying the above requirements, A1N, an AlGaInN mixed crystal partially containing Ga or In instead of A1 constituting A1N, or Grids can be mentioned. At this time, the content ratio of Ga and In in the AlGaInN mixed crystal used as the buffer layer, y, 1-x-y, is determined by the relaxation action of the strain stress caused by the lattice constant difference between Si and GaN. Select a range that is not significantly worse than Alternatively, in the AlGaInN superlattice, the averaged lattice constant is selected to be substantially the same as the lattice constant of an A1GaInN mixed crystal having a composition suitably usable as the buffer layer. Also contacts the Si (l l l) layer
Al Ga In N混晶中に含まれる Gaにより、その界面で Ga/Siメルトバック反応が The Ga / Si meltback reaction occurs at the interface due to Ga contained in the Al Ga In N mixed crystal.
Ι  Ι
顕著に進行しない範囲に、 Gaの含有比率 yを選択する。  The Ga content ratio y is selected so that the progress does not remarkably progress.
[0028] さらに、緩衝層は、格子定数差に起因する界面での応力歪みを緩和する機能を発 揮する上では、それ自体の膜厚は、 0. 02 μ m以上、 2 μ m以下の範囲、例えば、 0. 2 m程度の薄さに選択することが望ましい。なお、この緩衝層自体、その上に成長 する窒化ガリウム系半導体と、下地基板の Si (l l l)とを分離する役割を有するので、 過度に薄い膜厚に選択することは望ましく無ぐ少なくとも、 0. 以上を選択す ることが好ましい。 [0028] Furthermore, in order for the buffer layer to exhibit the function of alleviating the stress strain at the interface caused by the lattice constant difference, the thickness of the buffer layer itself is not less than 0.02 μm and not more than 2 μm. It is desirable to select a thickness within a range, for example, about 0.2 m. Since the buffer layer itself has a role of separating the gallium nitride based semiconductor grown thereon and Si (ll) of the underlying substrate, it is not desirable to select an excessively thin film thickness. It is preferable to select the above.
[0029] 本発明の第一の形態では、担体基板上に第一の誘電体層を介して、薄膜の Si (l l 1)層が積層されてなる基板を利用し、 Si (111)層上に緩衝層を介して、厚膜の窒化 ガリウム系半導体層を堆積する工程を選択している。この緩衝層の膜厚は薄いため、 Si (111)層表面の付着物などの外的な要因により、緩衝層中に微細なピンホールな どを含むことがある。その際、厚膜の窒化ガリウム系半導体層を堆積する間に、緩衝 層中のピンホールを介し、 GaZSiのメルトバック反応が局所的に生じても、薄膜の Si (111)層を採用することで、 Siの供給量を制限し、反応が加速度的に進行することを 抑制する効果が得られる。  [0029] In the first embodiment of the present invention, a substrate in which a thin Si (ll 1) layer is laminated on a carrier substrate via a first dielectric layer is used. Then, a process of depositing a thick gallium nitride-based semiconductor layer via a buffer layer is selected. Since the thickness of the buffer layer is small, fine pinholes and the like may be included in the buffer layer due to external factors such as deposits on the surface of the Si (111) layer. At this time, a thin Si (111) layer should be used even if a GaZSi melt-back reaction occurs locally through a pinhole in the buffer layer during the deposition of the thick gallium nitride based semiconductor layer. Thus, the effect of limiting the supply amount of Si and suppressing the reaction from proceeding at an accelerated rate can be obtained.
[0030] 本発明の第二の形態においては、薄膜の Si (l l l)層上に緩衝層を介して、厚膜の 窒化ガリウム系半導体層を堆積する際、緩衝層の表面を部分的に被覆する第二の 誘電体層を形成している。その際、窒化ガリウム系半導体層の成長は、前記第二の 誘電体層による被覆がなされて ヽな 、緩衝層の表面から開始し、この緩衝層に用い る A1Nなどの III族窒化物半導体と同一の面方位に結晶成長が進行する形態とする。 従って、第二の誘電体層としては、その表面においては、窒化ガリウム系半導体の成 長核の形成が生じることのない誘電体材料を用いる。カロえて、この第二の誘電体層 は、 HVPE成長条件下で安定であり、緩衝層の表面を被覆する機能を示すこと、ま た、緩衝層に用いる、第一の III族窒化物半導体膜との間でィ匕学反応を生じないこと も必要である。この三つの要件を満足する第二の誘電体層用の誘電体材料としては 、例えば、 SiO、 SiN、アルミニウム酸化物（Al O )、または、 SiO N、あるいは、そ [0030] In the second embodiment of the present invention, when depositing a thick gallium nitride based semiconductor layer on a thin Si (ll) layer via a buffer layer, the surface of the buffer layer is partially covered. A second dielectric layer is formed. At this time, the growth of the gallium nitride-based semiconductor layer starts from the surface of the buffer layer, which is not covered with the second dielectric layer, and is used for the buffer layer. The crystal growth proceeds in the same plane orientation as the group III nitride semiconductor such as A1N. Therefore, as the second dielectric layer, a dielectric material that does not cause the formation of a growth nucleus of a gallium nitride-based semiconductor on its surface is used. The second dielectric layer is stable under HVPE growth conditions and exhibits the function of covering the surface of the buffer layer. In addition, the first group III nitride semiconductor film used for the buffer layer It is also necessary that there is no danigami reaction between the two. As the dielectric material for the second dielectric layer that satisfies these three requirements, for example, SiO, SiN, aluminum oxide (Al 2 O 3), SiO N, or the like can be used.
2 2 3  2 2 3
れらを組み合わせた積層膜が例示できる。なかでも、第二の誘電体層に対しても、 Si Oを始めとする、 SiO Nで示される誘電体材料を用いることが好ましい。  A laminated film combining these can be exemplified. In particular, it is preferable to use a dielectric material represented by SiO N such as SiO 2 also for the second dielectric layer.
2  2
[0031] 厚膜の窒化ガリウム系半導体層成長においては、成長初期には、第二の誘電体層 による被覆領域上への堆積は生じな 、が、被覆されて 、な 、緩衝層の表面力も結晶 成長が進行し、その後、横方向への成長が生じる。この横方向成長を利用することで 、成長膜厚が増すととともに、第二の誘電体層による被覆領域上面も埋め込まれ、最 終的には、基板面全体に窒化ガリウム系半導体層の成長が進む (例えば、 C. Sas aoka他、ジャーナル'ォブ，クリスタル'グロース、 189Z190卷、 1998年、 61— 66 ページ)。その結果として、一定の膜厚以上の厚膜成長を行う際、基板全体に平坦な 表面を有する、厚膜の窒化ガリウム系半導体層が得られる。  [0031] In the growth of a thick gallium nitride based semiconductor layer, no deposition occurs on the area covered by the second dielectric layer in the initial stage of growth, but it is covered, and the surface strength of the buffer layer is also reduced. Crystal growth proceeds, followed by lateral growth. By utilizing this lateral growth, the thickness of the grown film is increased and the upper surface of the region covered by the second dielectric layer is also buried, so that the gallium nitride based semiconductor layer is eventually grown on the entire substrate surface. Proceed (eg, C. Sas aoka et al., Journal 'ob, Crystal' Growth, Vol. 189Z190, 1998, 61-66). As a result, a thick gallium nitride-based semiconductor layer having a flat surface over the entire substrate can be obtained when a thick film having a certain thickness or more is grown.
[0032] なお、横方向成長を利用する、第二の誘電体層による被覆領域上面の埋め込みを 効果的に行うためには、緩衝層を被覆する第二の誘電体層に設ける開口部を、密な 面密度で設ける必要がある。すなわち、成長初期において、第二の誘電体層表面に 降り注ぐ、 III族元素原料ならびに窒素原料は、第二の誘電体層表面を表面拡散し、 開口部の緩衝層表面での窒化ガリウム系半導体成長面に達する必要がある。成長 温度にも依存するが、第二の誘電体層表面において、 III族元素原料ならびに窒素 原料の表面拡散が可能な平均的距離と比較し、開口部間の平均間隔は、同程度ま たは、より短く選択することが好ましい。カロえて、第二の誘電体層に設ける開口部は、 基板面全体にわたり、規則的に配置することがより望ましい。少なくとも、基板面の各 部分領域において、個々の小領域内で平均した、開口部 Z (開口部と被覆領域)の 面積比率 (平均的開口比率）は、一定となるように、開口部を緻密な面密度で設ける ことが必要である。例えば、パターン 'エッチングによって、所望の幅を有する開口部 を挟んで、ストライプ状の第二の誘電体層を、一定のピッチで配置する手法が利用で きる。その際、前記ピッチ間隔を 10 m以下の範囲に選択し、ストライプ状第二の誘 電体層の幅は、開口部 Z (開口部と被覆領域)の面積比率 (平均的開口比率)が、 1 Z10以上、 4Z10以下の範囲となるように選択することが望ましい。カロえて、前記窒 化ガリウム系半導体における横方向成長は、結晶方位異方性を示すため、窒化ガリ ゥム系半導体層の成長面方位が（0001)の場合、前記ストライプ状開口部のストライ プの方向（長手方向）は、く 11 20 >もしくはく 1 100 >軸方向に選択することが 好ましい。 [0032] In order to effectively fill the upper surface of the covering region with the second dielectric layer using the lateral growth, an opening provided in the second dielectric layer covering the buffer layer must be formed. It must be provided with a high areal density. In other words, in the initial stage of growth, the Group III element material and the nitrogen material that pour down onto the surface of the second dielectric layer diffuse on the surface of the second dielectric layer, and grow the gallium nitride based semiconductor on the surface of the buffer layer in the opening. Need to reach the surface. Although it depends on the growth temperature, the average distance between the openings on the surface of the second dielectric layer is about the same as or similar to the average distance at which the surface diffusion of the group III element material and the nitrogen material is possible. , It is preferred to choose shorter. It is more preferable that the openings provided in the second dielectric layer are regularly arranged over the entire surface of the substrate. At least in each partial area of the substrate surface, the openings are densely packed so that the area ratio (average opening ratio) of the openings Z (opening and covering area), averaged within each small area, is constant. Provide with high areal density It is necessary. For example, a method of arranging a stripe-shaped second dielectric layer at a constant pitch with an opening having a desired width therebetween by pattern etching can be used. At this time, the pitch interval was selected to be within a range of 10 m or less, and the width of the stripe-shaped second dielectric layer was determined by the area ratio (average opening ratio) of the opening Z (the opening and the covering region). It is desirable to select the range of 1Z10 or more and 4Z10 or less. In fact, the lateral growth of the gallium nitride-based semiconductor shows crystal orientation anisotropy. Therefore, when the growth plane orientation of the gallium nitride-based semiconductor layer is (0001), the stripe of the stripe-shaped opening is stripped. The direction (longitudinal direction) is preferably selected to be 11 20> or 1 100> in the axial direction.
[0033] 力！]えて、上記の横方向成長機構を利用する際、ストライプ状開口部の幅に対して、 第二の誘電体層の膜厚が相対的に増し、力かる溝構造の深さ Z幅比力 ^を超えると 、ストライプ状開口部内の緩衝層表面力 ファセット状に成長した窒化ガリウム系半導 体を起点とする横方向成長が場合によっては困難とする。従って、ストライプ状開口 部の幅に対する、第二の誘電体層膜厚の比率 (溝構造の深さ Z幅比）は、 1Z1以下 、好ましくは 0. 2Z10— 2Z10の範囲に選択することが望ましい。  [0033] Power! When using the lateral growth mechanism described above, the thickness of the second dielectric layer is relatively increased with respect to the width of the stripe-shaped opening, and the depth of the groove structure is increased. If it exceeds ^, it is difficult in some cases to make lateral growth from a gallium nitride based semiconductor grown in a facet shape as a starting point. Therefore, it is desirable that the ratio of the thickness of the second dielectric layer to the width of the stripe-shaped opening (depth Z width ratio of the groove structure) is 1Z1 or less, preferably 0.2Z10-2Z10. .
[0034] 上記本発明の第二の形態においては、厚膜成長される窒化ガリウム系半導体層と 直接接する緩衝層表面は、前記開口部に露呈する部分のみとなる。従って、緩衝層 中に微細なピンホールなどを含む際、厚膜の窒化ガリウム系半導体層を堆積する間 に、緩衝層中のピンホールを介し、 GaZSiのメルトバック反応が局所的に生じるのは 、この開口部表面に限定される。従って、開口部 Z (開口部と被覆領域)の面積比率 (平均的開口比率)の減少に応じて、 GaZSiのメルトバック反応が局所的に生じる箇 所の総数も減少する効果が得られる。同時に、薄膜の Si (l l l)層を採用することで、 Siの供給量を制限し、反応が加速度的に進行することを抑制する効果と相俟って、 G aZSiメルトバックに起因する結晶劣化、その結果生じる表面のピット状欠陥に対して 、一層の低減効果が得られる。  [0034] In the second embodiment of the present invention, the surface of the buffer layer directly in contact with the gallium nitride-based semiconductor layer grown as a thick film is only a portion exposed to the opening. Therefore, when fine pinholes are included in the buffer layer, the melt-back reaction of GaZSi occurs locally through the pinholes in the buffer layer during the deposition of the thick gallium nitride based semiconductor layer. Is limited to the surface of the opening. Therefore, the effect of reducing the total number of locations where the melt back reaction of GaZSi occurs locally as the area ratio (average opening ratio) of the openings Z (the opening and the covering region) decreases is obtained. At the same time, the adoption of a thin Si (IIL) layer, combined with the effect of limiting the amount of Si supplied and suppressing the reaction from accelerating at an accelerated rate, has led to crystal degradation caused by the GaZSi meltback. As a result, the effect of further reducing pit-like defects on the surface can be obtained.
[0035] 前記第二の形態では、第二の誘電体層を利用して、部分的な被覆を施し、厚膜成 長される窒化ガリウム系半導体層と直接接する緩衝層表面は、前記開口部に露呈す る部分のみ限定している。それに対して、本発明にかかる第三の形態では、第一の 誘電体層上の Si (111)層と緩衝層との積層構造を部分的に残し、他の領域では、 Si (111)層と緩衝層との積層構造を除去し、第一の誘電体層表面を露出させることで、 厚膜成長される窒化ガリウム系半導体層と直接接する緩衝層表面を限定している。 [0035] In the second embodiment, the surface of the buffer layer, which is partially in contact with the gallium nitride-based semiconductor layer to be formed into a thick film by using the second dielectric layer, is partially covered with the opening. Only the parts that are exposed to the public are limited. In contrast, in the third embodiment according to the present invention, the first The laminated structure of the Si (111) layer and the buffer layer on the dielectric layer is partially left, and in other regions, the laminated structure of the Si (111) layer and the buffer layer is removed, and the first dielectric layer is removed. By exposing the surface, the surface of the buffer layer directly in contact with the gallium nitride based semiconductor layer to be grown thick is limited.
[0036] その際、露呈される第一の誘電体層は、その表面においては、窒化ガリウム系半導 体の成長核の形成が生じることのない誘電体材料を用いる。カロえて、この第一の誘 電体層は、 HVPE成長条件下で安定であり、また、緩衝層に用いる、第一の III族窒 化物半導体膜との間でィ匕学反応を生じないことも必要である。この三つの要件を満 足する第一の誘電体層用の誘電体材料としては、例えば、 SiO、 SiN、アルミ-ゥ  [0036] At this time, the exposed first dielectric layer uses a dielectric material that does not cause formation of a growth nucleus of a gallium nitride-based semiconductor on its surface. In short, the first dielectric layer is stable under HVPE growth conditions, and does not cause a dangling reaction with the first group III nitride semiconductor film used for the buffer layer. Is also necessary. Dielectric materials for the first dielectric layer that satisfy these three requirements include, for example, SiO, SiN, and aluminum- ゥ.
2  2
ム酸化物 (Al O )、または、 SiO N、あるいは、それらを組み合わせた積層膜が例  For example, oxide film (Al 2 O 3), SiO N, or a multilayer film combining them
2 3  twenty three
示できる。なかでも、第一の誘電体層に対して、 SiOを始めとする、 SiO Nで示され  Can be shown. In particular, the first dielectric layer is represented by SiON, including SiO.
2  2
る誘電体材料を用いることが好ま 、。  Preferably, a dielectric material is used.
[0037] 厚膜の窒化ガリウム系半導体層成長においては、成長初期には、第一の誘電体層 が露呈されて ヽる領域上への堆積は生じな ヽが、部分的に残されて ヽる緩衝層の表 面力 結晶成長が進行し、その後、横方向への成長が生じる。この横方向成長を利 用することで、成長膜厚が増すととともに、第一の誘電体層の露呈領域上面を横方 向成長層が覆い、最終的には、基板面全体に窒化ガリウム系半導体層の成長が進 む。その結果として、一定の膜厚以上の厚膜成長を行う際、基板全体に平坦な表面 を有する、厚膜の窒化ガリウム系半導体層が得られる。  In the growth of a thick gallium nitride-based semiconductor layer, in the initial stage of growth, deposition does not occur on a region where the first dielectric layer is exposed, but is partially left. The surface force of the buffer layer grows, and crystal growth proceeds, followed by lateral growth. By utilizing this lateral growth, the thickness of the grown film is increased, and at the same time, the upper surface of the exposed region of the first dielectric layer is covered by the lateral growth layer. The growth of the semiconductor layer proceeds. As a result, a thick gallium nitride based semiconductor layer having a flat surface over the entire substrate can be obtained when growing a thick film having a certain film thickness or more.
[0038] なお、横方向成長を利用する、第一の誘電体層露呈領域上面の埋め込みを効果 的に行うためには、緩衝層が残留する部分小領域を、密な面密度で設ける必要があ る。すなわち、成長初期において、第一の誘電体層表面に降り注ぐ、 III族元素原料 ならびに窒素原料は、第一の誘電体層表面を表面拡散し、残留部の緩衝層表面で の窒化ガリウム系半導体成長面に達する必要がある。成長温度にも依存するが、第 一の誘電体層表面において、 III族元素原料ならびに窒素原料の表面拡散が可能な 平均的距離と比較し、緩衝層の残留する小領域 (残留部）間の平均間隔は、同程度 または、より短く選択することが好ましい。カロえて、この緩衝層残留部は、基板面全体 にわたり、規則的に配置することがより望ましい。少なくとも、基板面の各部分領域に おいて、個々の小領域内で平均した、残留部 Z (残留部と露呈領域)の面積比率 (平 均的残留比率）は、一定となるように、緩衝層の残留部を緻密な面密度で設けること が必要である。例えば、マスク'エッチングによって、所望の幅を有する露呈部を挟ん で、ストライプ形状にエッチング加工された Si (111)層と緩衝層との積層構造を、一 定のピッチで残す手法が利用できる。その際、前記ピッチ間隔を 10 m以下の範囲 に選択し、ストライプ形状の Si(l l l)層と緩衝層との積層構造残留部の幅は、残留 部 Z (残留部と露呈領域)の面積比率 (平均的残留比率)が、 1Z10以上、 4Z10以 下の範囲となるように選択することが望ましい。カロえて、前記窒化ガリウム系半導体に おける横方向成長は、結晶方位異方性を示すため、窒化ガリウム系半導体層の成長 面方位が（0001)の場合、前記ストライプ状残留部のストライプの方向（長手方向）は 、く 11— 20>もしくはく 1— 100>軸方向に選択することが好ましい。 [0038] In order to effectively bury the upper surface of the first dielectric layer exposed region using lateral growth, it is necessary to provide a partial small region in which the buffer layer remains at a high area density. is there. In other words, in the initial stage of growth, the Group III element material and the nitrogen material that pour onto the surface of the first dielectric layer diffuse on the surface of the first dielectric layer, and grow the gallium nitride based semiconductor on the surface of the buffer layer in the remaining part. Need to reach the surface. Although it depends on the growth temperature, compared to the average distance over which the surface diffusion of the group III element material and the nitrogen material is possible on the surface of the first dielectric layer, The average interval is preferably selected to be equal or shorter. It is more preferable that the remaining portion of the buffer layer is regularly arranged over the entire surface of the substrate. At least, in each partial area on the substrate surface, the area ratio of the residual portion Z (the residual portion and the exposed region), It is necessary to provide the remaining portion of the buffer layer with a dense area density so that the average residual ratio is constant. For example, it is possible to use a method in which a layered structure of the Si (111) layer and the buffer layer, which are etched in a stripe shape, is left at a constant pitch by mask'etching with an exposed portion having a desired width therebetween. At this time, the pitch interval was selected to be within 10 m or less, and the width of the remaining portion of the laminated structure of the striped Si (ll) layer and the buffer layer was determined by the area ratio of the remaining portion Z (the remaining portion and the exposed region). It is desirable to select (average residual ratio) to be in the range of 1Z10 or more and 4Z10 or less. In fact, the lateral growth in the gallium nitride-based semiconductor exhibits crystal orientation anisotropy. Therefore, when the growth plane orientation of the gallium nitride-based semiconductor layer is (0001), the direction of the stripe of the stripe-shaped residual portion ( The longitudinal direction is preferably selected in the axial direction of 11-20> or 1-100>.
[0039] なお、上記の横方向成長機構を利用する際、ストライプ状露呈領域の幅に対して、 Si(l l l)層と緩衝層との積層構造膜厚、特には、 Si (l l l)層の膜厚が相対的に増しWhen the above-described lateral growth mechanism is used, the thickness of the laminated structure of the Si (ll) layer and the buffer layer, particularly the thickness of the Si (lll) layer, The film thickness increases relatively
、力かる溝構造の深さ Z幅比力 ^を超えると、その溝側面に露出する si(iii)層から の Siの供給が相対的に顕著となる。従って、この副次的影響を抑制するため、ストラ イブ状露呈領域部の幅に対する、 Si ( 111 )層と緩衝層との積層構造膜厚の比率 (溝 構造の深さ Z幅比）は、 1Z1以下、好ましくは 0. 2Z10— 2Z10の範囲に選択する ことが望ましい。換言すると、薄膜の Si(l l l)層と緩衝層との積層構造膜厚、特に、 薄膜の Si (111)層の膜厚は、 以下、好ましくは、 0. 2 m以下の範囲に選択 する際、ストライプ状露呈領域の幅は、 1 μ m— 10 mの範囲に選択することが可能 となる。 When the depth of the groove structure is greater than the specific width Z, the supply of Si from the si (iii) layer exposed on the side surface of the groove becomes relatively significant. Therefore, in order to suppress this secondary effect, the ratio of the thickness of the laminated structure of the Si (111) layer and the buffer layer to the width of the exposed stripe region (ratio of the depth Z width of the groove structure) is It is desirable to select a value within the range of 1Z1 or less, preferably 0.2Z10-2Z10. In other words, when the thickness of the laminated structure of the thin Si (ll) layer and the buffer layer, particularly the thickness of the thin Si (111) layer, is selected to be not more than 0.2 m, preferably not more than 0.2 m The width of the stripe-shaped exposed area can be selected in the range of 1 μm to 10 m.
[0040] カロえて、 Si (111)層と緩衝層との積層構造残留部において、下層の Si (111)層表 面を緩衝層が被覆する形態とする。すなわち、気相成長により、厚膜の窒化ガリウム 系半導体層を堆積する際、堆積される窒化ガリウム系半導体が下層の Si (l l l)層表 面と直接接触を生じない形態とする。その際、露呈される溝部の幅も微細であり、ま た、エッチングする Si (111)層と緩衝層とは異種材料であるので、両者を同時にマス ク 'エッチング除去でき、一方、第一の誘電体層はエッチングされない選択性を有す る手段として、塩素系ドライエッチング法の利用が適している。  It is assumed that the buffer layer covers the lower surface of the Si (111) layer in the remaining portion of the laminated structure of the Si (111) layer and the buffer layer. That is, when depositing a thick gallium nitride-based semiconductor layer by vapor phase growth, the deposited gallium nitride-based semiconductor does not directly contact the surface of the underlying Si (ll) layer. At this time, the width of the exposed groove is also fine, and since the Si (111) layer and the buffer layer to be etched are made of different materials, both can be masked and removed at the same time. Use of a chlorine-based dry etching method is suitable as a means having selectivity in which the dielectric layer is not etched.
[0041] 本発明にかかる第三の形態では、厚膜成長される窒化ガリウム系半導体層と直接 接する緩衝層表面は、エッチング加工された Si(l l l)層と緩衝層との積層構造の残 留部分に限定している。また、 GaZSiのメルトバック反応に関与する、薄膜の Si(l l 1)層も、この残留部分に限定されている。すなわち、緩衝層中に微細なピンホール などを含む際、厚膜の窒化ガリウム系半導体層を堆積する間に、緩衝層中のピンホ ールを介し、 GaZSiのメルトバック反応が局所的に生じるのは、この残留部表面に限 定される。従って、残留部 Z (残留部と露呈領域)の面積比率 (平均的残留比率)の 減少に応じて、 GaZSiのメルトバック反応が局所的に生じる箇所の総数も減少する 効果が得られる。同時に、薄膜の Si(l l l)層を採用し、かつ、残留している Si(l l l) 層の領域自体も限定されているため、一層 Siの供給量が制限され、反応が加速度的 に進行することをなお一層抑制する効果と相俟って、 GaZSiメルトバックに起因する 結晶劣化、その結果生じる表面のピット状欠陥に対して、格段の低減効果が得られる In the third embodiment according to the present invention, the gallium nitride-based semiconductor layer which is grown as a thick film is directly The surface of the buffer layer in contact is limited to the remaining portion of the laminated structure of the etched Si (ll) layer and the buffer layer. Further, the thin Si (ll 1) layer involved in the melt back reaction of GaZSi is also limited to the remaining portion. In other words, when a fine pinhole is included in the buffer layer, a GaZSi melt-back reaction occurs locally through the pinhole in the buffer layer while depositing the thick gallium nitride based semiconductor layer. Is limited to this residual surface. Therefore, as the area ratio (average residual ratio) of the residual portion Z (the residual portion and the exposed region) decreases, the effect is obtained that the total number of locations where the meltback reaction of GaZSi occurs locally also decreases. At the same time, since the thin Si (ll) layer is adopted and the area of the remaining Si (ll) layer itself is also limited, the supply amount of Si is further limited, and the reaction proceeds at an accelerated rate. Combined with the effect of further suppressing the occurrence of pitting defects on the crystal due to the melt back of GaZSi and the resulting pit-like defects on the surface.
[0042] 本発明にかかる窒化ガリウム系半導体基板の作製方法では、 SOI基板を利用し、 基板面全体に平坦な表面を有する、厚膜の窒化ガリウム系半導体層を堆積した後、 通常、 SOI基板と厚膜の窒化ガリウム系半導体層とを分離し、窒化ガリウム系半導体 自立基板の形態とする。その際、厚膜の窒化ガリウム系半導体層と SOI基板との界 面領域には、第一の誘電体層と薄膜の Si (l l l)層が存在しており、これらを選択的 に溶解可能なエッチング液を利用して、エッチング処理することで、分離を行うことが 可能である。この選択的エッチング処理に利用可能なエッチング液の例として、フッ 硝酸溶液を挙げることができる。 [0042] In the method for manufacturing a gallium nitride-based semiconductor substrate according to the present invention, an SOI substrate is used to deposit a thick gallium nitride-based semiconductor layer having a flat surface over the entire substrate surface. Is separated from the thick gallium nitride-based semiconductor layer to form a gallium nitride-based semiconductor free-standing substrate. At this time, the first dielectric layer and the thin Si (ll) layer exist in the interface region between the thick gallium nitride based semiconductor layer and the SOI substrate, and these can be selectively dissolved. Separation can be performed by etching using an etching solution. An example of an etchant that can be used for this selective etching process is a hydrofluoric / nitric acid solution.
[0043] 換言するならば、仮に、 SOI基板を構成する担体基板は、前記選択的エッチング処 理によって溶解されなくとも、界面領域を構成する第一の誘電体層と薄膜の Si (l l l )層を溶解除去できれば、厚膜の窒化ガリウム系半導体層を分離することが可能であ る。  In other words, even if the carrier substrate constituting the SOI substrate is not dissolved by the selective etching process, the first dielectric layer constituting the interface region and the thin Si (ll) layer constituting the interface region are formed. If gallium nitride-based semiconductor layers can be dissolved and removed, it is possible to separate a thick gallium nitride-based semiconductor layer.
[0044] 本発明に力かる窒化ガリウム系半導体基板の作製方法では、先に説明したように、 利用する SOI基板を構成する担体基板として、薄膜の Si(l l l)層と異なる材料から なる基板、あるいは、 Si (111)層と異なる面方位を有する Siバルタ基板を用いること ができる。 [0045] また、 SOI基板を構成する担体基板として、薄膜の Si (l l l)層と比較して、熱膨張 係数の面内異方性が異なる基板を利用することもできる。例えば、薄膜の Si(l l l) 層と異なる面方位を有する Siバルタ基板、例えば、 Si(100)基板では、その面内に 含まれる結晶方位が異なっており、熱熱膨張係数の面内異方性が相違している。 In the method of manufacturing a gallium nitride based semiconductor substrate according to the present invention, as described above, a substrate made of a material different from a thin Si (ll) layer may be used as a carrier substrate constituting an SOI substrate to be used. Alternatively, a Si Balta substrate having a plane orientation different from that of the Si (111) layer can be used. [0045] Further, as the carrier substrate constituting the SOI substrate, a substrate having a different in-plane anisotropy of the thermal expansion coefficient as compared with the thin Si (ll) layer can be used. For example, in a Si Balta substrate having a plane orientation different from that of a thin Si (ll) layer, for example, a Si (100) substrate, the crystal orientation contained in the plane is different, and the in-plane anisotropy of the thermal thermal expansion coefficient is obtained. Sex is different.
[0046] 薄膜の Si (l l l)層上に厚膜の窒化ガリウム系半導体層を堆積する際、 Si (l l l)層 と窒化ガリウム系半導体層とで熱膨張係数に差違があり、堆積後、冷却する間に、こ の熱膨張係数の差違に起因する歪み応力が生じる。この歪み応力は、 Si(l l l)層と 窒化ガリウム系半導体層との界面領域に集中する。カロえて、担体基板として、 Si (10 0)基板を選択すると、熱熱膨張係数の面内異方性が相違する結果、冷却する間に、 Si(100)基板と薄膜の Si(l l l)層との間にも、面内の歪み応力が生じる。従って、こ の二つの要因を有する歪み応力は、厚膜の窒化ガリウム系半導体層と SOI基板との 境界領域に集中している。  When depositing a thick gallium nitride based semiconductor layer on a thin Si (ll) layer, there is a difference in the thermal expansion coefficient between the Si (lll) layer and the gallium nitride based semiconductor layer. In the meantime, a strain stress occurs due to the difference in the coefficient of thermal expansion. This strain stress is concentrated in the interface region between the Si (ll) layer and the gallium nitride based semiconductor layer. If the Si (100) substrate is selected as the carrier substrate, the in-plane anisotropy of the coefficient of thermal expansion differs, and as a result, the Si (100) substrate and the thin Si (lll) layer In-plane strain stress is also generated between the two. Therefore, the strain stress having these two factors is concentrated in the boundary region between the thick gallium nitride based semiconductor layer and the SOI substrate.
[0047] 例えば、本発明の第三の形態では、 Si (111)層と緩衝層との積層構造はエツチン グ加工されており、厚膜の窒化ガリウム系半導体層と SOI基板との境界領域の一部 を占めているのみである。この場合には、境界領域に集中している面内方向の歪み 応力により、エッチング加工された Si (111)層と緩衝層との積層構造部分、 Si (111) 層と緩衝層との界面、あるいは、第一の誘電体膜と薄膜の Si (111)層との界面にお ける剥離が引き起こされることもある。すなわち、面内方向の歪み応力が境界領域に 集中する際、エッチング加工に伴い、残留部 Z (残留部と露呈領域)の面積比率 (平 均的残留比率)が一定比率以下となると、異種材料間の界面における剪断が優先し て進行する。  For example, in the third embodiment of the present invention, the laminated structure of the Si (111) layer and the buffer layer is etched, and the boundary region between the thick gallium nitride based semiconductor layer and the SOI substrate is formed. It only accounts for a part. In this case, due to in-plane strain stress concentrated in the boundary region, the laminated structure portion of the etched Si (111) layer and the buffer layer, the interface between the Si (111) layer and the buffer layer, Alternatively, delamination may occur at the interface between the first dielectric film and the thin Si (111) layer. In other words, when strain stress in the in-plane direction is concentrated on the boundary region, when the area ratio (average residual ratio) of the residual portion Z (residual portion and exposed region) becomes less than a certain ratio due to etching, different materials are used. Shearing at the interface between them proceeds with priority.
[0048] この Si ( 111)層と窒化ガリゥム系半導体層間における熱膨張係数の差異、ならび に薄膜の Si(l l l)層と担体基板の熱膨張係数面内異方性の相違を利用することで [0048] The difference in thermal expansion coefficient between the Si (111) layer and the gallium nitride-based semiconductor layer, and the difference in the in-plane anisotropy of the thermal expansion coefficient between the thin Si (ll) layer and the carrier substrate can be obtained.
、厚膜の窒化ガリウム系半導体層の堆積後、冷却する間に、自発的に分離する効果 が得られる。この現象は、担体基板サイズが大きくなるとともに、より顕著なものとなり、 成長後に、担体基板を除去するための研磨やィ匕学エッチング処理を行うことなぐ窒 化ガリウム系半導体基板を得ることができ、工程上大きな利点となる。なお、冷却する 間に、自発的に分離する厚膜の窒化ガリウム系半導体層の裏面には、 Si(l l l)層と 緩衝層との積層構造の一部が残余することがある。従って、一般に、力かる残渣を除 去する目的で、裏面研磨やィ匕学エッチング処理を施し、目的の窒化ガリウム系半導 体自立基板とする。 After the deposition of the thick gallium nitride based semiconductor layer, an effect of spontaneous separation can be obtained during cooling. This phenomenon becomes more remarkable as the carrier substrate size increases.After growth, a gallium nitride-based semiconductor substrate can be obtained without performing polishing or etching treatment for removing the carrier substrate. This is a great advantage in the process. During cooling, a Si (ll) layer is formed on the back of the thick gallium nitride-based semiconductor layer that spontaneously separates. A part of the laminated structure with the buffer layer may remain. Therefore, in general, for the purpose of removing strong residues, the back surface is polished or etched to obtain a desired gallium nitride-based semiconductor free-standing substrate.
[0049] また、本発明の第一の形態、あるいは、第二の形態においては、薄膜の Si(l l l) 層と担体基板の熱膨張係数面内異方性の相違があっても、冷却する間に、自発的な 分離に至らないことが少なくない。しかし、その場合にも、担体基板と厚膜の窒化ガリ ゥム系半導体層の境界領域には、面内に歪み応力が蓄積されており、例えば、第一 の誘電体膜、ならびに、薄膜の Si (111)層に対して、面内方向に歪み応力が加わつ ている。第一の誘電体膜、ならびに、薄膜の Si(l l l)層に対する選択的なエツチン グを施す際、その内部歪み応力に起因し、これら層状部分の横方向のエッチングが 促進される効果が発揮されることもある。  [0049] Further, in the first mode or the second mode of the present invention, cooling is performed even if there is a difference in the in-plane anisotropy of the thermal expansion coefficient between the Si (ll) layer of the thin film and the carrier substrate. In the interim, spontaneous separation often does not occur. However, also in this case, in the boundary region between the carrier substrate and the thick gallium nitride-based semiconductor layer, strain stress is accumulated in the plane, and for example, the first dielectric film and the thin film Strain stress is applied to the Si (111) layer in the in-plane direction. When selective etching is performed on the first dielectric film and the thin Si (ll) layer, the effect of promoting the lateral etching of these layered portions is exhibited due to the internal strain stress. Sometimes.
実施例  Example
[0050] 以下に、実施例を示して、本発明にかかる窒化ガリウム系半導体基板の作製方法 を具体的に説明する。なお、下記する実施例は、本発明にかかる最良の実施形態の 一例ではあるが、本発明は、これら実施例に示す実施形態に限定されるものではな い。  Hereinafter, a method for manufacturing a gallium nitride-based semiconductor substrate according to the present invention will be specifically described with reference to examples. The following examples are examples of the best embodiments according to the present invention, but the present invention is not limited to the embodiments shown in these examples.
[0051] (実施例 1)  (Example 1)
図 1に、本発明の第一の形態に力かる窒化ガリウム系半導体基板の作製方法によ る本実施例 1の作製工程を、また、図 2に、従来の手法を利用する窒化ガリウム系半 導体基板の作製工程を示す。  FIG. 1 shows the manufacturing process of the first embodiment according to the method for manufacturing a gallium nitride based semiconductor substrate according to the first embodiment of the present invention, and FIG. 2 shows a gallium nitride based semiconductor substrate using a conventional method. The manufacturing process of a conductive substrate is shown.
[0052] 図 1に示す、本実施例 1の作製工程においては、基板として、貼り合せ法により作 製された、 2インチ Si (111) SOI基板を利用している。すなわち、該 Si (l l l) SOI基 板は、 300 m厚の 2インチ Si (111)バルタ基板 101上に、 lOOnm厚の SiO膜 102 In the manufacturing process of the first embodiment shown in FIG. 1, a 2-inch Si (111) SOI substrate manufactured by a bonding method is used as a substrate. That is, the Si (ll) SOI substrate is formed on a 2-inch Si (111) Balta substrate 101 having a thickness of 300 m by a SiO film 102 having a thickness of 100 nm.
2 を介して、 Si (111)層 103が張り合わせられた SOI (silicon on insulator)構造で ある。表面側の Si (111)層 103は、張り合わせ後、研磨によって厚さ 0.： mまで薄 層化し、その表面は鏡面研磨により、 Si(l l l)面とされている。一方、図 2に示す、従 来の手法による作製工程においては、基板として、 2インチ Si (111)バルタ基板 201 を利用している。 [0053] Si(lll)SOI基板表面の Si(lll)層 103上に、次の手順 ·条件で 0. 厚の A1 N膜 104を堆積し、試料 Aを作製する。 SOI基板を RCA洗浄後、 MOCVD成長装 置に導入し、水素と窒素の混合雰囲気中で 1050°Cまで昇温する。昇温後、 NHを It has an SOI (silicon on insulator) structure in which a Si (111) layer 103 is bonded to the substrate via the second layer. After bonding, the Si (111) layer 103 on the surface side is thinned to a thickness of 0: m by polishing, and the surface is made into a Si (ll) surface by mirror polishing. On the other hand, in the manufacturing process according to the conventional method shown in FIG. 2, a 2-inch Si (111) Balta substrate 201 is used as a substrate. A sample A is prepared by depositing a 0.1-nm thick A1N film 104 on the Si (lll) layer 103 on the surface of the Si (lll) SOI substrate by the following procedure and conditions. After RCA cleaning of the SOI substrate, it is introduced into the MOCVD growth equipment, and the temperature is raised to 1050 ° C in a mixed atmosphere of hydrogen and nitrogen. After heating, NH
3 導入し、 Si(lll)表面に 10分間のァニール処理を施す。その後、 NHの導入を継  3 Introduce and subject the Si (lll) surface to annealing for 10 minutes. After that, continued the introduction of NH
3  Three
続し、基板温度を 1050°Cに保持したまま、トリメチルアルミニウム (TMA)を供給して 、 Si(lll)表面上に A1N膜を堆積する。所望の膜厚 0. 2 mに達する堆積時間、 T MAの供給を行い、 A1N膜の堆積を継続する。次いで、 NHの導入を継続した状態  Subsequently, while maintaining the substrate temperature at 1050 ° C., trimethylaluminum (TMA) is supplied to deposit an A1N film on the Si (ll) surface. The TMA is supplied for the deposition time to reach the desired film thickness of 0.2 m, and the deposition of the A1N film is continued. Next, the state where introduction of NH was continued
3  Three
で、 TMAの供給を停止し、 A1N膜堆積を終了する。その後、室温まで冷却して、 M OCVD装置から、 Si (111)表面上に緩衝層用の A1N膜が形成された試料 Aを取り 出した。  Then, supply of TMA is stopped, and A1N film deposition is completed. Thereafter, the sample A was cooled to room temperature, and a sample A in which an A1N film for a buffer layer was formed on the Si (111) surface was taken out from the MOCVD apparatus.
[0054] また、 Si(lll)バルタ基板 201の Si(lll)表面上にも、同様の手順 ·条件で 0. 2μ m厚の A1N膜 202を堆積し、試料 Bを作製する。  Also, an A1N film 202 having a thickness of 0.2 μm is deposited on the Si (ll) surface of the Si (ll) Balta substrate 201 in the same procedure and under the same conditions, thereby preparing a sample B.
[0055] Si (111)表面に緩衝層として、 0. 2 m厚の A1N膜を形成した、上記試料 A、 Bを[0055] The above samples A and B, in each of which a 0.2 m thick A1N film was formed as a buffer layer on the Si (111) surface, were used.
HVPE装置に導入し、 GaClと NHを原料ガスとする、 HVPE成長法により、基板温 HVPE growth method using GaCl and NH as source gases
3  Three
度 1020。Cで 300/zmのアンドープ GaN厚膜 105、 203を A1N膜 104、 202上にそ れぞれ堆積した。 GaN厚膜の堆積後、室温まで冷却し、 HVPE装置から取り出す。 その後、フッ硝酸溶液に浸して、基板 Siを溶解させ、 300 mのアンドープ GaN厚膜 を分離した。  Degree 1020. 300 / zm thick undoped GaN thick films 105 and 203 were deposited on the A1N films 104 and 202, respectively. After the deposition of the GaN thick film, it is cooled to room temperature and taken out of the HVPE equipment. Then, the substrate was immersed in a hydrofluoric-nitric acid solution to dissolve the substrate Si, and a 300-m thick undoped GaN film was separated.
[0056] 試料 B上に作製した GaN厚膜 203では、 Gaと Siのメルトバック反応により、 GaN膜 は多結晶化しており、 Si基板の溶解後、細かい破片となった。一方、試料 A上に作製 した GaN厚膜 105は、 Si基板の溶解後、細力 、破片とはならず、自立 GaN基板が得 られた。ただし、得られた自立 GaN基板において、 2インチ面内、 40— 50箇所に Ga と Si反応が局所的に生じており、表面にピット状の欠陥として観察された。両者の結 果を対比させると、試料 Aにおいても、緩衝層の A1N膜に存在するピンホールにおい て、 Gaと Si反応が生じるものの、 SOI基板の SiO膜 102によって、 Gaと Siのメルトバ  [0056] In the GaN thick film 203 produced on the sample B, the GaN film was polycrystallized by the melt back reaction of Ga and Si, and became fine fragments after dissolution of the Si substrate. On the other hand, the GaN thick film 105 formed on the sample A did not become fine or broken after the dissolution of the Si substrate, and a freestanding GaN substrate was obtained. However, in the obtained freestanding GaN substrate, Ga and Si reactions occurred locally in 40 to 50 places within a 2-inch plane, and pit-like defects were observed on the surface. Comparing the two results, in sample A, Ga and Si react in the pinholes in the A1N film of the buffer layer, but the melt film of Ga and Si is formed by the SiO film 102 on the SOI substrate.
2  2
ック反応の更なる進行は停止されている。その結果、 Gaと Siに因る反応に起因する 結晶劣化は、局所的な領域に限定され、 GaN膜全体に及ぶ多結晶化は回避されて いる。以上の結果より、担体基板上に、第一の誘電体層、本例においては、シリコン 酸化膜を介して形成されている Si (l l l)薄層を基板として利用することに伴う、本発 明の効果が検証される。 Further progress of the lock reaction has been stopped. As a result, crystal degradation due to the reaction caused by Ga and Si is limited to a local region, and polycrystallization over the entire GaN film is avoided. From the above results, on the carrier substrate, the first dielectric layer, in this example, silicon The effect of the present invention by using a Si (lll) thin layer formed via an oxide film as a substrate is verified.
[0057] (実施例 2)  (Example 2)
図 3に、本発明の第二の形態に力かる窒化ガリウム系半導体基板の作製方法によ る本実施例 2の作製工程を示す。図 3に示す、本実施例 2の作製工程においても、基 板として、貼り合せ法により作製された、 2インチ Si(l l l) SOI基板を利用している。 また、本実施例 2において利用する SOI基板も、 300 m厚の 2インチ Si (111)バル ク基板 301上に、 lOOnm厚の SiO膜 302を介して、 Si(l l l)層 303が張り合わせら  FIG. 3 shows a manufacturing process of Example 2 by a method of manufacturing a gallium nitride-based semiconductor substrate according to the second embodiment of the present invention. Also in the manufacturing process of Example 2 shown in FIG. 3, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as a substrate. Further, the SOI substrate used in the second embodiment also has a Si (ll) layer 303 laminated on a 300-m thick 2-inch Si (111) bulk substrate 301 via a lOOnm thick SiO film 302.
2  2
れた SOI (silicon on insulator)構造である。表面側の Si (111)層 303は、張り合 わせ後、研磨によって厚さ 0. 1 μ mまで薄層化し、その表面は鏡面研磨により、 Si (l 11)面とされている。  SOI (silicon on insulator) structure. After bonding, the Si (111) layer 303 on the front side is thinned to a thickness of 0.1 μm by polishing, and its surface is made into a Si (111) surface by mirror polishing.
[0058] この Si (l l l) SOI基板表面の Si(l l l)層 303上に、緩衝層として、実施例 1に記 載する手順'条件で 0. 2 m厚の A1N膜 304を堆積する。次いで、緩衝層用の A1N 膜 304表面に、 300nm厚の SiO膜を堆積し、フォトリソグラフィ一によりパターユング  [0058] On the Si (ll) layer 303 on the surface of the Si (ll) SOI substrate, an A1N film 304 having a thickness of 0.2 m is deposited as a buffer layer under the conditions described in the first embodiment. Next, a 300 nm thick SiO film is deposited on the surface of the A1N film 304 for the buffer layer, and patterned by photolithography.
2  2
して、基板表面全面に、ストライプ間に幅 2 m開口部を設ける、 SiOストライプ 305  Then, a 2 m wide opening is provided between the stripes on the entire surface of the substrate.
2  2
を 10 μ mピッチで作製した。  Were prepared at a pitch of 10 μm.
[0059] この緩衝層用の A1N膜 304表面に、周期的な SiOストライプ 'マスクパターン 305 On the surface of the A1N film 304 for the buffer layer, a periodic SiO stripe 'mask pattern 305
2  2
を形成した試料 Cを HVPE装置に導入し、実施例 1に記載する GaN厚膜形成工程と 同様の工程'条件で、 300 mのアンドープ GaN厚膜 306を堆積した。その後、フッ 硝酸溶液に浸して、基板 Siを溶解させて、 300 mのアンドープ GaN厚膜を分離し 、 自立 GaN基板を得た。  The sample C on which was formed was introduced into the HVPE apparatus, and an undoped GaN thick film 306 of 300 m was deposited under the same conditions as those of the GaN thick film forming step described in Example 1. Thereafter, the substrate Si was dissolved in a hydrofluoric / nitric acid solution to dissolve the substrate Si, and a 300-m thick undoped GaN thick film was separated to obtain a freestanding GaN substrate.
[0060] 上記試料 C上に作製した GaN厚膜 306からなる自立 GaN基板では、 2インチ面内 、 3箇所で表面にピット状の欠陥が観察された。本実施例 2では、緩衝層用の A1N膜 304表面に、周期的な SiOストライプ 'マスクパターン 305を形成し、その開口部の A [0060] In the self-standing GaN substrate composed of the GaN thick film 306 fabricated on the sample C, pit-like defects were observed on the surface at three places in a 2-inch plane. In the second embodiment, a periodic SiO stripe 'mask pattern 305 is formed on the surface of the buffer layer A1N film 304, and the A
2  2
IN膜表面力も GaN成長を行っている。従って、露出している A1N膜表面積は、基板 全表面の 2Z10と小さくなつており、その領域に形成される A1N膜中のピンホール数 もその比率で減少する。結果として、前記開口部に存在する A1N膜中のピンホール に起因している、 Gaと Si反応の生じる確率も小さくなり、対応して、ピット状の欠陥数 の減少が達成されていると理解される。 GaN is growing on the surface of the IN film. Therefore, the surface area of the exposed A1N film is as small as 2Z10 on the entire surface of the substrate, and the number of pinholes in the A1N film formed in that region also decreases at that ratio. As a result, the probability of a Ga-Si reaction occurring due to pinholes in the A1N film present in the opening is reduced, and the number of pit-like defects is correspondingly reduced. It is understood that a reduction in
[0061] (実施例 3)  (Example 3)
図 4に、本発明の第三の形態に力かる窒化ガリウム系半導体基板の作製方法によ る本実施例 3の作製工程を示す。図 4に示す、本実施例 3の作製工程においても、基 板として、貼り合せ法により作製された、 2インチ Si(l l l) SOI基板を利用している。 この SOI基板は、実施例 1に記載される作製方法により作製され、 300 /z m厚 2イン チ Si (111)ノ ノレク基板 401/0. 1 m厚 SiO膜 402/0. 1 m厚 Si (111)層 403  FIG. 4 shows a manufacturing process of Example 3 by a method of manufacturing a gallium nitride-based semiconductor substrate according to the third embodiment of the present invention. Also in the manufacturing process of the third embodiment shown in FIG. 4, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as a substrate. This SOI substrate was manufactured by the manufacturing method described in Example 1, and a 300 / zm-thick 2-inch Si (111) nonolec substrate 401 / 0.1-m thick SiO film 402 / 0.1-m-thick Si ( 111) Layer 403
2  2
の構造を有している。  It has the following structure.
[0062] この Si (l l l) SOI基板表面の Si(l l l)層 403上に、緩衝層として、実施例 1に記 載する手順'条件で 0. 厚の A1N膜 404を堆積する。次に、 A1N膜 404表面に 、レジストを塗布し、フォトリソグラフィ一によりパターユングして、基板表面全面に、ス トライプ間に幅 8 μ m開口部を設ける、レジストストライプを 10 μ mピッチで作製した。 引続き、レジストストライプをエッチング 'マスクとして、塩素系ドライエッチングを用い、 SOI基板中の SiO層 402が露出するまで開口部の A1N膜 404ZSi層 403を選択的  [0062] On the Si (ll) layer 403 on the surface of the Si (ll) SOI substrate, an A1N film 404 having a thickness of 0 is deposited as a buffer layer under the conditions described in the first embodiment. Next, a resist is applied to the surface of the A1N film 404 and patterned by photolithography to form an 8 μm wide opening between stripes on the entire surface of the substrate, and a resist stripe is formed at a 10 μm pitch. did. Using the resist stripe as an etching mask and chlorine-based dry etching, select the A1N film 404 and the ZSi layer 403 in the opening until the SiO layer 402 in the SOI substrate is exposed.
2  2
に除去し、ストライプ状の AlNZSi (111) 405を形成した。  Then, striped AlNZSi (111) 405 was formed.
[0063] レジスト除去'表面洗浄後、前記周期的な AlNZSi (l l l)ストライプ 'パターン 405 が形成された試料を HVPE装置に導入し、実施例 1に記載する GaN厚膜形成工程 と同様の工程'条件で、 300 mのアンドープ GaN厚膜 406を堆積した。その後、フ ッ硝酸溶液に浸して、基板 Siを溶解させて、 300 mのアンドープ GaN厚膜を分離 し、 自立 GaN基板を得た。  [0063] After removing the resist 'after surface cleaning, the sample on which the periodic AlNZSi (llll) stripe' pattern 405 was formed was introduced into an HVPE apparatus, and the same step as the GaN thick film forming step described in Example 1 ' Under the conditions, a 300-m thick undoped GaN thick film 406 was deposited. Then, the substrate Si was immersed in a hydrofluoric-nitric acid solution to dissolve the substrate Si, and a undoped GaN thick film of 300 m was separated to obtain a freestanding GaN substrate.
[0064] 上記試料上に作製した GaN厚膜 406からなる自立 GaN基板では、 2インチ面内、 その表面にピット状の欠陥は観察されな力つた。本実施例 3では、周期的なストライプ 'パターン形状にエッチングカ卩ェされている、緩衝層用の A1N膜 404から GaN成長 が開始している。一方、得られた自立 GaN基板の裏面を詳細に観察すると、前記周 期的な AlNZSi ( 111)ストライプ ·パターン 405に相当する部位の数箇所で、 Gaと Si の反応痕跡が見 ヽだされた。  [0064] In the self-standing GaN substrate composed of the GaN thick film 406 fabricated on the sample, no pit-like defects were observed on the surface within 2 inches. In the third embodiment, GaN growth starts from the A1N film 404 for the buffer layer, which has been etched into a periodic stripe pattern. On the other hand, when the back surface of the obtained free-standing GaN substrate was observed in detail, traces of reaction between Ga and Si were found at several locations corresponding to the periodic AlNZSi (111) stripe pattern 405. .
[0065] 周期的なストライプ 'パターン形状にエッチング加工する結果、残余している A1N膜 表面積は、基板全表面の 2Z10と小さくなつており、その領域に形成される A1N膜中 のピンホール数もその比率で減少している。同じぐ表面に残余する Si層 403の総量 も、 2Z10と少なくなつている。そのため、前記ストライプ 'パターン部に存在する A1N 膜中のピンホールに起因している、 Gaと Siの反応の生じる確率も小さくなり、同時に 、 Gaと Siの反応も、早い段階で自己停止する。結果として、 GaN厚膜 406の成長過 程初期に、局所的な Gaと Siの反応は生じるものの、早い段階で自己停止し、表面に ピット状の欠陥を生じさせるに到らな力つたと理解される。 The surface area of the remaining A1N film as a result of etching processing in a periodic stripe 'pattern shape is as small as 2Z10 on the entire surface of the substrate, and the surface area of the A1N film formed in that region is small. The number of pinholes also decreased at that rate. The total amount of the Si layer 403 remaining on the same surface is also reduced to 2Z10. Therefore, the probability of the reaction between Ga and Si caused by the pinhole in the A1N film present in the stripe 'pattern portion is reduced, and at the same time, the reaction between Ga and Si is stopped at an early stage. As a result, it was understood that although a local reaction of Ga and Si occurred in the early stage of the growth of the GaN thick film 406, it self-stopped at an early stage and led to a pit-like defect on the surface. Is done.
[0066] (実施例 4) (Example 4)
図 5に、本発明の第三の形態に力かる窒化ガリウム系半導体基板の作製方法を応 用している、本実施例 4の作製工程を示す。図 5に示す、本実施例 4の作製工程にお いても、基板として、貼り合せ法により作製された、 2インチ Si(l l l) SOI基板を利用 している。なお、本実施例 4において利用する SOI基板も、 300 m厚の 2インチ Si ( 100)ノ ノレク基板 501上に、 lOOnm厚の SiO膜 502を介して、 Si(l l l)層 503力 ^張  FIG. 5 shows a manufacturing process of Example 4 in which the method for manufacturing a gallium nitride based semiconductor substrate according to the third embodiment of the present invention is applied. Also in the manufacturing process of Example 4 shown in FIG. 5, a 2-inch Si (ll) SOI substrate manufactured by a bonding method is used as the substrate. The SOI substrate used in the present embodiment 4 also has a Si (ll) layer 503 on a 2-inch Si (100) NOREK substrate 501 having a thickness of 300 m via a SiO film 502 having a thickness of 100 nm.
2  2
り合わせられた SOI (silicon on insulator)構造である。表面側の Si (111)層 503 は、張り合わせ後、研磨によって厚さ 0. 1 μ mまで薄層化し、その表面は鏡面研磨に より、 Si (111)面とされている。  SOI (silicon on insulator) structure combined. After lamination, the Si (111) layer 503 on the front side is thinned to a thickness of 0.1 μm by polishing, and the surface is mirror-polished to the Si (111) plane.
[0067] この Si (l l l) SOI基板表面の Si(l l l)層 503上に、緩衝層として、実施例 1に記 載する手順'条件で 0. 2 m厚の A1N膜 504を堆積する。次に、実施例 3と同様に、 A1N膜 504表面に、レジストを塗布し、フォトリソグラフィ一によりパターユングして、基 板表面全面に、ストライプ間に幅 8 μ m開口部を設ける、レジストストライプを 10 m ピッチで作製した。引続き、レジストストライプをエッチング 'マスクとして、塩素系ドライ エッチングを用い、 SOI基板中の SiO層 502が露出するまで開口部の A1N膜 504 An A1N film 504 having a thickness of 0.2 m is deposited as a buffer layer on the Si (ll) layer 503 on the surface of the Si (ll) SOI substrate under the conditions described in the first embodiment. Next, in the same manner as in Example 3, a resist is applied to the surface of the A1N film 504 and patterned by photolithography to form openings of 8 μm width between stripes on the entire surface of the substrate. Were fabricated at a pitch of 10 m. Using the resist stripe as an etching mask and chlorine-based dry etching, the A1N film 504 in the opening is exposed until the SiO layer 502 in the SOI substrate is exposed.
2  2
ZSi層 503を選択的に除去し、ストライプ状の AlNZSi (111) 505を形成した。  The ZSi layer 503 was selectively removed to form a stripe-shaped AlNZSi (111) 505.
[0068] 実施例 3の工程と同様に、レジスト除去'表面洗浄後、前記周期的な AlNZSi (11 1)ストライプ 'パターン 505が形成された試料を HVPE装置に導入し、実施例 1に記 載する GaN厚膜形成工程と同様の工程'条件で、 300 mのアンドープ GaN厚膜 5 06を堆積した。 GaN厚膜の堆積後、室温まで冷却し、 HVPE装置から取り出すと、 実施例 3とは異なり、冷却過程において、 GaN厚膜 506と Si (100)バルタ基板 501と の層間で自発的な剥離が生じていた。結果的に、フッ硝酸溶液に浸して、基板 Siを 溶解させる操作なしで、自立 GaN基板が得られた。 As in the process of Example 3, after removing the resist and cleaning the surface, the sample on which the periodic AlNZSi (11 1) stripe “pattern 505” was formed was introduced into an HVPE apparatus, and described in Example 1. An undoped GaN thick film 506 of 300 m was deposited under the same conditions as those of the GaN thick film forming step. After the GaN thick film is deposited, it is cooled down to room temperature and taken out of the HVPE apparatus, and unlike the third embodiment, spontaneous peeling between the GaN thick film 506 and the Si (100) Balta substrate 501 occurs during the cooling process. Had occurred. As a result, the substrate Si is immersed in hydrofluoric-nitric acid solution A freestanding GaN substrate was obtained without any dissolving operation.
[0069] なお、上記実施例 3で作製された自立 GaN基板と同様に、本実施例 4において作 製した GaN厚膜 506からなる自立 GaN基板でも、 2インチ面内、その表面にピット状 の欠陥は観察されなカゝつた。本実施例 4でも、周期的なストライプ 'パターン形状にェ ツチングカ卩ェされている、緩衝層用の A1N膜 504力も GaN成長が開始している。また 、得られた自立 GaN基板の裏面を詳細に観察すると、前記周期的な AlNZSi(l l l )ストライプ ·パターン 505に相当する部位の数箇所で、 Gaと Siの反応痕跡が見 、だ された。 Note that, similarly to the self-standing GaN substrate manufactured in Example 3 above, the self-standing GaN substrate made of the GaN thick film 506 manufactured in Example 4 also has a pit-shaped surface within 2 inches. No defects were observed. Also in the fourth embodiment, the growth of GaN is started with the A1N film 504 for the buffer layer, which is etched in a periodic stripe pattern pattern. Further, when the back surface of the obtained free-standing GaN substrate was observed in detail, traces of reaction between Ga and Si were found at several portions corresponding to the periodic AlNZSi (ll) stripe pattern 505.
[0070] 一方、本実施例 4にお 、て、 GaN厚膜成長後、その冷却過程で生じた、 GaN厚膜 506と Si (100)バルタ基板 501との間の剥離は、 GaNと Siの熱膨張係数差に起因す る歪み応力に起因して ヽると理解される。実施例 3で利用して ヽる Si (111)バルタ基 板と本実施例 4で利用して 、る Si (100)バルタ基板とでは、その結晶方位が異なる 力 一方、 Si(l l l)層表面に形成された緩衝層の A1N膜から成長が進行する GaN 厚膜の結晶方位は、実施例 3と実施例 4では同じものとなっている。すなわち、実施 例 3と実施例 4においては、用いている Siバルタ結晶の結晶方位の違いに伴い、 Ga Nと Siの熱膨張係数差に起因する歪み応力に差違がある。従って、実施例 3におい ては、 GaNと Siの熱膨張係数差に起因する歪み応力は、両者の境界領域を形成す る、周期的なエッチングカ卩ェされている、 AlNZSi (l l l)ストライプ 'パターン部にお ける剥離を引き起こす閾値には至らないが、実施例 4においては、歪み応力が、この AIN/Si ( 111)ストライプ ·パターン部における剥離を引き起こす閾値を超えた結果 と理解される。  On the other hand, in Example 4, the separation between the GaN thick film 506 and the Si (100) Balta substrate 501, which occurred during the cooling process after the growth of the GaN thick film, was caused by the separation between GaN and Si. It is understood that this is caused by the strain stress caused by the difference in thermal expansion coefficient. The Si (111) Balta substrate used in Example 3 and the Si (100) Balta substrate used in Example 4 have different crystal orientations. The crystal orientation of the GaN thick film growing from the A1N film of the buffer layer formed in Example 3 is the same in Example 3 and Example 4. That is, in Example 3 and Example 4, there is a difference in strain stress caused by a difference in thermal expansion coefficient between GaN and Si due to a difference in crystal orientation of the Si Balta crystal used. Therefore, in Example 3, the strain stress caused by the difference in the thermal expansion coefficient between GaN and Si is due to the periodic etching of the AlNZSi (lll) stripe that forms the boundary region between the two. Although it does not reach the threshold value that causes peeling in the pattern portion, in Example 4, it is understood that the strain stress exceeds the threshold value that causes peeling in the AIN / Si (111) stripe / pattern portion.
[0071] (その他の実施態様）  (Other Embodiments)
上記実施例 1一 4においては、 Siと GaNの格子定数差に起因する結晶成長上の問 題を緩和する目的で、 A1N膜を緩衝層として用いている。この目的における緩衝層と しての効果を損なわな!/、範囲で、 A1に代えて、 Gaや Inを含む Al Ga In N混晶、 もしくは超格子を緩衝層に用いる場合にも、同様に本発明の効果が発揮される。そ の際、緩衝層として利用する、 Al Ga In N混晶中の Ga、 Inの含有比率 y、 1-χ- yを、 Siと GaNの格子定数差に起因する歪み応力の緩和作用が、 A1Nよりも大きく劣 らない範囲に選択する。あるいは、 Al Ga In N超格子において、その平均され た格子定数を、前記緩衝層として好適に利用可能な組成の Al Ga In N混晶が 示す格子定数と同程度に選択する。また、 Si (l l l)層と接する Al Ga In N混晶 中に含まれる Gaにより、その界面で GaZSiメルトバック反応が顕著に進行しない範 囲に、 Gaの含有比率 yを選択する。 In Examples 14 to 14, the A1N film is used as the buffer layer in order to alleviate the problem of crystal growth caused by the lattice constant difference between Si and GaN. The effect as a buffer layer for this purpose is not impaired! / In the range, Al Ga In N mixed crystal containing Ga or In or a superlattice or a superlattice is used for the buffer layer instead of A1. The effects of the present invention are exhibited. At this time, the content ratio y, 1-、-y of Ga and In in the AlGaInN mixed crystal used as the buffer layer is determined by the effect of relaxing the strain stress caused by the lattice constant difference between Si and GaN. Greatly inferior to A1N Select a range that does not Alternatively, in the AlGaInN superlattice, the averaged lattice constant is selected to be substantially the same as the lattice constant of an AlGaInN mixed crystal having a composition suitably usable as the buffer layer. Further, the Ga content ratio y is selected so that the GaZSi melt-back reaction does not significantly proceed at the interface due to Ga contained in the AlGaInN mixed crystal in contact with the Si (ll) layer.
[0072] 上記実施例 1一 4においては、作製される厚膜の III族窒化物半導体層が GaNの例 を示した。本発明において解決すべき課題の第一は、 Ga/Siメルトバック反応の抑 制であるが、 A1および Inは、 Gaと比較して、 Siと接した際、メルトバックを引き起こす 反応性が極めて低い。一方、作製される厚膜の III族窒化物半導体層は、 GaNに代 えて、 Al In Ga N混晶とする際、 Gaの含有比率は若干低下する力 依然としてIn Examples 14 to 14, the example in which the thick group III nitride semiconductor layer to be manufactured is GaN is described. The first problem to be solved in the present invention is the suppression of the Ga / Si meltback reaction.A1 and In have a much higher reactivity to cause meltback when in contact with Si than Ga does. Low. On the other hand, when the thick III-nitride semiconductor layer is made of Al In GaN mixed crystal instead of GaN, the Ga content ratio is slightly reduced.
、 GaZSiメルトバックに起因する結晶劣化、その結果生じる表面のピット状欠陥の課 題は存在している。従って、作製される厚膜の III族窒化物半導体層が Al In GaHowever, there is a problem of crystal degradation due to the GaZSi meltback and the resulting pit-like defects on the surface. Therefore, the formed thick group III nitride semiconductor layer is
Ν混晶である際にも、本発明が有効性を有することは明らかである。 It is clear that the present invention is effective even in the case of mixed crystals.
[0073] さらに、実施例 1一 4においては、作製される厚膜の III族窒化物半導体層がアンド ープ GaNの例を示した。例えば、上記の LED、 LDの作製に利用される導電性基板 、あるいは、高周波トランジスタの作製に利用される半絶縁性基板を作製する際には 、伝導型を制御するために、シリコン、マグネシウム、酸素などの不純物をドーピング する。これら不純物を高濃度ドーピングする際にも、やはり、厚膜の III族窒化物半導 体層を作製する過程で、緩衝層中のピンホールなどの介した、 Si(l l l)層に由来す る Siと Gaによる GaZSiメルトバック反応の影響が存在する。一般に、高濃度にドーピ ングされる不純物自体は、成長初期に生じる界面での GaZSiメルトバック反応自体 の頻度を有意に低下する効果 ·作用を示さない。従って、不純物を高濃度ドーピング する際にも、本発明が有効性を有することは明らかである。 Further, in Examples 14 to 14, the example in which the thick group III nitride semiconductor layer to be manufactured is Andoop GaN was described. For example, when manufacturing a conductive substrate used for manufacturing the above-described LED or LD, or a semi-insulating substrate used for manufacturing a high-frequency transistor, silicon, magnesium, Doping with impurities such as oxygen. Even when these impurities are doped at a high concentration, in the process of producing a thick group III nitride semiconductor layer, the impurities originate from the Si (lll) layer via pinholes in the buffer layer. The influence of the GaZSi meltback reaction by Si and Ga exists. In general, impurities doped at a high concentration do not have the effect of significantly reducing the frequency of the GaZSi melt-back reaction itself at the interface that occurs at the early stage of growth. Therefore, it is clear that the present invention is effective even when the impurity is highly doped.
[0074] その他、例えば、 Si不純物を高濃度ドーピングする際に、厚膜の III族窒化物半導 体層を作製する過程で、 GaZSiメルトバック反応に至らないが、緩衝層中のピンホ ールなどの介して、界面より III族窒化物半導体層中へ Siが局所的に拡散する場合も ある。その際、局所的に Si濃度が極度に高くなり、 III族窒化物半導体層内で、クラス ター化した Siが微細な析出物を形成する場合もある。この種の析出物の形成に対し ても、本発明は、その抑制を行う効果を有する。 In addition, for example, when doping a Si impurity at a high concentration, a GaZSi meltback reaction does not occur in the process of forming a thick group III nitride semiconductor layer, but the pinhole in the buffer layer In some cases, Si diffuses locally from the interface into the group III nitride semiconductor layer. At that time, the Si concentration becomes extremely high locally, and the clustered Si may form fine precipitates in the group III nitride semiconductor layer. For the formation of this kind of precipitate Even so, the present invention has an effect of suppressing the above.
[0075] 一方、上記実施例 1一 3においては、張り合わせにより作製される、 Si (111)バルタ 基板 ZSiO膜 ZSi (111)層の構造を有する SOI基板を用いる例を示した。例えば、  On the other hand, in the above-mentioned Examples 13 to 13, an example is shown in which an SOI substrate having a structure of a Si (111) Balta substrate, a ZSiO film, and a ZSi (111) layer, which is produced by laminating, is used. For example,
2  2
表面から Si (111)基板に酸素イオンを打ち込み、その後、ァニールを施して、 Si (11 1)バルタ基板 ZSiO膜 ZSi(l l l)層の構造を形成した SOI基板を用いても、同様  Oxygen ions are implanted into the Si (111) substrate from the surface and then annealed, and the Si (111) Balta substrate ZSiO film ZSi (ll)
2  2
の効果が得られる。  The effect of is obtained.
[0076] 一方、上記実施例 2においては、緩衝層として用いる、第一の III族窒化物半導体 膜、ここでは、 A1N膜の表面を部分的に被覆する第二の誘電体層として、 SiO膜を  On the other hand, in Example 2 described above, a first III nitride semiconductor film used as a buffer layer, here, an SiO film was used as a second dielectric layer partially covering the surface of the A1N film. To
2 用いる例を示した。この第二の誘電体層は、 HVPE成長条件下で安定であり、緩衝 層の表面を被覆する機能を示すこと、また、緩衝層に用いる、第一の III族窒化物半 導体膜との間でィ匕学反応を生じないことも必要である。 SiO膜以外に、この二つの  2 Examples of use are given. The second dielectric layer is stable under HVPE growth conditions, exhibits a function of covering the surface of the buffer layer, and has a function to cover the first group III nitride semiconductor film used for the buffer layer. In addition, it is necessary to prevent the dangling reaction from occurring. In addition to the SiO film, these two
2  2
要件を満足する誘電体材料、例えば、 SiN、アルミニウム酸ィ匕物 (Al O )  Dielectric materials satisfying requirements, for example, SiN, aluminum oxide (Al 2 O 3)
2 3、または、 2 3 or
SiO N、あるいは、それらを組み合わせた積層膜を用いても、同様の効果が得られ る。 The same effect can be obtained by using SiON or a laminated film combining them.
[0077] 力！]えて、周期的なストライプ状開口部内の第一の III族窒化物半導体膜表面から、 選択的に厚膜の III族窒化物半導体層の成長が開始する形態とする際には、この第 二の誘電体層として、その表面において、 III族窒化物半導体の結晶核生成が生じ難 V、材料を選択することがより好ま 、。  [0077] Power! In order to selectively start growing a thick group III nitride semiconductor layer from the surface of the first group III nitride semiconductor film in the periodic stripe-shaped opening, It is more preferable to select a material as a dielectric layer of which hardly generates crystal nuclei of a group III nitride semiconductor on its surface.
[0078] 一方、上記実施例 3、 4においては、緩衝層として用いる、第一の III族窒化物半導 体膜を周期的なストライプ状パターンにエッチング加工し、このストライプ状の第一の III族窒化物半導体膜から選択的に厚膜の III族窒化物半導体層の成長が開始する 形態を利用している。このように、ストライプ状の第一の III族窒化物半導体膜から選 択的に厚膜の III族窒化物半導体層の成長が開始する形態とする際には、表面に露 出している第一の誘電体層として、その表面において、 III族窒化物半導体の結晶核 生成が生じ難 ヽ材料を選択することがより好ま ヽ。  On the other hand, in Examples 3 and 4, the first group III nitride semiconductor film used as the buffer layer was etched into a periodic stripe pattern, and the first III nitride semiconductor film was striped. A mode in which the growth of a thick group III nitride semiconductor layer is selectively started from the group III nitride semiconductor film is used. As described above, when the growth of the thick group III nitride semiconductor layer is started selectively from the striped first group III nitride semiconductor film, the first group III nitride semiconductor film exposed on the surface is As the dielectric layer, it is more preferable to select a material that does not easily generate crystal nuclei of a group III nitride semiconductor on its surface.
産業上の利用可能性  Industrial applicability
[0079] 本発明にかかる窒化ガリウム系半導体基板の作製方法により、安価で、大面積の S i基板を下地基板として利用し、良質な窒化ガリウム系半導体自立基板を簡便、かつ 高 、生産性で作製することが可能となる。 According to the method for manufacturing a gallium nitride-based semiconductor substrate according to the present invention, a high-quality gallium nitride-based semiconductor free-standing substrate can be easily and simply used by using an inexpensive, large-area Si substrate as a base substrate. It can be manufactured with high productivity.

Claims

請求の範囲 The scope of the claims
[1] 窒化ガリウム系半導体基板を作製する方法であって、  [1] A method for producing a gallium nitride based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si(lll)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si(lll)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (ll) layer on the substrate surface;
緩衝層の堆積後、厚膜の窒化ガリウム系半導体層を堆積する工程とを 少なくとも有し、  Depositing a thick gallium nitride-based semiconductor layer after depositing the buffer layer,
前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法。  A method for manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[2] 窒化ガリウム系半導体基板を作製する方法であって、  [2] A method for producing a gallium nitride based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si(lll)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si(lll)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (ll) layer on the substrate surface;
緩衝層の堆積後、前記緩衝層の表面を部分的に被覆する第二の誘電体層を形成 する工程と、  Forming a second dielectric layer that partially covers the surface of the buffer layer after depositing the buffer layer;
前記第二の誘電体層による部分的被覆後、厚膜の窒化ガリウム系半導体層を堆積 する工程とを  Depositing a thick gallium nitride based semiconductor layer after the partial coating with the second dielectric layer.
少なくとも有し、  At least have
前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法。  A method for manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[3] 窒化ガリウム系半導体基板を作製する方法であって、  [3] A method for producing a gallium nitride based semiconductor substrate,
担体基板上に、第一の誘電体層と、該第一の誘電体層上に Si(lll)層が積層さ れてなる基板を用い、  Using a substrate in which a first dielectric layer and a Si (ll) layer are laminated on the first dielectric layer on a carrier substrate,
前記基板表面の Si(lll)層上に緩衝層を堆積する工程と、  Depositing a buffer layer on the Si (ll) layer on the substrate surface;
緩衝層の堆積後、前記第一の誘電体層上の前記 Si ( 111 )層と緩衝層との積層構 造を部分的に残し、他の領域では、前記 Si (111)層と緩衝層との積層構造を除去し After the deposition of the buffer layer, the laminated structure of the Si (111) layer and the buffer layer on the first dielectric layer is partially left, and in other regions, the stacked structure of the Si (111) layer and the buffer layer is removed. Remove the laminated structure of
、第一の誘電体層表面を露出させる工程と、 Exposing the surface of the first dielectric layer,
前記 Si(lll)層と緩衝層との積層構造の部分的除去後、厚膜の窒化ガリウム系半 導体層を堆積する工程とを After partially removing the laminated structure of the Si (ll) layer and the buffer layer, a thick gallium nitride-based Depositing a conductor layer
少なくとも有し、  At least have
前記厚膜の窒化ガリウム系半導体層を用いて、窒化ガリウム系半導体基板を作製 することを特徴とする窒化ガリウム系半導体基板の作製方法。  A method for manufacturing a gallium nitride-based semiconductor substrate, comprising manufacturing a gallium nitride-based semiconductor substrate using the thick gallium nitride-based semiconductor layer.
[4] 前記 Si (l l l)層の厚さを、： L m以下の範囲に選択することを特徴とする請求項 1 一 3のいずれか一項に記載の窒化ガリウム系半導体基板の作製方法。  [4] The method for producing a gallium nitride based semiconductor substrate according to any one of [13] to [13], wherein the thickness of the Si (ll) layer is selected within a range of Lm or less.
[5] 前記緩衝層は、少なくとも A1を含む窒化ガリウム系半導体層であることを特徴とする 請求項 1一 4のいずれか一項に記載の窒化ガリウム系半導体基板の作製方法。  5. The method for manufacturing a gallium nitride based semiconductor substrate according to claim 14, wherein the buffer layer is a gallium nitride based semiconductor layer containing at least A1.
[6] 前記第一の誘電体層の誘電体材料は、 SiO Nで示される誘電体材料の群から選 択されることを特徴とする請求項 1一 5のいずれか一項に記載の窒化ガリウム系半導 体基板の作製方法。  6. The nitride according to claim 15, wherein the dielectric material of the first dielectric layer is selected from a group of dielectric materials represented by SiON. A method for manufacturing a gallium-based semiconductor substrate.
[7] 前記第二の誘電体層の誘電体材料は、 SiO Nで示される誘電体材料の群から選 択されることを特徴とする請求項 2に記載の窒化ガリウム系半導体基板の作製方法。  7. The method according to claim 2, wherein the dielectric material of the second dielectric layer is selected from a group of dielectric materials represented by SiON. .
[8] 前記担体基板として、 Si (111)基板とは異なる熱膨張係数の面内異方性を有する 基板を用いることを特徴とする請求項 1一 7のいずれか一項に記載の窒化ガリウム系 半導体基板の作製方法。 8. The gallium nitride according to claim 17, wherein a substrate having an in-plane anisotropy of a thermal expansion coefficient different from that of a Si (111) substrate is used as the carrier substrate. A method of manufacturing a semiconductor substrate.
[9] 前記担体基板として、 Si (100)基板を用いることを特徴とする請求項 8に記載の窒 化ガリウム系半導体基板の作製方法。 9. The method for producing a gallium nitride-based semiconductor substrate according to claim 8, wherein a Si (100) substrate is used as the carrier substrate.
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