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WO2005083945A1 - Microcircuit integre redimensionnable pour couplage de systemes de bus de donnees - Google Patents

Microcircuit integre redimensionnable pour couplage de systemes de bus de donnees Download PDF

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Publication number
WO2005083945A1
WO2005083945A1 PCT/IB2005/050567 IB2005050567W WO2005083945A1 WO 2005083945 A1 WO2005083945 A1 WO 2005083945A1 IB 2005050567 W IB2005050567 W IB 2005050567W WO 2005083945 A1 WO2005083945 A1 WO 2005083945A1
Authority
WO
WIPO (PCT)
Prior art keywords
system chip
data bus
external
transceiver
coupling
Prior art date
Application number
PCT/IB2005/050567
Other languages
English (en)
Inventor
Matthias Muth
Original Assignee
Philips Intellectual Property & Standards Gmbh
Koninklijke Philips Electronics N. V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property & Standards Gmbh, Koninklijke Philips Electronics N. V. filed Critical Philips Intellectual Property & Standards Gmbh
Priority to EP05702975A priority Critical patent/EP1719298A1/fr
Priority to JP2006553740A priority patent/JP2007527577A/ja
Publication of WO2005083945A1 publication Critical patent/WO2005083945A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge

Definitions

  • the invention relates to a scalable system chip for coupling at least two data bus systems.
  • gateways are provided. Different designs of these gateways are known.
  • One option comprises the provision in a gateway of all the transceiver types that are suitable for the data bus systems provided in the vehicle. This means that, for every data bus, an assigned transceiver is provided, which, however, is in each case suitable only for a data bus type assigned to it.
  • Scalable system chip for coupling at least two data bus systems, with at least one transceiver, integrated on the system chip, which is provided to create a coupling with a data bus of a first type, and with at least one controller, integrated on the system chip, to control at least one external transceiver, which is provided for coupling with a data bus of a second type.
  • the scalable system chip in accordance with the invention is equipped with at least one transceiver, provided on the system chip and integrated on it, which is provided for a data bus type assigned to it. With this transceiver, data can be exchanged with this data bus type. Multiple transceivers may, of course, be integrated on the system chip, which are in each case then provided for a data bus type assigned to them.
  • the system chip is equipped with at least one controller, which is provided to control at least one external transceiver. This external transceiver is, in turn, provided for a particular data bus type. Multiple transceivers, which are in each case provided for a data bus type assigned to them, may be connected to the controller externally.
  • the scalable system chip in accordance with the invention offers a high degree of flexibility, since the external transceivers can be provided as required and according to the data bus types encountered.
  • the system chip is suitable for all situations and, as a result, can be used in any circumstances without having to be adapted.
  • the system chip controls all transceivers, i.e. both those provided on the chip and those provided externally. As a result, optimum system reliability is guaranteed, despite the flexibility, since the control takes place virtually within a closed system.
  • the system chip may advantageously operate together with an externally provided microcontroller, which processes at least parts of the send and/or receive protocols of the internal and external transceivers. Since these send and/or receive protocols are, where applicable, implemented physically with different voltage levels, these signals may, as provided in accordance with a further embodiment of the invention as claimed in claim 4, advantageously be carried via the system chip that undertakes the corresponding voltage compensations.
  • the scalable chip can assume basic control tasks of the internal and external transceivers, as provided in accordance with an embodiment of the invention as claimed in claim 3.
  • the system chip can thereby nevertheless control all transceivers assigned to all the different data bus systems.
  • the invention will be further described with reference to an example of an embodiment shown in the drawing, to which, however, the invention is not restricted.
  • the Figure shows, in the form of a block circuit diagram, a scalable system chip 1 in accordance with the invention.
  • the system chip 1 is equipped with a first integrated transceiver 2, which is provided to create a coupling with an external data bus, of type A, which is not shown in the drawing.
  • the system chip 1 is further equipped with a second integrated transceiver 3
  • transceiver 8 is provided for a data bus type C
  • transceiver 9 for a data bus type D
  • transceiver 10 for another data bus type, which is here labeled with n, wherein C, D and n may also be of the same type.
  • the system basic chip 1 further operates together with an externally provided microcontroller 11, which the system basic chip 1 controls in respect of power supply (P), reset (R) and Interrupt (Int).
  • a data bus D which may be, for example, an SPI data bus, as known er se.
  • the system chip 1 can be advantageously designed in such a way that it can drive a quantity of external transceivers 8, 9 or 10 that is sufficient in all cases.
  • These external transceivers 8, 9 or 10 can be adapted in terms of their design in line with the particular requirements, i.e. the data bus types with which they exchange data. This adaptation is undertaken exclusively through the selection of suitable external transceivers, whereas the system chip 1 can itself remain unchanged. It is advantageous hereby to provide the internal transceivers for those data bus types that are more or less always provided, and to provide the external transceivers for those data bus types that are only implemented in some cases.
  • the system chip 1 offers a high degree of operational reliability, since, in the event of, for example, any hardware fault on the external microcontroller 11 or defective software of the microcontroller 11, it can nevertheless undertake certain basic control tasks (emergency operation) of both the internal and, as via the controller 4, the external transceivers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un microcircuit intégré redimensionnable (1) pour le couplage d'au moins deux systèmes de bus de données, avec au moins un émetteur-récepteur (2; 3) intégré au microcircuit dont la fonction est de créer un couplage avec un bus de données d'un premier type, et avec au moins une unité de commande (4), intégrée au microcircuit, qui commande au moins un émetteur-récepteur (8; 9; 10) qui assure le couplage avec un bus de données d'un second type.
PCT/IB2005/050567 2004-02-20 2005-02-14 Microcircuit integre redimensionnable pour couplage de systemes de bus de donnees WO2005083945A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05702975A EP1719298A1 (fr) 2004-02-20 2005-02-14 Microcircuit integre redimensionnable pour couplage de systeme de bus de donnees
JP2006553740A JP2007527577A (ja) 2004-02-20 2005-02-14 データバスシステム結合用スケーラブルシステムチップ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100681.8 2004-02-20
EP04100681 2004-02-20

Publications (1)

Publication Number Publication Date
WO2005083945A1 true WO2005083945A1 (fr) 2005-09-09

Family

ID=34896096

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050567 WO2005083945A1 (fr) 2004-02-20 2005-02-14 Microcircuit integre redimensionnable pour couplage de systemes de bus de donnees

Country Status (4)

Country Link
EP (1) EP1719298A1 (fr)
JP (1) JP2007527577A (fr)
CN (1) CN1922829A (fr)
WO (1) WO2005083945A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438462B1 (en) * 1996-03-26 2002-08-20 Daimlerchrysler Ag Semiconductor circuit for an electronic unit
US20030163587A1 (en) * 2002-02-25 2003-08-28 Knight Alexander N. Vehicle communications network adapter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438462B1 (en) * 1996-03-26 2002-08-20 Daimlerchrysler Ag Semiconductor circuit for an electronic unit
US20030163587A1 (en) * 2002-02-25 2003-08-28 Knight Alexander N. Vehicle communications network adapter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LAWICEL HB: "uCAN.cpu.505: Manual Single Board Computer, version 1.00", 12 April 2003 (2003-04-12), XP002328790, Retrieved from the Internet <URL:http://web.archive.org/web/20030412060729/http://candip.com/pdf/mcan-cpu505-lawicel.pdf> [retrieved on 20050520] *

Also Published As

Publication number Publication date
CN1922829A (zh) 2007-02-28
EP1719298A1 (fr) 2006-11-08
JP2007527577A (ja) 2007-09-27

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