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WO2005071840A2 - Systemes de telecommunication - Google Patents

Systemes de telecommunication Download PDF

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Publication number
WO2005071840A2
WO2005071840A2 PCT/GB2004/004923 GB2004004923W WO2005071840A2 WO 2005071840 A2 WO2005071840 A2 WO 2005071840A2 GB 2004004923 W GB2004004923 W GB 2004004923W WO 2005071840 A2 WO2005071840 A2 WO 2005071840A2
Authority
WO
WIPO (PCT)
Prior art keywords
reference frequency
frequency signals
signal
output
operable
Prior art date
Application number
PCT/GB2004/004923
Other languages
English (en)
Other versions
WO2005071840A3 (fr
Inventor
Rob Bristow
Lars Jonsson
Thomas Mattsson
Original Assignee
Telefonaktiebolaget L M Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP04250308A external-priority patent/EP1557951B1/fr
Application filed by Telefonaktiebolaget L M Ericsson (Publ) filed Critical Telefonaktiebolaget L M Ericsson (Publ)
Priority to US10/597,292 priority Critical patent/US20080056427A1/en
Priority to JP2006550267A priority patent/JP4625030B2/ja
Publication of WO2005071840A2 publication Critical patent/WO2005071840A2/fr
Publication of WO2005071840A3 publication Critical patent/WO2005071840A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • H03L7/141—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail the phase-locked loop controlling several oscillators in turn
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Definitions

  • the present invention relates to mobile telecommunications systems, and, in particular, to systems for generating reference frequency signals in mobile telecommunications systems.
  • VCOs voltage controlled oscillators
  • the VCOs used for transmission operate on the same frequency as the required transmit channel and the VCOs used for reception operate at twice the required receive frequency to allow use of a well known digital divider circuit to provide in-phase and quadrature local oscillator (LO) signals.
  • LO local oscillator
  • the silicon area of the IC used by the 1 and 2 GHz VCOs has a significant upward impact on the cost of the ASIC. Also, there are significant problems with feedback to these VCOs since they operate at the same frequency as the transmitter signal .
  • all of the required frequencies are generated using a single VCO combined with frequency divider circuits; for example the VCO could operate in the region of 4GHz and be divided by 2 or 4 as required to provide the lower frequencies.
  • VCO could operate in the region of 4GHz and be divided by 2 or 4 as required to provide the lower frequencies.
  • this is not a straightforward technique to use in an ASIC as the required tuning range of the VCO is large.
  • a reference frequency generator circuit for a radio frequency transmit and receive apparatus, the circuit comprising: a first voltage controlled oscillator which is operable to produce a first reference frequency signal, a second voltage controlled oscillator which is operable to produce a second reference frequency signal, a switchable set of dividers, connected to receive the first and second reference frequency signals, and operable to produce a set of output reference frequency signals therefrom, a first subset of the set of output reference frequencies being derived from the first reference frequency, and a second subset of the set of output reference frequencies being derived from the second reference frequency, wherein the first and second reference frequency signals are not equal in frequency to the output reference frequency signals in the set of output reference frequency signals.
  • Figure 1 illustrates a first embodiment of the present invention
  • Figure 2 illustrates a second embodiment of the present invention
  • Figure 3 illustrates a third embodiment of the present invention
  • Figure 4 illustrates ranges of reference frequencies provided by VCOs used in embodiments of the present invention.
  • Figure 1 illustrates a first embodiment of the present invention, for providing transmitter and receiver signals suitable for use in a mobile station (MS) for use in a mobile telecommunications network.
  • the embodiment of Figure 1 comprises a phase lock loop circuit (PLL) comprising first and second voltage controlled oscillators (VCOA, VCOB) 2 and 4.
  • the VCOs 2 and 4 provide output signals to an adder 6 which supplies a signal to a switchable divider 8.
  • the VCOs 2 and 4 are used independently, and so the output of the adder 6 is equivalent to the output of the chosen operating VCO.
  • the switchable divider 8 is operable to divide the signal from the adder 6 by one or two.
  • the output of the switchable divider 8 is supplied to a further divider 10, which is operable to divide the signal by 2.
  • the output of the divider 10 is supplied to a programmable divider 12.
  • the programmable divider 12 supplies an output to a phase detector 14 for comparison with a reference frequency 20.
  • the output of the phase detector 14 is supplied to a loop filter 16, which in turn supplies a filtered control signal to each of the first and second VCOs 2 and 4.
  • the PLL operates to stabilise the outputs of the VCOs 2 and 4, in known manner.
  • the VCO is operated at 2x or 4x the desired frequency, and there is always a fixed division of 2 or 4 provided by the dividers 10 and 8. This means that the frequency provided to the input of the programmable divider is the same as if the VCO were operating at the required frequency and divider 10 and 8 were not present .
  • the programmable divider 12 operates to lock the operating VCO to twice or four times the required output frequency of Npd*Fref, where Npd is the programmable divider modulus and Fref is the reference frequency .
  • the fixed and programmable dividers provide a set of dividers which are used to tailor the output of the VCOs.
  • the modulus (size) of the divider eg. /2 or /4) can be fixed or varying. If varying appropriately, the VCOs can be frequency modulated.
  • the varying modulus can be provided by a varying signal or by a suitable combination of varying and fixed signals. For example, the modulus may vary around a fixed point .1
  • the output of the second VCO 4 is also supplied to a divider 26, which is operable to divide the output of the VCO by 4.
  • the output of the divider is supplied, via a buffer 28, to a power amplifier (not shown) of the mobile station and provides the low band transmitter signal frequency.
  • the output of the adder 6 is supplied to a divider 22 which operates to divide that summed signal by 2.
  • the divided signal is supplied, via a buffer 24, to the power amplifier of the mobile station. This provides the high band transmitter signal frequency.
  • the VCOs 2 and 4 are both tuned to output signals of around 4GHz, so that the high band transmitter signal frequency is 2GHz and the low band 1GHz .
  • the circuit is also operable to provide the local oscillator (LO) signals to the mobile station receiver (not shown) , and this is achieved by supplying the output of the switchable divider 8 to a quadrature splitter and divider 30.
  • the quadrature splitter and divider 30 is operable to produce a signal which is half the frequency of the input signal, and has inphase and quadrature signals for supply to the receiver.
  • the divider 30 has a single output connection which carries the LO signal at either around 1GHz or around 2GHz. This is possible only if the receiver's mixer has enough bandwidth to handle both these bands. If this is not the case, then respective receivers can be used for the bands, with the LO signal split and routed to those receivers as required.
  • the characteristics of the frequency modulation as measured at the input to the programmable divider and also at the output of the circuit (24, 28) are dictated by Npd in exactly the same way as if the VCO was operated at the required final frequency and the fixed dividers 10, 8, 22 and 26 were omitted.
  • the frequency modulation measured at the outputs of the VCOs will not be correct - peak deviations of the FM modulation will be twice or four times the required values.
  • the modulated signal at input of programmable divider is defined by variations in Npd produces exactly the same result as for a conventional technique with the VCO equal to the final frequency.
  • VCO A (2) is used for the reference frequencies for systems around 3600Mhz to 4000Mhz, and VCO B for the range around 3300Mhz to 3650Mhz.
  • the loop dynamics of the PLL will be affected by the fixed divider in such a way as to reduce the open loop gain by 2 or 4. This is not usually significant though because the tuning sensitivity of the 4GHz VCO is usually approximately twice or 4 times that of a 2 or 1GHz VCO respectively, so the overall loop gain with embodiments of the present invention is not changed significantly.
  • Embodiments of the present invention can therefore provide two VCOs (2 and 4) that cover the entire required tuning range.
  • the programmable divider of the phase locked loop circuit is presented with a signal at the same frequency as the required frequency (ie. nominally the centre frequency of the GSM channel concerned) so that the circuit behaves as if the VCO was operating at the required frequency instead of a multiple of 2 or 4 times.
  • FIG. 2 illustrates an alternative circuit layout, in which switchable divider 8 is provided by a fixed divider ( ⁇ 2) 7 and gates 9 and 21.
  • the gates operate to select an input signal to be transferred to the rest of the circuit.
  • the signal routes from the VCOs 2 and 4 are determined by switching the gates 6, 9, 21, such that the correct VCO is used for the transmit/receive frequencies in use.
  • Figure 2 layout gives advantages in terms of circuit layout and size.
  • Figure 3 shows a further enhancement, where the PLL actually operates at the VCO frequency, ie. 4GHz. In the case of a fractional-N PLL this allows the resolution of the divided down signals to be higher by a factor 2 or 4.
  • the tuning range of the VCOs is relatively small and easy to implement, and the small size of 4GHz circuits allows significant cost saving relative to the 1GHz VCOs.
  • the frequency of the VCO is different from the final output frequency, which gives benefits in reducing the coupling effects between the output signal and the VCOs. This has the benefit of maintaining control compatibility between different architectures.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transmitters (AREA)

Abstract

Selon l'invention, un circuit de production de fréquence de référence destiné à un dispositif d'émission et réception à fréquence radio, comprend: un premier oscillateur commandé en tension qui peut fonctionner pour produire un premier signal de fréquence de référence,; un second oscillateur commandé en tension qui peut fonctionner pour produire un second signal de fréquence de référence; un ensemble commutable de diviseurs connectés pour recevoir le premier et le second signal de fréquence de référence et qui peuvent fonctionner pour produire une ensemble de signaux de fréquence de référence de sortie, un premier sous-ensemble de l'ensemble de fréquences de référence de sortie étant dérivé de la première fréquence de référence, et un second sous-ensemble de l'ensemble de fréquences de référence de sortie étant dérivé de la seconde fréquence de référence, le premier et le second signal de fréquence de référence n'étant pas égaux en fréquence aux signaux de fréquence de référence de sortie de l'ensemble de signaux de fréquence de référence de sortie.
PCT/GB2004/004923 2004-01-21 2004-11-23 Systemes de telecommunication WO2005071840A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/597,292 US20080056427A1 (en) 2004-01-21 2004-11-23 Telecommunications Systems
JP2006550267A JP4625030B2 (ja) 2004-01-21 2004-11-23 通信システム

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP04250308A EP1557951B1 (fr) 2004-01-21 2004-01-21 Générateur de fréquence avec oscillateurs multiples commandé en tension
EP04250308.6 2004-01-21
US55309604P 2004-03-15 2004-03-15
US60/553,096 2004-03-15

Publications (2)

Publication Number Publication Date
WO2005071840A2 true WO2005071840A2 (fr) 2005-08-04
WO2005071840A3 WO2005071840A3 (fr) 2008-01-10

Family

ID=34809761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2004/004923 WO2005071840A2 (fr) 2004-01-21 2004-11-23 Systemes de telecommunication

Country Status (3)

Country Link
JP (1) JP4625030B2 (fr)
KR (1) KR20060128933A (fr)
WO (1) WO2005071840A2 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788237A4 (fr) * 1995-08-03 1998-11-25 Anritsu Corp Diviseur rationnel de frequences et synthetiseur de frequences employant ce diviseur de frequences
JPH10242854A (ja) * 1997-02-27 1998-09-11 Oki Electric Ind Co Ltd 周波数シンセサイザ回路
US6047029A (en) * 1997-09-16 2000-04-04 Telefonaktiebolaget Lm Ericsson Post-filtered delta sigma for controlling a phase locked loop modulator
JP2001332971A (ja) * 2000-05-19 2001-11-30 Matsushita Electric Ind Co Ltd Ｐｌｌ周波数シンセサイザ
US20020163391A1 (en) * 2001-03-01 2002-11-07 Peterzell Paul E. Local oscillator leakage control in direct conversion processes
DE10112575A1 (de) * 2001-03-15 2002-10-02 Siemens Ag Verfahren und Vorrichtung zur Erzeugung von Mobilfunksignalen
JP2003091328A (ja) * 2001-09-19 2003-03-28 Alps Electric Co Ltd コンピュータ

Also Published As

Publication number Publication date
KR20060128933A (ko) 2006-12-14
JP2007538418A (ja) 2007-12-27
JP4625030B2 (ja) 2011-02-02
WO2005071840A3 (fr) 2008-01-10

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