+

WO2005066792A3 - Memoire non volatile et procede avec alignement de plans de memoire - Google Patents

Memoire non volatile et procede avec alignement de plans de memoire Download PDF

Info

Publication number
WO2005066792A3
WO2005066792A3 PCT/US2004/043377 US2004043377W WO2005066792A3 WO 2005066792 A3 WO2005066792 A3 WO 2005066792A3 US 2004043377 W US2004043377 W US 2004043377W WO 2005066792 A3 WO2005066792 A3 WO 2005066792A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
logical
logical unit
versions
plane
Prior art date
Application number
PCT/US2004/043377
Other languages
English (en)
Other versions
WO2005066792A2 (fr
Inventor
Sergey Anatolievich Gorobets
Peter John Smith
Alan David Bennett
Original Assignee
Sandisk Corp
Sergey Anatolievich Gorobets
Peter John Smith
Alan David Bennett
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/750,155 external-priority patent/US7139864B2/en
Application filed by Sandisk Corp, Sergey Anatolievich Gorobets, Peter John Smith, Alan David Bennett filed Critical Sandisk Corp
Priority to JP2006547386A priority Critical patent/JP4933269B2/ja
Priority to EP04815452A priority patent/EP1704483A2/fr
Publication of WO2005066792A2 publication Critical patent/WO2005066792A2/fr
Publication of WO2005066792A3 publication Critical patent/WO2005066792A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne une mémoire non volatile constituée d'un ensemble de plans de mémoire, chaque plan comprenant son propre ensemble de circuits de lecture/écriture de sorte que les plans de mémoire puissent fonctionner en parallèle. Par ailleurs, cette mémoire est organisée en blocs effaçables, chaque bloc permettant de stocker un groupe logique d'unités logiques de données. Dans la mise à jour d'une unité logique, toutes les versions d'une unité logique sont maintenues dans le même plan que l'original. De préférence, toutes les versions d'une unité logique sont alignées dans un plan de sorte qu'elles soient toutes desservies par le même ensemble de circuits de détection. Dans une opération de collecte d'informations parasites subséquente, la dernière version de l'unité logique ne doit pas être nécessairement récupérée à partir d'un plan différent ou d'un ensemble différent de circuits de détection, ce qui permet d'éviter une réduction de performance. Dans un mode de réalisation, tous les espaces subsistant après l'alignement sont remplis par copie des dernières versions d'unités logiques en ordre séquentiel.
PCT/US2004/043377 2003-12-30 2004-12-21 Memoire non volatile et procede avec alignement de plans de memoire WO2005066792A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006547386A JP4933269B2 (ja) 2003-12-30 2004-12-21 不揮発性メモリおよびメモリプレーン配列を伴う方法
EP04815452A EP1704483A2 (fr) 2003-12-30 2004-12-21 Memoire non volatile et procede avec alignement de plans de memoire

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/750,155 US7139864B2 (en) 2003-12-30 2003-12-30 Non-volatile memory and method with block management system
US10/750,155 2003-12-30
US10/917,888 US20050141313A1 (en) 2003-12-30 2004-08-13 Non-volatile memory and method with memory planes alignment
US10/917,888 2004-08-13

Publications (2)

Publication Number Publication Date
WO2005066792A2 WO2005066792A2 (fr) 2005-07-21
WO2005066792A3 true WO2005066792A3 (fr) 2006-02-09

Family

ID=34753195

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/043377 WO2005066792A2 (fr) 2003-12-30 2004-12-21 Memoire non volatile et procede avec alignement de plans de memoire

Country Status (4)

Country Link
EP (1) EP1704483A2 (fr)
KR (1) KR20060134011A (fr)
TW (1) TWI272487B (fr)
WO (1) WO2005066792A2 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139864B2 (en) 2003-12-30 2006-11-21 Sandisk Corporation Non-volatile memory and method with block management system
US9104315B2 (en) 2005-02-04 2015-08-11 Sandisk Technologies Inc. Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage
JP4751163B2 (ja) 2005-09-29 2011-08-17 株式会社東芝 メモリシステム
US7870231B2 (en) * 2006-07-21 2011-01-11 Qualcomm Incorporated Efficiently assigning precedence values to new and existing QoS filters
KR100825802B1 (ko) * 2007-02-13 2008-04-29 삼성전자주식회사 기입 데이터의 논리적 페이지보다 이전 논리적 페이지들을가지는 데이터들을 데이터 블록으로부터 복사하는 불휘발성메모리 장치의 데이터 기입 방법
US8898412B2 (en) * 2007-03-21 2014-11-25 Hewlett-Packard Development Company, L.P. Methods and systems to selectively scrub a system memory
US8634470B2 (en) 2007-07-24 2014-01-21 Samsung Electronics Co., Ltd. Multimedia decoding method and multimedia decoding apparatus based on multi-core processor
KR101297563B1 (ko) 2007-11-15 2013-08-19 삼성전자주식회사 스토리지 관리 방법 및 관리 시스템
KR100982440B1 (ko) * 2008-06-12 2010-09-15 (주)명정보기술 단일 플래시 메모리의 데이터 관리시스템
US8219781B2 (en) * 2008-11-06 2012-07-10 Silicon Motion Inc. Method for managing a memory apparatus, and associated memory apparatus thereof
JP4956593B2 (ja) 2009-09-08 2012-06-20 株式会社東芝 メモリシステム
US8626989B2 (en) * 2011-02-02 2014-01-07 Micron Technology, Inc. Control arrangements and methods for accessing block oriented nonvolatile memory
KR101419004B1 (ko) * 2012-05-03 2014-07-11 주식회사 디에이아이오 비휘발성 메모리 시스템
WO2013171792A1 (fr) * 2012-05-16 2013-11-21 Hitachi, Ltd. Appareil de commande de mémorisation et procédé de commande de mémorisation
KR101987740B1 (ko) 2012-07-09 2019-06-11 에스케이하이닉스 주식회사 불휘발성 메모리 장치의 채널 특성을 추정하기 위한 방법
US9817593B1 (en) 2016-07-11 2017-11-14 Sandisk Technologies Llc Block management in non-volatile memory system with non-blocking control sync system
US10423353B2 (en) 2016-11-11 2019-09-24 Micron Technology, Inc. Apparatuses and methods for memory alignment
TWI747349B (zh) * 2020-06-30 2021-11-21 大陸商合肥沛睿微電子股份有限公司 儲存裝置之低級格式化方法
US20230418743A1 (en) * 2021-12-28 2023-12-28 SK Hynix Inc. Data storage device and method of operating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860124A (en) * 1996-09-30 1999-01-12 Intel Corporation Method for performing a continuous over-write of a file in nonvolatile memory
US20020099904A1 (en) * 2001-01-19 2002-07-25 Conley Kevin M. Partial block data programming and reading operations in a non-volatile memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860124A (en) * 1996-09-30 1999-01-12 Intel Corporation Method for performing a continuous over-write of a file in nonvolatile memory
US20020099904A1 (en) * 2001-01-19 2002-07-25 Conley Kevin M. Partial block data programming and reading operations in a non-volatile memory

Also Published As

Publication number Publication date
EP1704483A2 (fr) 2006-09-27
TW200601042A (en) 2006-01-01
KR20060134011A (ko) 2006-12-27
WO2005066792A2 (fr) 2005-07-21
TWI272487B (en) 2007-02-01

Similar Documents

Publication Publication Date Title
WO2005066792A3 (fr) Memoire non volatile et procede avec alignement de plans de memoire
US8954654B2 (en) Virtual memory device (VMD) application/driver with dual-level interception for data-type splitting, meta-page grouping, and diversion of temp files to ramdisks for enhanced flash endurance
US9548108B2 (en) Virtual memory device (VMD) application/driver for enhanced flash endurance
US9720616B2 (en) Data-retention controller/driver for stand-alone or hosted card reader, solid-state-drive (SSD), or super-enhanced-endurance SSD (SEED)
CN101689140B (zh) 存储器系统
TWI775122B (zh) 用來存取至少一非揮發性記憶體元件的處理單元
CN103488578B (zh) 虚拟存储设备（vmd）应用/驱动器
CN101233498B (zh) 快闪存储器中利用直接数据文件存储的数据操作
US7516296B2 (en) Flash memory storage device and read/write method
CN102541757B (zh) 写缓存方法、缓存同步方法和装置
CN107526540B (zh) 数据储存装置及其数据维护方法
US20080282023A1 (en) Restoring storage devices based on flash memories and related circuit, system, and method
JP2008527586A (ja) オンチップデータのグループ化および整列
CN101124555A (zh) 具有多流更新的非易失性存储器和方法
CN105824759B (zh) 数据储存装置以及快闪存储器控制方法
WO2004061673A3 (fr) Procede et appareil de gestion de memoire orientee bloc pour controleurs de cartes a puce
WO2005103878A3 (fr) Procede et systeme de compression de fichiers a stocker et operation sur des fichiers comprimes
WO2007076378A3 (fr) Acces en mode double pour dispositifs de stockage non-volatiles
US9141530B2 (en) Data writing method, memory controller and memory storage device
TW201437807A (zh) 映射資訊記錄方法、記憶體控制器與記憶體儲存裝置
CN107291378A (zh) 数据储存装置及其数据维护方法
US11204697B2 (en) Wear leveling in solid state devices
CN102033811B (zh) 用于管理闪存多个区块的方法和相关记忆装置及其控制器
TW200732918A (en) Method and system for accessing non-volatile storage devices
WO2009140157A3 (fr) Systèmes et procédés de récupération d'informations à partir de systèmes de mémoire à réseau de portes non-et

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020067013315

Country of ref document: KR

Ref document number: 2006547386

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 2004815452

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 200480042138.2

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2004815452

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020067013315

Country of ref document: KR

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载