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WO2005057628A3 - A method and apparatus for reducing leakage in integrated circuits - Google Patents

A method and apparatus for reducing leakage in integrated circuits Download PDF

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Publication number
WO2005057628A3
WO2005057628A3 PCT/US2004/040989 US2004040989W WO2005057628A3 WO 2005057628 A3 WO2005057628 A3 WO 2005057628A3 US 2004040989 W US2004040989 W US 2004040989W WO 2005057628 A3 WO2005057628 A3 WO 2005057628A3
Authority
WO
WIPO (PCT)
Prior art keywords
leakage
present
reduction
control
accordance
Prior art date
Application number
PCT/US2004/040989
Other languages
French (fr)
Other versions
WO2005057628A2 (en
Inventor
Nagarajan Ranganathan
Narender Hanchate
Original Assignee
Univ South Florida
Nagarajan Ranganathan
Narender Hanchate
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ South Florida, Nagarajan Ranganathan, Narender Hanchate filed Critical Univ South Florida
Publication of WO2005057628A2 publication Critical patent/WO2005057628A2/en
Publication of WO2005057628A3 publication Critical patent/WO2005057628A3/en
Priority to US11/422,973 priority Critical patent/US7256608B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.
PCT/US2004/040989 2003-12-08 2004-12-08 A method and apparatus for reducing leakage in integrated circuits WO2005057628A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/422,973 US7256608B2 (en) 2003-12-08 2006-06-08 Method and apparatus for reducing leakage in integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48175103P 2003-12-08 2003-12-08
US60/481,751 2003-12-08

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/422,973 Continuation US7256608B2 (en) 2003-12-08 2006-06-08 Method and apparatus for reducing leakage in integrated circuits

Publications (2)

Publication Number Publication Date
WO2005057628A2 WO2005057628A2 (en) 2005-06-23
WO2005057628A3 true WO2005057628A3 (en) 2006-01-19

Family

ID=34676551

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/040989 WO2005057628A2 (en) 2003-12-08 2004-12-08 A method and apparatus for reducing leakage in integrated circuits

Country Status (2)

Country Link
US (1) US7256608B2 (en)
WO (1) WO2005057628A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7793239B2 (en) * 2006-04-24 2010-09-07 International Business Machines Corporation Method and system of modeling leakage
ATE534994T1 (en) 2006-04-28 2011-12-15 Mosaid Technologies Inc SRAM RESIDUAL CURRENT REDUCTION CIRCUIT
US8255854B2 (en) * 2006-09-22 2012-08-28 Actel Corporation Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit
JP5116392B2 (en) * 2007-07-31 2013-01-09 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit
US20090179664A1 (en) * 2008-01-10 2009-07-16 Janet Wang Method and Apparatus for Controlling Leakage in a Circuit
US7816946B1 (en) * 2008-01-31 2010-10-19 Actel Corporation Inverting flip-flop for use in field programmable gate arrays
JP4492736B2 (en) * 2008-06-12 2010-06-30 ソニー株式会社 Semiconductor integrated circuit
US8445947B2 (en) * 2008-07-04 2013-05-21 Stmicroelectronics (Rousset) Sas Electronic circuit having a diode-connected MOS transistor with an improved efficiency
US8464198B1 (en) * 2008-07-30 2013-06-11 Lsi Corporation Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit
JP5599983B2 (en) * 2009-03-30 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device
WO2011137339A2 (en) 2010-04-30 2011-11-03 Cornell University Systems and methods for zero-delay wakeup for power gated asynchronous pipelines
US8570077B2 (en) * 2010-12-17 2013-10-29 Qualcomm Incorporated Methods and implementation of low-power power-on control circuits
US9529953B2 (en) * 2012-08-02 2016-12-27 The United States Of America, As Represented By The Secretary Of The Navy Subthreshold standard cell library
KR20150112148A (en) 2014-03-27 2015-10-07 삼성전자주식회사 Power gating circuit and integrated circuit
CN111684723B (en) * 2018-02-09 2024-05-10 新加坡国立大学 Multi-mode standard cell logic and self-starting for battery-less or pure energy harvesting systems
US10924112B2 (en) * 2019-04-11 2021-02-16 Ememory Technology Inc. Bandgap reference circuit
US11063590B1 (en) * 2020-11-13 2021-07-13 Nxp Usa, Inc. High voltage integrated circuit devices with hot carrier injection damage protection
CN113098467B (en) * 2021-03-01 2023-05-26 电子科技大学 Multi-threshold CMOS circuit for reducing leakage power

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107829A (en) * 1998-03-31 2000-08-22 Lucent Technologies, Inc. Low leakage tristatable MOS output driver
US6169419B1 (en) * 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098689B1 (en) * 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107829A (en) * 1998-03-31 2000-08-22 Lucent Technologies, Inc. Low leakage tristatable MOS output driver
US6169419B1 (en) * 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same

Also Published As

Publication number Publication date
US7256608B2 (en) 2007-08-14
US20070007996A1 (en) 2007-01-11
WO2005057628A2 (en) 2005-06-23

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