WO2003103035A1 - Method for the production of a double-gate transistor - Google Patents

Abstract

The invention relates to a method for producing a double-gate transistor, comprising the following steps: a first gate area is formed on a silicon-on-isolator substrate of a first wafer; a layer having a planar surface is formed on top of the silicon-on-isolator substrate and the first gate area; a second wafer is bonded to the planar surface of the first wafer; and a second gate area which is located across from the first gate area is formed within the silicon-on-isolator substrate.

Description

description

Method of manufacturing a double gate transistor

The invention relates to a method for producing a double-gate transistor and in particular to a method for producing a self-aligned double-gate transistor.

As the scaling of conventional planar metal oxide semiconductor field effect transistors (MOSFET) in silicon technology continues, the performance of the individual component is significantly deteriorated, among other things, by the short channel effects. These undesired short-channel effects include, for example: a decreasing increase in drain current with increasing gate voltage, a dependency of the threshold voltage on the operating point and a penetration of source and drain regions (punch-through). With gate lengths in the range from 20 nm to 30 nm, it is expected that further scaling of the bulk transistor does not represent any further progress overall. In this context, a bulk transistor is a transistor in which the transistor is constructed by means of doping in the low-doped region of the complementary doping in each case. For example, For the implementation of an NMOS transistor, a p-substrate is used, into which the NMOS transistor is implemented directly.

One possibility for a transistor with a channel length of 20 nm to 30 nm is the use of substrates which have a layer which is completely depleted of charge carriers (FD substrates).

A promising alternative to circumvent the limits, which are caused by the short channel effects that occur in a The double-gate transistor represents further scaling. In the case of a sufficiently thin active region, short-channel effects can be drastically reduced by the control action of two gates or a comprehensive gate (so-called “surrounded gate”). It is therefore assumed that double Gate transistors are essential components for terrabit integration [1], however, no simple manufacturing processes have yet been established for the production of double gate transistors.

Various concepts for the manufacture of double-gate transistors are discussed and tested. These concepts are, for example, vertical transistors, bridge transistors or planar structures with a replacement gate. However, all these concepts have in common that complex processes that have not yet been tried and tested in production technology have to be used. In addition, the manufacturing process as a whole is quite complex. In the case of a vertical transistor, there is also a non-planar surface of the individual regions (e.g. the gate), which leads to a deterioration in the current flow through the individual regions.

A difficulty in the manufacture of a planar double-gate transistor is to ensure exact adjustment of the two respective gates in a double-gate transistor, in other words, that the two gates of the transistor are arranged in a fixed spatial relationship to one another. The two gates of the transistor are arranged on both sides of a channel region of the transistor, which is arranged between the source and drain connection. In the case of a planar double-gate transistor, this means that the two gates of the transistor are arranged one above the other at the same location on the substrate are, the channel region being arranged between the two gates.

For example, to produce a planar double-gate transistor, all of the required layers of the double-gate can first be formed and then all layers can be etched at once to obtain the double-gate transistor [2]. However, this method has the disadvantage that different etching agents may have to be used to etch the different layers of the double gate of a transistor, since the individual layers consist of different materials. Using different etchants causes higher costs in the production of the planar double gate transistor. Selective etching also results in a high topology, i.e. one

Layer sequence of different layers, problems because an already etched layer is subject to further etching in a subsequent etching step by means of an etchant which also etches the already etched layer. This can lead to incorrect structuring of the layer sequence.

DE 692 26 687 T2 discloses a method for producing a double-gate transistor. In this method, a gate is applied to a first substrate, a second substrate is bonded, the first substrate is polished on the exposed surface, and a second gate is then formed on this polished surface.

US 5 899 710 discloses a method of manufacturing a transistor with at least three gates and DE 100 52 131 AI discloses a method of manufacturing a field effect transistor using a self-adjusting technique. The invention is based on the problem of creating a simple production method for a planar double-gate transistor, in which known and simple method steps of silicon technology can be used.

The problem is solved by a method for producing a double gate transistor with the features according to the independent claim.

In a method according to the invention, a first gate region of a double-gate transistor is formed on a silicon-on-insulator (SOI) substrate of a first wafer. The wafer preferably has a carrier layer made of silicon. The SOI substrate, which preferably has an insulator layer made of silicon oxide and a silicon layer formed thereon, is arranged on this carrier layer. An additional step of the method is the formation of a layer with a flat surface over the SOI substrate and the formed first gate area. To this tarpaulin

A second wafer, preferably a silicon wafer, is then bonded to the surface. After the second wafer has been bonded, the second gate region is formed in the SOI substrate of the first wafer. This is opposite the first gate area and, together with the first gate area, forms the double gate of the double gate transistor.

With the method according to the invention, a planar double-gate transistor is produced in a simple and inexpensive manner using known method steps in silicon technology.

Preferred developments of the invention result from the dependent claims. The method according to the invention for producing a double-gate transistor preferably has the following sub-steps. An active region is defined on the silicon layer of the SOI substrate by means of photolithography and etching the layer of silicon of the SOI substrate. In an additional sub-step, a first gate insulating layer is formed on the silicon of the SOI substrate. Silicon oxide is preferably used as the material of the first gate-insulating layer, which is preferably formed by means of thermal oxidation of a part of the layer of silicon of the SOI substrate. A first layer of electrically conductive material is subsequently formed on the first gate insulating layer. Doped polysilicon, which is deposited on the first gate insulating layer, is preferably used as the material of the first electrically conductive layer. A first layer made of an electrically non-conductive material, preferably silicon nitride, is formed on the first layer made of electrically conductive material. This first layer of electrically non-conductive material is part of an insulation and encapsulation of the first gate region. An additional sub-step of the method is a photolithographic definition of the gate region with subsequent structuring of the first layer made of an electrically conductive material and the first layer made of an electrically non-conductive material. This structuring is preferably carried out by means of anisotropic etching. Subsequently, first side wall layers, clearly spacers, are formed on the remaining layer made of electrically conductive material and the remaining layer made of electrically non-conductive material. The first sidewall layers are preferably also formed from silicon nitride and are a second part of the insulation and encapsulation of the first Gate region. The first side wall layers are preferably formed by conformal deposition of an electrically non-conductive layer and subsequent anisotropic recessing of this electrically non-conductive layer. With the partial steps described so far, the formation of the first gate area and the encapsulation, which encapsulation has the first layer of electrically non-conductive material and the first side wall layers, of the first gate area is essentially completed.

The following sub-steps essentially serve to prepare the first wafer for the subsequent wafer bonding. In a partial step of the preparation, the layer of silicon of the SOI substrate and the insulator layer of the SOI substrate are structured. Structuring the

Silicon layer, which is preferably a layer completely depleted of charge carriers (FD layer), of the SOI substrate and the insulator layer of the SOI substrate is preferably carried out by means of anisotropic etching. The encapsulation of the first gate is used as a mask for this anisotropic etching. A surface area of the silicon layer of the SOI substrate is exposed by means of this anisotropic etching. The exposed surface area of the silicon layer is subsequently oxidized in an additional sub-step. In a next sub-step, an auxiliary layer is applied, which is preferably made of undoped polysilicon and which is subsequently planarized. The planarization is preferably carried out by means of chemical mechanical polishing (CMP). A second layer of an electrically non-conductive material is applied to this flat surface. Silicon oxide is preferably used as the material of the second layer made of an electrically non-conductive material. With the now described The preparation of the first wafer for wafer bonding is essentially complete.

An additional sub-step of the method for producing a double-gate transistor is the bonding of a second wafer to the second layer made of an electrically non-conductive material. The second wafer is preferably made of silicon. The carrier layer of the first wafer is subsequently removed. As a result, a surface of the insulator layer of the SOI substrate is exposed for further processing, which exposed surface was coupled to the carrier layer before the carrier layer of the first wafer was removed. With the partial steps described, the wafer bonding of the second wafer to the first wafer is essentially completed.

Subsequent steps also follow, which essentially relate to the formation of a second gate of the double-gate transistor. A sub-step for forming the second gate is structuring the exposed surface of the

Insulator layer of the SOI substrate. This structuring is preferably carried out by means of etching, particularly preferably by means of wet chemical etching. This structuring exposes the silicon layer of the SOI substrate. A subsequent sub-step of the method is to define the active area by structuring the exposed silicon layer of the SOI substrate. The structuring of the exposed silicon layer of the SOI substrate is preferably carried out by means of photolithography and subsequent etching of the exposed silicon layer of the SOI substrate. A next sub-step is the formation of a thin layer of electrically non-conductive material, as which material silicon oxide is preferably used. Below are second Sidewall layers of an electrically non-conductive material are formed in the active area on the thin layer of electrically non-conductive material. The second side wall layers are preferably formed from an electrically non-conductive material by means of conformal deposition and subsequent anisotropic etching back of a layer of silicon nitride. A next sub-step of the method is the partial removal of the thin layer from an electrically non-conductive material. Below is a second gate insulating

Layer formed on the exposed silicon layer of the SOI substrate. The formation of the second gate insulating layer is preferably carried out by means of thermal oxidation of parts of the exposed silicon layer of the SOI substrate. With the partial steps described, the exposure of the area for the second gate is essentially completed.

Subsequent steps also follow, which essentially relate to separating and encapsulating the second gate. A second layer of electrically conductive material is formed in the active region. The second layer of electrically conductive material is preferably formed by depositing a layer of doped polysilicon and forms the second gate of the double gate transistor. Planarization is then carried out. The planarization is preferably carried out by means of chemical mechanical polishing. An additional sub-step is etching back the second layer from an electrically conductive material. Subsequently, a second passivation layer is formed from an electrically non-conductive material over the active area. The second passivation layer serves to encapsulate the second gate of the double-gate transistor. The second passivation layer is preferably formed by depositing silicon nitride. Planarization is then carried out. Chemical mechanical polishing is preferably used for this planarization. The separation and encapsulation of the second gate is essentially completed with the partial steps described.

In a partial step, sections of the thin layer made of an electrically non-conductive material are removed. The auxiliary layer is removed in a further sub-step.

The oxidized exposed surface area of the silicon layer of the SOI substrate is subsequently removed. Parts of the silicon layer of the SOI substrate, which silicon layer forms a channel region of the double-gate transistor, are thereby exposed.

According to one embodiment of the method according to the invention for producing a planar double-gate transistor, source / drain connections are produced by forming a third layer made of electrically conductive material. Doped polysilicon is preferably used as the material of the third layer made of electrically conductive material. Subareas of the third layer made of electrically conductive material represent the source / drain connections of the double gate transistor according to the invention. Subsequently, in a further partial step, a surface of the double gate transistor, which was produced by means of a method according to the invention, is planarized. The planarization is preferably carried out by means of chemical mechanical polishing.

According to another embodiment of the method according to the invention for producing a double-gate transistor, the source / drain connections are produced by third sidewall layers made of electrical on the first gate and the second gate conductive material are formed. The third side wall layers are preferably formed from an electrically conductive material by means of deposition of polysilicon. A metal is then sputtered on. The metal is preferably titanium. A third passivation layer is then formed. The third passivation layer is preferably formed by depositing silicon oxide. Then, in a further sub-step, a surface of the double gate transistor, which was produced by means of a method according to the invention, is planarized. The planarization is preferably carried out by means of chemical mechanical polishing. According to the preferred embodiment, in which the third side wall layers are formed from polysilicon, silicidation is carried out after the metal has been sputtered on.

The first and / or second gate insulating layer can be formed as a charge storage layer (charge trapping layer).

The first and / or the second gate insulating layer are particularly preferably formed as ONO layers.

The first gate area and the second gate area are preferably electrically decoupled from one another, so that they can be controlled separately from one another.

Standard processes of back-end technology are used for subsequent contacting of the double-gate transistor, which was produced by means of a method according to the invention.

An additional subject of the application relates to a double gate memory transistor with two Charge storage layers (charge trapping layers), a method for producing a double-gate storage transistor with two charge-storage layers and the arrangement of such double-gate storage transistors in an array.

According to one embodiment of the invention, memory transistors are created which have a so-called floating gate for storing information. One bit per memory transistor can be stored by means of these memory transistors.

According to another embodiment of the invention, memory transistors are created which have an ONO layer as gate-insulating layer, ie a layer sequence of a first silicon oxide layer Si0 ₂ , a silicon nitride layer Si ₃ N ₄ and a second silicon oxide layer Si0 ₂ . This ONO layer is used to store charge carriers and forms a charge storage layer (charge trapping layer).

When a so-called ONO layer is used as the charge storage layer, it is possible to store two bits in a memory transistor, the two SiO ₂ regions being able to be used separately for storing one bit each.

A problem in the course of constant further development in the area of memory transistors is the memory power per required area of the memory transistor, i.e. increasing the storage density and simplifying the current manufacturing processes.

A method for producing a memory transistor has the following steps. A first gate area on one Silicon-on-insulator substrate of a first wafer is formed, with a first gate-insulating layer being formed as a charge storage layer. Furthermore, a layer with a flat surface is formed over the silicon-on-insulator substrate and the first gate region and a second wafer is bonded to the flat surface of the first wafer. Furthermore, a second gate region opposite the first gate region is formed in the silicon-on-insulator substrate, a second gate-insulating layer being formed as a charge storage layer and the first and second gate regions being decoupled from one another.

A double gate memory transistor has two gates lying on opposite sides of a channel region, each gate insulating layer being designed in such a way that it can be used as a charge storage layer, the two gates of the double gate memory transistor being different from one another are decoupled that they can be controlled separately.

An arrangement of double-gate memory transistors has a memory cell array with double-gate memory transistors according to the invention, which are arranged in an array. The first gates of the double gate memory transistors of the array are electrically coupled to one another row by row on a first main side of the array, first word lines being formed, while the second gates of the double gate memory transistors on the second main side of the array are row by row are coupled to one another, second word lines being formed.

With the method according to the additional subject of the application, the Silicon technology produced a planar double-gate memory transistor in a simple and inexpensive manner. By means of this double-gate storage transistor, it is possible to achieve a storage density which is doubled compared to the prior art, since the two gates can be controlled separately from one another and thus the charge storage layers can be used separately as storage devices. Here, the charge storage layer is understood to be a so-called charge trapping layer, as is used, for example, in floating gate transistors for storing charge.

The method according to the additional subject matter of the application for producing a double-gate memory transistor, the double-gate memory transistor and the arrangement of double-gate memory transistors is described in more detail below. Refinements of the method for producing the double-gate memory transistor also apply to the double-gate memory transistor and the arrangement of double-gate memory transistors.

Forming the first gate region on the silicon-on-insulator substrate can have the substep of forming the first gate-insulating layer on the silicon-on-insulator substrate. Furthermore, it can comprise the formation and structuring of a first layer made of an electrically conductive material on the first gate-insulating layer and the partial encapsulation of the first gate region with an electrically non-conductive material.

The method preferably has the partial encapsulation of the first gate region, the formation of a first passivation layer and the formation of first side wall layers from an electrically non-conductive material. Silicon nitride is particularly preferably used as the electrically non-conductive material of the partial encapsulation of the first gate region.

The first gate insulating layer is preferably produced from silicon oxide.

The first layer is preferably produced from an electrically conductive material made of doped polysilicon.

The method for forming a layer with a flat surface preferably has the following sub-steps. Structuring the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate, whereby an exposed surface area of the silicon layer of the silicon-on-insulator substrate is obtained, oxidizing the exposed surface area, forming an auxiliary layer with a flat surface, and forming a first layer of electrically non-conductive material at least on the flat surface of the auxiliary layer.

The partial encapsulation of the first gate region is preferably used as a mask for structuring the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate.

The bonding of the second wafer can comprise the steps of bonding the second silicon wafer on the first layer made of a non-conductive material and removing a carrier layer of the first wafer. According to the method, the formation of the second gate region can have the following steps, structuring the insulator of the silicon-on-insulator substrate and exposing the silicon layer of the silicon-on-insulator substrate, structuring the silicon of the silicon-on-insulator substrate as an active region, forming a thin non-conductive layer, forming second side wall layers from a non-conductive material and forming the second gate insulating layer as a charge-adhering layer.

The second sidewall layers can be made from silicon nitride.

The method for forming the second gate preferably further comprises the following sub-steps, forming a second layer from an electrically conductive material in the active region, forming a second passivation layer over the active region and then planarizing.

This preferably also has the following sub-steps, removing a part of the thin non-conductive layer, removing the auxiliary layer, removing the oxidized exposed surface area of the silicon layer of the silicon-on-insulator substrate, forming two source / drain areas by forming a third layer an electrically conductive material and subsequent planarizing.

The third layer can be made of an electrically conductive material made of doped polysilicon.

The method may further include the steps of removing a portion of the thin non-conductive layer, Removing the auxiliary layer, removing the oxidized, exposed surface area of the silicon layer of the silicon-on-insulator substrate, forming two source / drain regions by forming third side wall layers from an electrically conductive material on the first gate and on the second gate, sputtering a metal onto the third sidewall layers made of a conductive material, forming a third passivation layer and then planarizing.

Polysilicon, which is silicided after sputtering on the metal, is preferably used as the conductive material of the third side wall regions.

The first and / or the second gate insulating layer are particularly preferably formed as ONO layers.

As a result, the storage density of the double-gate storage transistor can be increased compared to a storage transistor with a floating gate.

The first gate area and the second gate area are preferably electrically decoupled from one another.

As a result, the two charge storage layers can be controlled independently of one another by means of the gate belonging to the respective charge storage layer. A separation of gate leads (word lines) at different levels of the double gate memory transistor is possible with wafer bonding technology without difficulty. This results in an additional increase in storage density. In combination with the charge storage layers designed as ONO layers, a double gate Memory transistor four bits of information can be stored.

With the arrangement of double-gate memory transistors, the first word lines are preferably fed in a first direction, while the second word lines are fed in the opposite direction to the first direction.

In the arrangement of double-gate memory transistors, the source / drain connections of the double-gate memory transistors of one column of the arrangement are preferably coupled to one another such that the source connection of a double-gate memory transistor is connected to the drain connection of an adjacent one Double gate memory transistor is coupled to the same column of the arrangement.

In the arrangement of double-gate memory transistors, the source connections of the double-gate memory transistors of one column of the arrangement can be coupled by means of a bit line to the source connections of other double-gate memory transistors of the same column of the arrangement, while the drain connections the double-gate memory transistors of a column of the arrangement are coupled by means of a bit line to the drain connections of other double-gate memory transistors of the same column of the arrangement.

With this type of arrangement, each double-gate memory transistor of the arrangement can be individually programmed. Programming is possible using Fowler Nordheim Tunnels as well as Channel Hot Electron Tunnels. This enables NROM-like operation of the double-gate memory transistors of the arrangement. 1 o

Preferably, in the arrangement of double-gate memory transistors, the source connections of the double-gate memory transistors in one column of the arrangement are coupled to the drain connections of the double-gate memory transistors in an adjacent column of the arrangement by means of coupling lines, the coupling lines of double gate memory transistors of the same columns are coupled by means of a bit line.

By means of this arrangement of the double-gate memory transistors, a so-called AND arrangement with a virtual ground is formed.

Possible methods of deposition which can be used according to the invention are e.g. Epitaxy, Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition, Sputtering and Molecular Beam Epitaxy.

With the described method for producing a double-gate transistor, a planar, self-aligned double-gate transistor is created by means of simple, known, proven and inexpensive process steps. By using the encapsulation of the first gate as a mask when structuring the silicon layer of the SOI substrate and the insulator layer of the SOI substrate, the method is a self-aligning method and the first gate region and the second gate region lie exactly opposite one another.

Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

Show it: Fig. 1 is a schematic cross-sectional illustration of a

Layer arrangement which was formed by means of a method for producing a double gate transistor according to an exemplary embodiment of the invention, which layer arrangement has a first gate;

2 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps for preparing a wafer bonding of a method according to an exemplary embodiment of the invention;

3 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional

Partial steps of a method according to an embodiment of the invention;

Fig. 4 is a schematic cross-sectional illustration of a layer arrangement according to the invention after additional

Partial steps of a method according to an exemplary embodiment of the invention, which serve to expose an area for a second gate;

5 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to an exemplary embodiment of the invention, which serve to separate and encapsulate the second gate;

6A shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of a method according to a Embodiment of the invention, which are used to form source / drain connections of the double gate transistor;

6B shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of an additional method according to an exemplary embodiment of the invention, which serve to form source / drain connections of the double-gate transistor.

Fig. 7 is a schematic cross-sectional illustration of a

Layer arrangement, which by means of a method for producing a double gate memory transistor according to an additional

Embodiment was formed, which layer arrangement has a first gate;

8 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional

Partial steps for preparing a wafer bonding of a method according to the additional exemplary embodiment;

9 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to the additional exemplary embodiment;

10 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to the additional exemplary embodiment, which a Expose an area for a second gate;

11 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional

Partial steps of a method according to the additional exemplary embodiment, which serve to separate and encapsulate the second gate;

12A shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of a method according to the additional exemplary embodiment, which serve to form source / drain connections of the double-gate memory transistor;

12B shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of an additional method according to a second additional exemplary embodiment, which serve to form source / drain connections of the double-gate memory transistor;

Fig. 13 is a schematic cross-sectional illustration of a layer arrangement according to the invention, which the

12A or 12B in a section perpendicular to the direction of the drain current;

14 shows a schematic illustration with the aid of which regions of different photolithography steps of the additional method are explained; 15 shows a first arrangement in which double-gate memory transistors can be arranged;

16 shows a second arrangement in which double-gate memory transistors can be arranged; and

17 shows a third arrangement in which double-gate memory transistors can be arranged.

With reference to FIGS. 1 to 6B, the essential partial steps of a method according to the invention for producing a self-aligned planar double gate transistor according to an exemplary embodiment of the invention are described and explained in more detail.

FIG. 1 shows a layer arrangement according to the invention which has a first gate. The layer arrangement has an SOI substrate applied to a first silicon wafer 100. The SOI substrate has an insulator layer made of silicon oxide 101 and a silicon layer 102. An active region is defined on the silicon layer 102 for a subsequent formation of the first gate. The active region is defined by means of photolithography and subsequent etching of the silicon layer 102 of the SOI substrate. Then, in a partial step, a first gate insulating layer 103 made of silicon oxide is formed by means of thermal oxidation of the silicon layer 102 of the SOI substrate.

A first layer 104 of doped is subsequently

Polysilicon is formed on the first gate insulating layer 103. The first layer 104 of doped polysilicon is the layer which forms the first gate of the double-gate transistor after further sub-steps. In an additional sub-step, a first passivation layer 105 made of silicon nitride is formed on the layer 104 made of doped polysilicon. The first passivation layer 105 made of silicon nitride forms part of an encapsulation of the first gate. An additional sub-step of the method is the photolithographic definition of the first gate area.

The first passivation layer 105 made of silicon nitride and the first layer 104 made of doped polysilicon are then etched back in the regions which should not belong to the first gate region by means of anisotropic etching.

In an additional sub-step, a conformal deposition of a layer of silicon nitride and the subsequent anisotropic etching back of this layer of silicon nitride takes place. This will cause first sidewall layers 106, i.e. Spacer 106, produced from silicon nitride, which represent a further part of the encapsulation of the first gate.

With these method steps according to the invention, the formation of a layer arrangement according to the invention which has the first gate is completed.

Figure 2 shows the layer arrangement according to the invention after additional sub-steps, which serve to prepare a wafer bonding.

FIG. 2 shows the layer arrangement of FIG. 1 after partial areas of the layer 102 made of silicon of the SOI substrate and partial areas of the insulator layer 101 made of silicon oxide of the SOI substrate have been removed by means of anisotropic etching. As The anisotropic etching mask for removing the partial areas of the layer 102 made of silicon and the insulator layer 101 of the SOI substrate uses the encapsulation of the first gate, which has the first passivation layer 105 made of silicon nitride and the first side wall layers 106 made of silicon nitride. During the anisotropic etching, partial regions 207 of the layer 102 made of silicon of the SOI substrate are exposed.

In an additional sub-step, these exposed partial areas 207 of the layer 102 made of silicon are oxidized. An additional substep is the deposition of an auxiliary layer 208 made of undoped polysilicon in the areas of the layer arrangement which do not belong to the active area. Then a surface 219 of the auxiliary layer 208, which is at the top in FIG. 2, is

Planarized mechanical polishing. A first layer 209 of silicon oxide is subsequently deposited on the planarized surface 219 of the auxiliary layer and on the upper surface of the encapsulation, in other words on the exposed surface of the first passivation layer 105. With these method steps according to the invention, the preparation for wafer bonding of a layer arrangement according to the invention is completed.

FIG. 3 shows the layer arrangement according to the invention after additional sub-steps which relate to wafer bonding. FIG. 3 shows the layer arrangement of FIG. 2 after a second silicon wafer 310 has been bonded to the planarized surface. As a further sub-step, the first silicon wafer 100 was removed. FIGS. 3 to 5, 6A and 6B show the layer arrangement of FIGS. 1 and 2 rotated through 180 ° in the paper plane. In wafer bonding, the two thermally oxidized silicon wafers, which are pressed against each other under pressure and thereby have weak adhesion, are mechanically firmly coupled to one another. The mechanically strong coupling takes place according to this embodiment by means of a

Temperature step are carried out. Here thermal oxidation is carried out in a pure oxygen atmosphere at about 1000 ° C. In another bonding method used in an alternative embodiment, the anionic bonding, the coupling of the wafers is assisted by means of an electrical field and is carried out at a relatively low temperature of approximately 500 ° C.

FIG. 4 shows the layer arrangement according to the invention after additional sub-steps to expose an area for a second gate. FIG. 4 shows the layer arrangement of FIG. 3 after the insulator layer 101 made of silicon oxide of the SOI substrate has been removed by means of wet chemical etching. An additional sub-step is the definition of the active area by means of photolithography and subsequent etching of the layer 102 made of silicon of the SOI substrate.

A thin layer 411 made of silicon oxide is then applied to the layer arrangement according to the invention. In a region of the layer arrangement from which the insulator layer 101 made of silicon oxide of the SOI substrate has been removed, second side wall layers 412 made of silicon nitride are produced by means of conformal deposition of silicon nitride and subsequent anisotropic etching back of the conformally deposited silicon nitride. The thin layer 411 of silicon oxide is then removed in the active region.

An additional substep is the formation of a second gate insulating layer 413 for the second gate. To do this the layer 102 made of silicon of the SOI substrate is thermally oxidized. With these method steps according to the invention, the exposure of the area for the second gate is completed.

FIG. 5 shows the layer arrangement according to the invention after further sub-steps which relate to deposition and encapsulation of the second gate.

FIG. 5 shows the layer arrangement of FIG. 4 after a second layer 514 of doped in the active region

Polysilicon was deposited. This second layer 514 of doped polysilicon forms the second gate of the planar double-gate transistor. It is then chemically and mechanically polished and the second layer 514 made of doped polysilicon is etched back. An additional sub-step is the deposition of a second passivation layer 515 made of silicon nitride. The surface, which is shown in FIG. 5 above, is then planarized by means of chemical mechanical polishing. The separation and encapsulation of the second gate is completed with these method steps according to the invention.

FIG. 6A shows the layer arrangement according to the invention after additional sub-steps of a first exemplary embodiment of the invention, which sub-steps form an embodiment of

Affect source / drain connections. FIG. 6A shows the layer arrangement of FIG. 5 after the thin layer 411 of silicon oxide has been removed in the regions which do not belong to the active region.

An additional substep is the removal of the auxiliary layer 208 from undoped polysilicon and the removal of the exposed, oxidized partial regions 207 of the layer 102 from silicon of the SOI substrate. To train the In the first exemplary embodiment, a third layer 616 made of doped polysilicon is applied to source / drain connections. The surface arranged at the top in FIG. 6A is then planarized by means of chemical mechanical polishing. With these method steps according to the invention, the formation of the source / drain connections of the double-gate transistor is completed. Subsequent contacting is carried out using standard processes of backend technology.

FIG. 6B shows the layer arrangement according to the invention after additional sub-steps of a second exemplary embodiment of the invention, which sub-steps relate to the formation of source / drain connections. FIG. 6B shows the layer arrangement of FIG. 5 after the thin layer 411 made of silicon oxide has been removed in the regions which do not belong to the active region. An additional sub-step is the removal of the auxiliary layer 208 from undoped polysilicon and the removal of the exposed, oxidized partial regions 207 of the layer 102 from silicon of the SOI substrate. To form the source / drain connections, third side wall layers 617 made of polysilicon are deposited in the second exemplary embodiment. Titanium is subsequently sputtered onto the third sidewall layers 617 made of polysilicon.

In an additional sub-step, parts of the third side wall layers 617 are silicided. Silicidized areas 618 of the third side wall layers are formed. A layer of silicon oxide (not shown in FIG. 6B) is subsequently deposited and the layer arrangement is then planarized by means of chemical mechanical polishing. With these method steps according to the invention, the second embodiment of the training is Source / drain connections of the double gate transistor, completed. Subsequent contacting is carried out using standard processes of backend technology.

In summary, the invention relates to a method for

Manufacture of a planar double gate transistor, which uses known, simple and inexpensive sub-steps in semiconductor technology. Linking the individual sub-steps according to the invention produces a self-aligned planar double-gate transistor in which short-channel effects are drastically reduced by the control effect of two gates.

7 to 13B, the essential sub-steps of a method that is independent of the previously described method are described. The figures relate to the additional subject matter of the application, a method for producing a double-gate memory transistor, in which method steps of the method described with reference to FIGS. 1 to 6B are slightly modified. A method for producing a self-aligned planar double-gate memory transistor according to an additional exemplary embodiment is described and explained in more detail.

FIG. 7 shows a layer arrangement according to the invention which has a first gate. The layer arrangement has an SOI substrate applied to a first silicon wafer 700. The SOI substrate has an insulator layer made of silicon oxide 701 and a silicon layer 702. An active region of the double-gate memory transistor is defined on the silicon layer 702. The active region is defined by means of a first photolithography process and subsequent etching of the silicon layer 702 of the SOI substrate. The area in which the definition of the first active area is shown in FIG. 14 and is identified by reference numeral 1460. Furthermore, a silicon nitride layer 1350 (only visible in FIG. 13) is deposited, which is then planarized, preferably by means of chemical mechanical polishing. Here, the silicon layer 702 is preferably used as a stop layer. The silicon nitride layer 1350 is used for the electrical decoupling of the double-gate memory transistors. A first ONO layer 703 is then formed in a substep. For this purpose, a first silicon oxide layer 720 of the ONO layer is first formed, on which a silicon nitride layer 721 of the ONO layer is then formed, on which in turn a final second silicon oxide layer 722 of the ONO layer is formed.

A first layer 704 of doped polysilicon is subsequently formed on the first ONO layer 703. The first layer 704 made of doped polysilicon is the layer which forms the first gate of the double-gate memory transistor after further sub-steps.

In an additional substep, a first passivation layer 705 made of silicon nitride is formed on the layer 704 made of doped polysilicon. The first

Passivation layer 705 has a sufficient thickness that it is not completely removed in a subsequent etching to form spacers. The first passivation layer 705 made of silicon nitride forms part of an encapsulation of the first gate. An additional one

Part of the method is defining the first gate area, which is carried out with a second photolithographic process step. The area of this 14 is denoted by reference numeral 1461 in FIG.

The first passivation layer 705 made of silicon nitride and the first layer 704 made of doped polysilicon are then etched back in the regions which do not belong to the first gate region by means of anisotropic etching.

In an additional sub-step, a conformal deposition of a layer of silicon nitride and the subsequent anisotropic restoration of this layer of silicon nitride takes place. This will cause first sidewall layers 706, i.e. Spacer 706, produced from silicon nitride, which represent an additional part of the encapsulation of the first gate. The etching is carried out in such a way that partial regions of the ONO layer 703 and the silicon nitride layer 1350 which are located on the buried silicon oxide layer 702 are removed.

With these method steps according to the invention

Formation of a layer arrangement according to the invention, which has the first gate, is completed.

FIG. 8 shows the layer arrangement according to the invention after additional sub-steps, which serve to prepare a wafer bonding.

FIG. 8 shows the layer arrangement of FIG. 7 after partial regions of the ONO layer 703, the layer 702 made of silicon of the SOI substrate and partial regions of the insulator layer 701 made of silicon oxide of the SOI substrate have been removed by means of anisotropic etching. The mask is used as the mask for the anisotropic etching to remove the partial regions of the layer 702 made of silicon and the insulator layer 701 of the SOI substrate Encapsulation of the first gate, which has the first passivation layer 705 made of silicon nitride and the first side wall layers 706 made of silicon nitride, is used. During the anisotropic etching, partial areas 807 of the layer 702 made of silicon of the SOI substrate are exposed. The etching of the silicon oxide layers 720, 722 and 702 is preferably carried out selectively with respect to silicon nitride.

In an additional sub-step, these exposed partial areas 807 of the layer 702 made of silicon are oxidized. An additional substep is the deposition of an auxiliary layer 808 made of undoped polysilicon in the areas of the layer arrangement which do not belong to the active area. Then a surface 819 of the auxiliary layer 808, which is at the top in FIG. 8, is

Planarized mechanical polishing. A first layer 809 of silicon oxide is subsequently deposited on the planarized surface 819 of the auxiliary layer and on the upper surface of the encapsulation, in other words on the exposed surface of the first passivation layer 705. With these method steps according to the invention, the preparation for wafer bonding of a layer arrangement according to the invention is completed.

FIG. 9 shows the layer arrangement according to the invention after additional sub-steps which relate to wafer bonding. FIG. 9 shows the layer arrangement of FIG. 8 after a second silicon wafer 910 has been bonded to the planarized surface. As a further sub-step, the first silicon wafer 700 was removed. FIGS. 9 to 11, 12A and 12B show the layer arrangement of FIGS. 7 and 8 rotated by 180 ° in the paper plane. In wafer bonding, the two thermally oxidized silicon wafers, which are pressed against each other under pressure and thereby have weak adhesion, are mechanically firmly coupled to one another. The mechanically strong coupling takes place according to this embodiment by means of a

Temperature step. Here thermal oxidation is carried out in a pure oxygen atmosphere at about 1000 ° C. In another bonding method used in an alternative embodiment, the anionic bonding, the coupling of the wafers is assisted by means of an electrical field and is carried out at a relatively low temperature of approximately 500 ° C.

FIG. 10 shows the layer arrangement according to the invention after additional sub-steps to expose an area for a second gate. FIG. 10 shows the layer arrangement of FIG. 9 after the insulator layer 701 made of silicon oxide of the SOI substrate has been removed by means of wet chemical etching. An additional sub-step is the definition of the active area by means of photolithography and subsequent etching of the layer 702 made of silicon of the SOI substrate.

A thin layer 1011 of silicon oxide is then applied to the layer arrangement according to the invention. In a region of the layer arrangement from which the insulator layer 701 made of silicon oxide of the SOI substrate was removed, second side wall layers 1012 made of silicon nitride are produced by means of conformal deposition of silicon nitride and subsequent anisotropic etching back of the conformally deposited silicon nitride. The thin layer 1011 of silicon oxide is then removed in the active region.

An additional substep is the formation of a second gate insulating layer 1013 for the second gate, which as second ONO layer 1013 is formed from a first silicon oxide layer 1023 of the second ONO layer, a silicon nitride layer 1024 of the second ONO layer and a second silicon oxide layer 1025 of the second ONO layer. With these method steps according to the invention, the exposure of the area for the second gate is completed.

FIG. 11 shows the layer arrangement according to the invention after further sub-steps which relate to deposition and encapsulation of the second gate.

FIG. 11 shows the layer arrangement of FIG. 10 after a second layer 1114 made of doped polysilicon has been deposited in the active region. This second layer 1114 of doped polysilicon forms the second gate of the planar

Double-gate storage transistor. It is then chemically and mechanically polished and the second layer 1114 made of doped polysilicon is etched back. Sub-regions of the second silicon oxide layer 1025 of the second ONO layer 1013 are then etched back, so that sub-regions of the side wall layers 1012 made of silicon nitride are exposed. An additional sub-step is the deposition of a second passivation layer 1115 made of silicon nitride. The surface, which is shown in FIG. 11 above, is then planarized by means of chemical mechanical polishing. In planarization, the auxiliary layer made of polysilicon layer 808 preferably serves as a stop layer. An additional third photolithographic step is also carried out. The area in which the third photolithography step is carried out is provided with the reference number 1462 in FIG. 14. This photolithography step serves to decouple the two gates of the double-gate memory transistor. The active area is covered and the auxiliary layer made of polysilicon 808 is subsequently etched. A second layer of silicon oxide is then deposited in the etched-back regions and then planarized, preferably by means of chemical mechanical polishing. The second passivation layer made of silicon nitride 1115 is preferably used as a stop layer during planarization.

The separation and encapsulation of the second gate is completed with these method steps according to the invention.

FIG. 12A shows the layer arrangement according to the invention after additional sub-steps of an additional one

Embodiment of the invention, which substeps relate to the formation of source / drain connections. FIG. 12A shows the layer arrangement of FIG. 11 after the thin layer 1011 of silicon oxide has been removed in the regions which do not belong to the active region.

An additional substep is the removal of the auxiliary layer 808 from undoped polysilicon and that

Removing the exposed, oxidized partial areas 807 of the layer 702 made of silicon of the SOI substrate. In the additional exemplary embodiment, a third layer 1216 made of doped polysilicon is applied to form the source / drain connections. The surface arranged at the top in FIG. 12A is then planarized, preferably by means of chemical mechanical polishing. With these method steps according to the invention, the formation of the source / drain connections of the double-gate memory transistor is completed. Subsequent contacting is carried out using standard processes of backend technology.

FIG. 12B shows the layer arrangement according to the invention after additional sub-steps of a second additional one Embodiment of the invention, which substeps relate to the formation of source / drain connections. FIG. 12B shows the layer arrangement of FIG. 11 after the thin layer 1011 made of silicon oxide has been removed in the regions which do not belong to the active region. An additional sub-step is the removal of the auxiliary layer 808 from undoped polysilicon and the removal of the exposed, oxidized partial regions 807 of the layer 702 from silicon of the SOI substrate. In the second exemplary embodiment, third side wall layers 1217 made of polysilicon are deposited to form the source / drain connections. Titanium is subsequently sputtered onto the third side wall layers 1217 made of polysilicon.

In an additional sub-step, parts of the third side wall layers 1217 are silicided. This produces silicided areas 1218 of the third side wall layers. A layer of silicon oxide (not shown in FIG. 12B) is subsequently deposited and then the layer arrangement is preferably planarized by means of chemical mechanical polishing. With these method steps according to the invention, the second is additional

Embodiment of the formation of the source / drain connections of the double gate memory transistor, completed. Subsequent contacting is carried out using standard processes of backend technology.

For a better understanding of the structure of the layer arrangement of the double-gate memory transistor, FIG. 13 shows the layer arrangement of FIG. 12A or FIG. 12B in a cross section perpendicular to the representation in these figures.

The second silicon wafer 910 can be seen. The first layer of silicon oxide 809 is on the second silicon wafer 910 educated. Then, in turn, the first passivation layer made of silicon nitride 705, which in turn is followed by the first layer made of doped polysilicon 704 of the first gate. Subsequently, the layers of the first ONO layer 703, ie the second silicon oxide layer 722 of the ONO layer, the silicon nitride layer 721 of the ONO layer and the first silicon oxide layer 720 of the ONO layer, are shown. The silicon layer 702 of the SOI substrate, which forms the channel region of the double-gate memory transistor, can be seen in partial regions on the first ONO layer 703. Subsequently, in FIG. 13, laterally, parts of the silicon nitride layer 1350 can be seen, which serves to decouple the two gates of the double-gate memory transistor. On the channel region 702 and the silicon nitride layer 1350 is the second ONO layer 1013, which is formed from the first silicon oxide layer 1023 of the second ONO layer 1013, the silicon nitride layer 1024 of the second ONO layer 1013 and the second silicon oxide layer 1025 of the second ONO layer , educated. Furthermore, the second layer of doped polysilicon 1114, which forms the second gate of the double-gate memory transistor, is shown. This in turn shows the second passivation layer 1115 made of silicon nitride.

In FIG. 14, the various areas in which photolithographic process steps are carried out and the cutting lines along which the cross sections of FIGS. 7 to 13 are carried out are shown to illustrate the various areas. The area denoted by reference numeral 1460 represents the area in which the process steps of the first photolithographic process, ie the definition of the active area of the double-gate memory transistor, are carried out. The one designated by reference numeral 1461 Area, represents the area in which the process steps of the second photolithographic process, ie the definition of the gate region of the double-gate memory transistor, are carried out. The region denoted by reference numeral 1462 represents the region in which the process steps of the third photolithographic process, ie the covering of the active region of the double-gate memory transistor, are carried out.

Furthermore, in FIG. 14 the section line along which the cross sections of FIGS. 7 to 12B are shown is designated A-A, while the section line along which the cross section of FIG. 13 is shown is designated B-B.

FIG. 15 shows a first arrangement in which double-gate memory transistors can be arranged. The arrangement has a plurality of double-gate memory transistors in accordance with a so-called NAND arrangement of memory transistors. In such a NAND arrangement, the gate connections of each row of double-gate memory transistors are usually coupled to one another by means of a word line 1570, 1571 and 1572. In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 15, of the arrangement are coupled to one another. The gate connections of double-gate memory transistors in one row of the opposite second main side of the arrangement, which is located at the bottom in FIG. 15, are coupled to one another by means of additional word lines 1573, 1574 and 1575. As a result, the two gates of a double-gate memory transistor can be controlled independently of one another. The source and drain of the double gate memory transistors of a column are open for a NAND arrangement coupled in the usual way. Bit lines 1576, 1577 and 1578 are formed in that the source connection of a double-gate memory transistor in one column is coupled to the drain connection of a double-gate memory transistor adjacent in the column. All source / drain connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line.

With the NAND arrangement shown in FIG

Programming of the individual double-gate memory transistors is only possible using so-called Fowler Nordheim tunnels.

16 shows a second arrangement in which double-gate memory transistors can be arranged. The arrangement has a plurality of double-gate memory transistors in accordance with a so-called AND arrangement of memory transistors. In such an AND arrangement, the gate connections of each row of double-gate memory transistors are coupled to one another by means of a word line 1670, 1671 and 1672. In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 16, of the arrangement are coupled to one another. The gate connections of double gate memory transistors one

Lines of the opposite second main side of the arrangement, lying at the bottom in FIG. 16, are coupled to one another by means of additional word lines 1673, 1674 and 1675. As a result, the two gates of a double-gate memory transistor can be controlled independently of one another. The source and drain connections of the double-gate memory transistors of a column are coupled to one another in a manner customary for an AND arrangement. Bit lines 1676, 1677 and 1678 are formed by the source connection each double-gate memory transistor of a column is coupled by means of a bit line to the source of every other double-gate memory transistor arranged in the column. All source connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line. Furthermore, bit lines 1679, 1680 and 1681 are formed in that the drain connection of each double gate memory transistor of a column is coupled by means of a bit line to the drain connection of each other double gate memory transistor arranged in the column. All drain connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line.

With the AND arrangement shown in FIG. 16, each double-gate memory transistor can be controlled individually. Programming of the individual double-gate memory transistors is possible both by means of so-called Fowler Nordheim tunnels and by means of so-called channel hot electron tunnels. This also enables NROM-like operation of the double-gate memory transistors of the arrangement.

17 shows a second arrangement in which double-gate memory transistors can be arranged. The arrangement has a plurality of double-gate memory transistors in accordance with a so-called AND arrangement of memory transistors with virtual ground. The arrangement is similar to the arrangement shown in FIG. 16, except that one bit line of the source connections of the double gate memory transistors of one column is combined with one bit line of the drain connections of the double gate memory transistors of an adjacent column.

In such an AND arrangement with virtual grounding, the gate connections of each row of double-gate memory transistors are coupled to one another by means of a word line 1770, 1771 and 1772. In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 17, of the arrangement are coupled to one another. The gate connections of double gate memory transistors one

Rows of the opposite second main side of the arrangement, lying at the bottom in FIG. 17, are coupled to one another by means of additional word lines 1773, 1774 and 1775. As a result, the two gates of a double-gate memory transistor can be controlled independently of one another. The source and drain connections of the double-gate memory transistors of a column are coupled to one another in a manner customary for an AND arrangement with virtual grounding. Bit lines 1776, 1777, 1778 and 1779 are formed in that the source terminal of a double-gate memory transistor in one column is coupled to the source terminal of a double-gate memory transistor adjacent in the column. At the same time, the drain connections of the double-gate memory arrays arranged in the adjacent column are Transistors coupled to the same bit line. Thus, all source connections of the double gate memory transistors in one column of the arrangement and all drain connections of the double gate memory transistors in the adjacent column are driven by means of a bit line.

In FIGS. 15 to 17, the word lines are fed to a main side of the arrangement in a first direction, while the word lines are fed to the opposite main side in the direction opposite to the first direction. These arrangements have the advantage that this leaves more space for electronic circuits which are required to control and read out the word lines. However, it is not imperative that the word lines are fed in opposite directions. Also one

Arrangement in which the word lines are fed in the same direction is possible. The manufacture of the separate word lines on the two main sides of the arrangement is easily possible using wafer bonding.

In summary, the additional subject matter of the application creates a double-gate memory transistor, which can be produced using known and simple process steps. By means of the double-gate memory transistor, the memory density can be doubled compared to a conventional memory transistor. In the case of the formation of the double gate memory transistor with ONO layers, four bits per individual double gate memory transistor can thus be stored. It should be noted, however, that no formation of ONO layers is necessary, but that any formation of a so-called charge trapping layer can be used. The following documents are cited in this document:

[1] Limits on Silicon Nanoelectronics for Terascale Integration, J. Meindl, Q. Chen, JA Davis, Science 293, (2001) 2044-2049 [2] Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits, KW Guarini et al. , IEDM01

LIST OF REFERENCE NUMBERS

100 first silicon wafers

101 silicon oxide insulator layer of the SOI substrate

102 silicon layer of the SOI substrate

103 first. Gate insulating layer

104 first layer of doped polysilicon

105 first passivation layer made of silicon nitride

106 first sidewall layers made of silicon nitride

207 exposed parts of the silicon layer of the SOI substrate

208 Auxiliary layer made of undoped polysilicon

209 first layer of silicon oxide

219 planarized surface of the auxiliary layer made of undoped polysilicon

310 second silicon wafer

411 thin layer of silicon oxide

412 second sidewall layers made of silicon nitride

413 second gate insulating layer

514 second layer of doped polysilicon

515 second passivation layer made of silicon nitride

616 third layer of doped polysilicon

617 third side wall layers made of polysilicon

618 Silicided area of the third sidewall layers

700 first silicon wafer

701 silicon oxide insulator layer of the SOI substrate

702 silicon layer of the SOI substrate

703 first ONO layer

704 first layer of doped polysilicon

705 first passivation layer made of silicon nitride

706 first side wall layers made of silicon nitride

720 first silicon oxide layer of the first ONO layer

721 silicon nitride layer of the first ONO layer

722 second silicon oxide layer of the first ONO layer

807 exposed areas of the silicon layer of the SOI substrate

808 Auxiliary layer made of undoped polysilicon

809 first layer of silicon oxide 819 planarized surface of the auxiliary layer made of undoped polysilicon

910 second silicon wafer

1011 thin layer of silicon oxide

1012 second sidewall layers made of silicon nitride

1013 second ONO layer

1023 first silicon oxide layer of the second ONO layer

1024 silicon nitride layer of the second ONO layer

1025 second silicon oxide layer of the second ONO layer

1114 second layer of doped polysilicon

1115 second passivation layer made of silicon nitride

1216 third layer of doped polysilicon

1217 third side wall layers made of polysilicon

1218 Silicided area of the third sidewall layers 1350 Silicon nitride layer

1460 photolithography 1

1461 photolithography 2

1462 photolithography 3

1570 upper word line

1571 upper word line

1572 upper word line

1573 lower word line

1574 Lower word line

1575 lower word line

1576 bit line

1577 bit line

1578 bit line

1670 upper word line

1671 upper word line

1672 upper word line

1673 lower word line

1674 lower word line

1675 lower word line

1676 Source bit line

1677 source bit line

1678 Source bit line

1679 drain bit line

1680 drain bit line

1681 drain bit line 1770 upper word line

1771 upper word line

1772 upper word line

1773 lower word line

1774 lower word line

1775 lower word line

1776 bit line

1777 bit line

1778 bit line

1779 bit line

Claims

claims 1. A method for producing a double-gate transistor, which comprises the following steps: forming a first gate region on a silicon-on-insulator substrate of a first wafer; Forming a layer with a flat surface over the silicon-on-insulator substrate and the first gate region; Bonding a second wafer to the flat surface of the first wafer; and Forming a second gate region opposite the first gate region in the silicon-on-insulator substrate. 2. The method according to claim 1, wherein the insulator of the silicon-on-insulator substrate is made of silicon oxide. 3. The method of claim 1 or 2, wherein forming the first gate region on the silicon-on-insulator substrate comprises the following steps: Forming a first gate insulating layer on the silicon on insulator substrate; • Forming and structuring a first layer made of an electrically conductive material on the first gate insulating layer; and • partial encapsulation of the first gate area with an electrically non-conductive material. 4. The method of claim 3, wherein partially encapsulating the first gate region forming a first passivation layer and forming a first Has side wall layers made of an electrically non-conductive material. 5. The method according to claim 3 or 4, wherein silicon nitride is used as the electrically non-conductive material of the partial encapsulation of the first gate region. 6. The method according to any one of claims 3 to 5, wherein the first gate insulating layer is made of silicon oxide. 7. The method according to any one of claims 3 to 6, wherein the first layer is made of an electrically conductive material made of doped polysilicon. 8. The method according to any one of claims 1 to 7, wherein the formation of a layer with a flat surface comprises the following steps: Structuring the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate, whereby an exposed surface area of the silicon layer of the silicon-on-insulator substrate is obtained; • oxidize the exposed surface area; Forming an auxiliary layer with a flat surface; and • Forming a first layer of electrically non-conductive material at least on the flat surface of the auxiliary layer. The method of claim 8, wherein for patterning the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate the partial encapsulation of the first gate area is used as a mask. 10. The method according to any one of claims 1 to 9, wherein the bonding of the second wafer comprises the following steps: Bonding the second silicon wafer to the first layer made of a non-conductive material; Removing a carrier layer of the first wafer. 11. The method according to any one of claims 1 to 10, wherein the formation of the second gate area comprises the following steps: Structuring the insulator of the silicon-on-insulator substrate and exposing the silicon layer of the silicon-on-insulator substrate; Structuring the silicon of the silicon-on-insulator substrate as an active region; Forming a thin non-conductive layer; and • Forming second side wall layers from a non-conductive material and a second gate insulating layer in the active region. 12. The method of claim 11, wherein the second sidewall layers are made of silicon nitride. 13. The method according to any one of claims 1 to 12, wherein forming the second gate further comprises the steps of: forming a second layer of an electrically conductive material in the active region; • Formation of a second passivation layer over the active area and subsequent planarization. 14. The method according to any one of claims 1 to 13, the method further comprising the following steps: Removing part of the thin non-conductive layer; • removing the auxiliary layer; Removing the oxidized exposed surface area of the silicon layer of the silicon-on-insulator substrate; • Forming two source / drain regions by forming a third layer from an electrically conductive one Material and subsequent planarization. 15. The method of claim 14, wherein the third layer is made of an electrically conductive material of doped polysilicon. 16. The method according to any one of claims 1 to 13, the method further comprising the following steps: Removing part of the thin non-conductive layer; • removing the auxiliary layer; Removing the oxidized exposed surface area of the silicon layer of the silicon-on-insulator substrate; Forming two source / drain regions by forming third sidewall layers made of an electrically conductive material on the first gate and on the second gate; Sputtering a metal onto the third side wall layers of a conductive material; • Formation of a third passivation layer and subsequent planarization. 17. The method according to claim 16, wherein polysilicon is used as the conductive material of the third side wall regions, which is silicided after sputtering on the metal. 18. The method according to any one of claims 1 to 17, wherein the first and / or second gate insulating layer are formed as a charge trapping layer. 19. The method according to any one of claims 1 to 18, wherein the first and / or second gate insulating layer are formed as an ONO layer. 20. The method according to claim 18 or 19, wherein the first gate area and the second gate area are electrically decoupled from one another, so that they can be controlled separately from one another. 1/13 G1 105

G2

2.13

FIG4

3.13 5

4.13 FIG6A

FIG6B

5.13

FIG8

13.6 FIG9 701

7.13 IG11

8.13

9/13 FIG13

FIG14 B

11/13

12/13 IG16

13/13 IG17