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WO2003100864A2 - High-voltage semiconductor device - Google Patents

High-voltage semiconductor device Download PDF

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Publication number
WO2003100864A2
WO2003100864A2 PCT/US2003/015975 US0315975W WO03100864A2 WO 2003100864 A2 WO2003100864 A2 WO 2003100864A2 US 0315975 W US0315975 W US 0315975W WO 03100864 A2 WO03100864 A2 WO 03100864A2
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WO
WIPO (PCT)
Prior art keywords
field
sic
dmos
channel
jfet region
Prior art date
Application number
PCT/US2003/015975
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French (fr)
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WO2003100864A9 (en
WO2003100864A3 (en
Inventor
Tatsing Paul Chow
Original Assignee
Rensselaer Polytechnic Institute
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Application filed by Rensselaer Polytechnic Institute filed Critical Rensselaer Polytechnic Institute
Priority to AU2003241545A priority Critical patent/AU2003241545A1/en
Publication of WO2003100864A2 publication Critical patent/WO2003100864A2/en
Publication of WO2003100864A3 publication Critical patent/WO2003100864A3/en
Publication of WO2003100864A9 publication Critical patent/WO2003100864A9/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/121—BJTs having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the field of the invention relates to semiconductor devices, and more particularly, to semiconductor devices used in high-power applications.
  • Si Silicon
  • semiconductors referred to in the art as widegap semiconductors, particularly SiC and GaN have been the focus of development as these types of semiconductors are predicted to have much better performance than silicon.
  • semiconductors offer a lower intrinsic carrier concentration, higher electric breakdown field, higher thermal conductivity, a larger saturated electron drift velocity as compared to silicon.
  • IGBT Insulated-Gate Bipolar Transistor
  • SCR Silicon-Controlled Rectifier
  • GTO Gate-Controlled Thyristor
  • MCT MOS-Controlled Thyristor
  • MPS Merged Pin/Schottky
  • MFS MOS Barrier Schottky
  • Two or three terminal semiconductor power devices can be generally classified into unipolar and bipolar families, dependent on whether a single type of carrier (unipolar devices using electrons or holes as carriers) and both types of carriers (bipolar devices using both electrons and holes) are present during the conduction or on-state.
  • Power rectifiers e.g., Schottky rectifiers
  • power MOSFETs belong to the unipolar group while junction rectifiers, BJTs, IGBTs and thyristors (SCRs) belong to the bipolar group.
  • Unipolar devices are attractive at low breakdown voltages because of their fast switching speeds, while bipolar devices are preferred at higher breakdown voltages because of conductivity modulation of the drift region produced by double injection (lowering the on-resistance).
  • the blocking voltage rating above which bipolar devices are favored is about 300 V.
  • the cross-over voltage is approximately 2500 V.
  • a higher insulator electric field is expected for a relative permittivity lower than that of SiC due to the oxide reliability at greater temperatures.
  • a higher electric field can be expected using an oxide such as SiO .
  • the oxide SiO 2 the field is approximately 7.5 times higher than the field present when silicon is used, and the field is within 75% of the intrinsic breakdown field of 10 MV/cm.
  • hot carrier effects tend to degrade insulator quality by creating traps and SiO 2 is significantly prone to hot electron effects at temperatures as low as 3000 degrees C.
  • an improved semiconductor device that reduces the electric field located near the top of the oxide/substrate interface. More particularly, when using SiC as the substrate and SiO 2 as the oxide, and in a DMOS device, the field is reduced at the drain end of the DMOS channel near the wafer surface.
  • the trench depth (or channel length referred to hereinafter as the "mesa height") of the JFET region can be independently varied with respect to the p-body junction depth.
  • the surface electric field can be reduced with increasing mesa height.
  • the mesa height can be increased (e.g., to 2.5 ⁇ m or more as shown in Fig. 3) to reduce the surface field to that of conventional silicon planar DMOS devices.
  • This structure may be applied, for example, to any power MOS device, including IGBT and MCT device structures, and high-voltage power MOSFET devices.
  • an integrated circuit device comprising a semiconductor substrate having a surface and within which a JFET region is formed, and an oxide layer formed upon the surface of the semiconductor substrate, the device having an electrical configuration in which the JFET region is capable of being formed below the surface of the semiconductor substrate, the JFET region having a height that provides for a reduction in an electric field in the oxide layer within an operating region of the integrated circuit.
  • the device further comprises a p-body junction formed below the JFET region, and wherein the height of the JFET region is independently determined with respect to p-body junction depth.
  • the oxide layer includes SiO .
  • the substrate includes SiC.
  • the height of the JFET region is used that substantially reduces the field to a level approximating Si-based devices.
  • the integrated circuit device is a DMOS IGBT device.
  • the integrated circuit device is a DMOS MGT device.
  • the integrated circuit device is a DMOS FET.
  • a MOS channel is formed during operation of the device, and wherein the height of the JFET region reduces the magnitude of the field in the MOS channel.
  • the oxide layer includes SiO 2 and the substrate includes SiC.
  • Figure 1 is a block diagram showing a cross-sectional view of a conventional IGBT device
  • Figure 2 is a block diagram showing a cross-sectional view of a conventional DMOS MGT device
  • Figure 3 is a chart showing a relationship between a magnitude of an electric field measured in a JFET channel of a semiconductor device and a mesa height of the JFET channel according to one embodiment of the present invention
  • Figure 4 is a block diagram showing a cross-sectional view of an IGBT device according to one embodiment of the invention
  • Figure 5 is a block diagram showing a cross-sectional view of an MGT device according to one embodiment of the invention.
  • Figure 6 is a block diagram showing a cross-sectional view of a FET device according to one embodiment of the invention.
  • these surface fields may be modulated by increasing the mesa channel height of the semiconductor device to isolate the MOS channel from the high electric field. This isolation may be performed, for example, in any power switching device to increase its performance by reducing the chance of material breakdown.
  • Figure 1 shows a diagram of a type of conventional semiconductor device in whose structure may be modified according to various aspects of the invention. More particularly, Figure 1 shows a conventional DMOS IGBT device 100.
  • Device 100 includes an emitter 101, collector 102, base 106A, 106B, and gate 103.
  • Device 100 includes a semiconductor substrate 109, which may be, for example SiC, and may be P+ doped. Upon substrate 109, other layers may be formed. For instance, on this substrate is formed an N- buffer layer 108, and on top of buffer layer 108 is formed an N- drift layer 107.
  • Device 100 also includes a number of N+ regions 105A-105B formed in P- base regions 106A-106B, respectively.
  • P- base regions 106A-106B are deposited on N- drift layer 107.
  • a MOS channel 110 is formed that traverses N+ region 105 A horizontally through P- base region 106A near the surface of the N- drift layer 107 that contacts oxide layer 104, and through this channel current flows.
  • a similar MOS channel is formed through region 105B, P- base 106B and N- drift layer 107.
  • Oxide layer 104 forms a portion of gate 103 and may be made from SiO 2 as discussed above. Also, as noted above, the SiO 2 /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO 2 /Si interface due to the 8-10 time higher avalanche field in SiC. This high field is problematic, as it may be near to breakdown voltage limits of device 100 and may affect reliability.
  • FIG. 2 shows a conventional DMOS MGT device 200, wherein the DMOS channel is formed similar to that of the IGBT as discussed above with reference to Figure 1.
  • the structure of DMOS MGT device 200 may also be modified according to various aspects of the invention.
  • this conventional device may include an oxide (e.g., SiO 2 ) that contacts an SiC layer.
  • SiO 2 oxide
  • the electric field at the SiO 2 /SiC interface is higher than the corresponding SiO 2 /Si interface due to the 8-10 times higher avalanche field in SiC. As a result, there is a higher electric field produced near the DMOS channel.
  • device 200 includes an on gate 201 for turning device 200 on, and an off gate 202 for turning device 200 off.
  • Device 200 also includes a floating base 203, emitter 207, and collector 204.
  • Device 200 includes an N+ substrate 211 upon which other layers are formed. For instance, an N- drift layer 210 may be formed on top of substrate 211.
  • Device 200 also includes a number of N+ regions 205A, 205B formed in a P- base material 209 which is formed on N- drift layer 210.
  • P+ region 206 is formed between N+ regions 205 A and 205B, and is in contact with floating base 203.
  • N+ region 208 is formed on top of P- base region 209 and is in electrical contact with emitter 207.
  • oxide layers 212, 213 are also used to form the on and off gates, respectively, and are in electrical contact with SiC material of device 100.
  • oxide layer 212 interfaces with N- drift layer 210 near on gate 201.
  • these gates may be made using the SiO 2 oxide as discussed above.
  • the SiO 2 /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO /Si interface due to the 8-10 time higher avalanche field in SiC. This high voltage is problematic, as it may be near to breakdown voltage limits of device 200 and this may affect reliability of device 200.
  • one embodiment of the present invention is directed to adjusting the height of the JFET region to reduce the field near the MOS channel. This may be accomplished, for example, by lengthening the height between the SiO 2 /SiC surface and the bottom portion of the JFET region. This lengthening increases the field drop along the vertical length of the region, thereby lowering the field near the MOS channel.
  • the relation between mesa height and the magnitude of the electric field is shown with particularity in chart 300 of Figure 3.
  • Figure 3 shows a plot of the electric field at device breakdown along the center of the JFET region as a function of the trench depth (Td).
  • the surface electric field in a 5000V conventional planar DMOS transistor is approximately 1.6 MV/cm, leading to an oxide field of 4MV/cm, which is at least five (5) times higher than an Si- based related device. This high oxide field should be avoided for reliability concerns.
  • the surface field can be reduced with increasing mesa height.
  • the surface electric field is approximately 1.6 MV/cm.
  • This field may be lowered by adjusting the trench depth (of mesa height) to a value greater than zero.
  • the mesa height may be increased in this particular example to 2.5 ⁇ m or more, bringing the surface field down to a value that approaches the surface field of conventional Si planar DMOS devices.
  • a DMOS device in one embodiment, includes an increased mesa height which in turn reduces the surface field near the DMOS channel.
  • Figure 4 shows one embodiment of a DMOS IGBT device having an increased mesa height. Although an IGBT device is shown, it should be appreciated that this method of increasing the channel height may be applied to other types of semiconductor devices that are sensitive to overvoltage conditions. For instance, as shown in Figures 5 and Figure 6, aspects of the invention may be implemented in an MGT device and a power FET device, respectively.
  • the voltage drop across the JFET region significantly reduces the oxide/SiC field at the drain end of the DMOS channel near the wafer surface.
  • the electric field at device breakdown along the center of the JFET region is plotted as a function of trench depth. For trench depths larger than l ⁇ m, the oxide field is less than 1 MV/cm and similar in magnitude to that found in state-of-the-art silicon power DMOSFETs.
  • Such a trenched DMOS process can also be applied to other power MOS devices such as the IGBT and MCT. Also, such a trench DMOS structure can also be used in the termination area to reduce the surface electric field.
  • Device 400 includes a gate 401, emitters 402A, 402B and a collector 403.
  • Device 400 includes a semiconductor substrate 409, which may be, for example SiC, and may be P+ doped.
  • substrate 409 Upon substrate 409, other layers may be formed using conventional methods for depositing semiconductor materials. For instance, layers may be epitaxially grown on 6H- and 4H-SiC substrates.
  • N- drift layer 408 On this substrate 409 is formed an N- drift layer 408, and on top of drift layer 408 is formed a number of P regions 406, 407.
  • Device 100 also includes a number of N+ regions 410A-410B formed in P- regions 406, 407, respectively.
  • P- regions 406, 407 are deposited on N- drift layer 408.
  • a MOS channel 411 is formed that traverses N+ region 410A horizontally through P- region 406 near the surface of the N- drift layer 408 that contacts oxide layer 405, and through this channel current flows.
  • a similar MOS channel 412 is formed through region 410B, P- region 407 and N- drift layer 408.
  • Oxide layer 405 forms a portion of gate 401 and may be made from SiO 2 as discussed above. Also, as noted above, the SiO 2 /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO /Si interface due to the 8-10 times higher avalanche field in SiC. However, this additional field is compensated for by isolating the MOS channel from the field by lengthening the JFET channel, thereby decreasing the field near the MOS channel. As is shown, this height h (item 404) may be adjusted such that the field is within acceptable limits. For instance, as shown in Figure 3, a distance of 1 ⁇ m or greater may be selected for a DMOS device operating at 5200V having a channel width of 8 ⁇ m.
  • Figure 5 shows a view of an MGT device 500 according to one embodiment of the invention.
  • Device 500 includes an on gate 501, an off gate 502 floating base 503, emitter 504 and collector 505.
  • Device 500 also includes semiconductor substrate 507, which may be, for example, SiC, and may be N+ doped.
  • substrate 507 Upon substrate 507, other layers may be formed. For instance, on the substrate may be formed an N- drift layer 506.
  • a P- base region 510 may be deposited on N- drift layer 506.
  • a number of additional regions may be formed, including N+ region 508A, N+ region 508B, N+ region 509 and P+ region 11.
  • Oxide layer 513 forms a portion of gate 501 and may be made form SiO 2 as discussed above.
  • the SiO /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO 2 /Si interface due to the 8-10 times higher avalanche field in SiC.
  • this additional field may be compensated for by isolating MOS channel 512 from the field by lengthening the JFET channel. As is shown, this height H (item 514) may be adjusted such that the field is within acceptable limits. As discussed above with reference to Figures 3 and 4.
  • Figure 6 shows a power FET device 600 according to one embodiment of the present invention.
  • Device 600 includes a gate 601, sources 602A, 602B and a drain 603.
  • Device 600 also includes a substrate 605, which may be, for example, SiC, and this substrate may be N+ doped. Upon substrate 605, other layers may be formed. For example, on substrate 605 may be formed an N- drift layer 604.
  • Device 600 also includes a number of P regions 606A and 606B formed on N- drift layer 604. Upon P regions 606A, 606B are respectively formed N+ regions 607A and 607B.
  • Device 600 also includes source regions 602A and 602B.
  • Oxide layer 611 forms a portion of gate 601 and may be made from SiO 2 as discussed above. Also, as noted above, the SiO 2 /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO 2 /Si interface due to the 8-10 times higher avalanche field in SiC. However, this additional field may be compensated for by isolating the MOS channel (e.g., channel 609, 610) from the field by lengthening the JFET channel. As is shown in Figure 6, this height H (item 608) may be adjusted such that the field is within acceptable limits as discussed above with reference to Figures 3 and 4.
  • MOS- gated power bipolar transistors IGBT or MGT
  • junction rectifiers are good candidates for high-voltage applications.
  • BV breakdown voltage
  • unipolar transistors are fast switching, the on-resistance increases rapidly (varies as (BV) 2,5 ) with increasing breakdown voltage (BV).
  • BV breakdown voltage
  • unipolar devices are not attractive for BV over 2500 V.
  • thyristors have nearly the highest level of conductivity modulation possible but have a limited safe-operating-area under forward and reverse bias conditions (called FBSOA and RBSOA respectively) due to the formation of current filaments, which must be suppressed to prevent device failure.
  • FBSOA and RBSOA safe-operating-area under forward and reverse bias conditions
  • MOS-gated, voltage-control power bipolar transistors may be used for power applications, as these devices have minority carrier injection level higher than that of unipolar transistors but lower than that of thyristors and which exhibit current saturation in their I-V characteristics.
  • the trenched DMOS (T-DMOS) according to one embodiment of the invention may be implemented to minimize the gate oxide field and maximize gate oxide reliability.
  • the Insulated Gate Bipolar Transistor is the most popular MOS-gated bipolar transistor in silicon because of its high input impedance, low forward drop and current saturation features.
  • SiC Insulated Gate Bipolar Transistor
  • the operation of the IGBT can be modelled as a n-channel MOSFET driving a wide-base pnp bipolar transistor connected in the Darlington configuration.
  • the high substrate resistance is equivalent to adding extra emitter resistance to the pnp transistor, leading a higher forward drop.
  • the substrate resistance is not an issue because heavily doped n+ and p+ substrates are readily available.
  • the use of the complementary p- channel IGBT circumvents the problem of the p+ substrate.
  • the input MOSFET is now a p-channel device, resulting in a higher channel resistance and a lower transconductance, through its effect is tampered by the higher npn transistor gain.
  • the wide-base npn bipolar transistor has a narrower stability region than the pnp counterpart.
  • the parasistic four-layer thyristor structure present in the IGBT must be suppressed to retain gate control and to prevent latchup, which is more likely to occur at elevated temperatures.
  • MOS-gated bipolar transistor which has been previously produced in silicon
  • MOS-gated bipolar transistor is a viable alternative to the IGBT.
  • the input n-channel MOSFET is driving a narrow-base npn bipolar transistor connected also in the Darlington configuration.
  • both transistors are n-type, only three-layer parasitics exist in the device structure so that latchup is not possible.
  • a turn-off MOSFET can also be designed into the MGT.
  • This MOSFET enhances the turn-off of the npn by providing a shunting path between the emitter and base of the npn transistor and performs active turn-off.
  • the open base pnp transistor needs to be turned off by minority carrier recombination alone.
  • the MGT also has a DMOS turn-on channel, the T-DMOS can also be applied to the MGT to lower the gate oxide field. Comparing the I-V characteristic of a 5000 V IGBT and MGT (both n-channel), the MGT is very similar to the IGBT. Both the MGT and IGBT may be developed for power applications using various aspects of the invention.
  • the main advantage of the elongated trench DMOS structure is that it can reduce the electric field in the gate dielectric of SiC devices to that in conventional silicon power devices using conventional MOS processes.
  • the increased parasitic JFET channel length results in a higher parasitic JFET resistance, and the need for trench etching leads to a non-planar device surface, when compared to planar DMOS.
  • the choice of the MGT eliminates the substrate doping problem of the n-channel SiC IGBT and has a better forward drop than IGBT at room temperature though it has slightly worse forward drop of 350°C. Also, the MGT allows active turn-off and generally has a faster turn-off transient than the IGBT. Furthermore, the safe-operating-area of the MGT is equal or close to that of the IGBT despite the main constituent transistor is npn (vs. pnp for the equivalent IGBT) because of the lightly doped n collector layer and the higher electron saturation velocity.
  • MGT and the IGBT have a significantly better RBSOA and faster turn-off time (especially at elevated temperatures) than any thyristor structures, including the GTO, because of a lower level of conductivity modulation, though it also has a slightly higher forward drop.
  • Another advantageous feature of the MGT and the IGBT is that they can be driven and controlled from an integrated circuit while additional discrete active devices (e.g., a MOSFET and rectifier) and passive elements (e.g., a snubber) are needed for the GTO.
  • additional discrete active devices e.g., a MOSFET and rectifier
  • passive elements e.g., a snubber

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A semiconductor device (400) having a JFET region located between base regions (406, 407), such as an IGBT, a MGT or a DMOSFET, has an increased JFET region height (h, 404) to reduce surface fields at an oxide layer (405). Advantageously, the device is made of SIC.

Description

HIGH-VOLTAGE SEMICONDUCTOR DEVICE
Related Applications
This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application Serial No. 60/382,228, entitled "A NOVEL LOW SURFACE-FIELD DMOS STRUCTURE FOR HIGH-VOLTAGE SIC POWER MOS-GATED TRANSISTORS AND THYRISTORS," by Tatsing Paul Chow, filed on May 21, 2002, which is herein incorporated by reference in its entirety.
Federally Sponsored Research
This invention was made with Government support under DARPA MDA Contract No. 97298C0001 and Department of the Navy, Office of Naval Research Contract No. N000140110784. The Government may have certain rights to this invention.
Background of the Invention
1. Field of Invention
The field of the invention relates to semiconductor devices, and more particularly, to semiconductor devices used in high-power applications.
2. Discussion of Related Art
Silicon (Si) as long been the dominant semiconductor of choice for high-power electronics power application. However, semiconductors referred to in the art as widegap semiconductors, particularly SiC and GaN have been the focus of development as these types of semiconductors are predicted to have much better performance than silicon. There are many other materials that have been developed for power applications that are used. These semiconductors offer a lower intrinsic carrier concentration, higher electric breakdown field, higher thermal conductivity, a larger saturated electron drift velocity as compared to silicon.
These materials have the required physical properties necessary for power applications. In particular, these materials are used to manufacture various power devices used for switching applications involving high voltages and currents. For instance, the Insulated-Gate Bipolar Transistor (IGBT) is the dominant silicon power transistor that is used in high-voltage applications (> 1000V). Other devices such as, for example, the Bipolar Junction Transistor (BJT), Silicon-Controlled Rectifier (SCR), Gate-Controlled Thyristor (GTO), power MOSFET, and MOS-Controlled Thyristor (MCT), power rectifiers such as, for example, Merged Pin/Schottky (MPS) and MOS Barrier Schottky (MBS) rectifiers have been used in such power switching applications.
Two or three terminal semiconductor power devices can be generally classified into unipolar and bipolar families, dependent on whether a single type of carrier (unipolar devices using electrons or holes as carriers) and both types of carriers (bipolar devices using both electrons and holes) are present during the conduction or on-state. Power rectifiers (e.g., Schottky rectifiers) and power MOSFETs belong to the unipolar group while junction rectifiers, BJTs, IGBTs and thyristors (SCRs) belong to the bipolar group. Unipolar devices are attractive at low breakdown voltages because of their fast switching speeds, while bipolar devices are preferred at higher breakdown voltages because of conductivity modulation of the drift region produced by double injection (lowering the on-resistance). For silicon, the blocking voltage rating above which bipolar devices are favored is about 300 V. However, for SiC, because of the much-reduced drift layer thickness from the higher avalanche field, the cross-over voltage is approximately 2500 V. Despite the performances of these devices and the materials used to manufacture such devices, there are problems using these devices in the ever-increasing conditions (e.g., high voltage/current, operating temperature, switching frequency, etc.) in which these devices are expected to perform. These conditions continue to push the development of more capable devices. Therefore, there is a need to develop more capable devices for power switching applications.
Summary of the Invention
For high-voltage applications, especially at very high voltages (e.g., 5000 V), improved devices are needed. It is realized that, due to these conditions, most unipolar devices are not able to operate within this range. Therefore, junction rectifiers, bipolar transistors and thyristors may be used in such applications. In particular, IGBT, MCT, and EST devices are favored due to their ease of controllability by integrated circuits.
However, using SiC devices, a higher insulator electric field is expected for a relative permittivity lower than that of SiC due to the oxide reliability at greater temperatures. In particular, it is realized, according to one embodiment of the present invention, that due to the higher avalanche field (81 OX higher than that of silicon) and 15% lower dielectric constant, a higher electric field can be expected using an oxide such as SiO . For the oxide SiO2, the field is approximately 7.5 times higher than the field present when silicon is used, and the field is within 75% of the intrinsic breakdown field of 10 MV/cm. Also, hot carrier effects tend to degrade insulator quality by creating traps and SiO2 is significantly prone to hot electron effects at temperatures as low as 3000 degrees C.
To minimize the field produced by using an oxide such as SiO2 in combination with SiC, it is realized according to one aspect of the invention that either new gate insulators or new MOS device structures are needed. However, it is realized that by using other oxides (e.g., TiO2) having a higher relative permittivity than SiO2, the sustainable electrical potential of the dielectric is actually decreased, and therefore, the potential improvement is diminished. Also, the facial properties of the deposited oxides with the SiC material are not as good as those interfaces using SiO2. Therefore, there is a need for a new MOS structure that is capable of operating at high voltages.
According to one aspect of the present invention, an improved semiconductor device is provided that reduces the electric field located near the top of the oxide/substrate interface. More particularly, when using SiC as the substrate and SiO2 as the oxide, and in a DMOS device, the field is reduced at the drain end of the DMOS channel near the wafer surface. In particular, it may be desired to modify the structure using trench technology to isolate a MOS channel from a high substrate voltage in a JFET region of the device by increasing the trench depth. The trench depth (or channel length referred to hereinafter as the "mesa height") of the JFET region can be independently varied with respect to the p-body junction depth. Thus, the surface electric field can be reduced with increasing mesa height. For example, in a 5000V DMOS transistor having an SiO2/SiC interface, the mesa height can be increased (e.g., to 2.5 μm or more as shown in Fig. 3) to reduce the surface field to that of conventional silicon planar DMOS devices. This structure may be applied, for example, to any power MOS device, including IGBT and MCT device structures, and high-voltage power MOSFET devices.
According to one aspect of the invention, an integrated circuit device is provided comprising a semiconductor substrate having a surface and within which a JFET region is formed, and an oxide layer formed upon the surface of the semiconductor substrate, the device having an electrical configuration in which the JFET region is capable of being formed below the surface of the semiconductor substrate, the JFET region having a height that provides for a reduction in an electric field in the oxide layer within an operating region of the integrated circuit. According to one embodiment of the invention, the device further comprises a p-body junction formed below the JFET region, and wherein the height of the JFET region is independently determined with respect to p-body junction depth. According to another embodiment, the oxide layer includes SiO . According to another embodiment, the substrate includes SiC.
According to another embodiment of the invention, the height of the JFET region is used that substantially reduces the field to a level approximating Si-based devices. According to another embodiment, the integrated circuit device is a DMOS IGBT device. According to another embodiment, the integrated circuit device is a DMOS MGT device. According to another embodiment, the integrated circuit device is a DMOS FET. According to another embodiment, a MOS channel is formed during operation of the device, and wherein the height of the JFET region reduces the magnitude of the field in the MOS channel. According to another embodiment, the oxide layer includes SiO2 and the substrate includes SiC.
Further features and advantages of the present invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate like or functionally similar elements. Additionally, the left-most one or two digits of a reference numeral identifies the drawing in which the reference numeral first appears.
Brief Description of the Drawings
The accompanying drawings, are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: Figure 1 is a block diagram showing a cross-sectional view of a conventional IGBT device;
Figure 2 is a block diagram showing a cross-sectional view of a conventional DMOS MGT device;
Figure 3 is a chart showing a relationship between a magnitude of an electric field measured in a JFET channel of a semiconductor device and a mesa height of the JFET channel according to one embodiment of the present invention;
Figure 4 is a block diagram showing a cross-sectional view of an IGBT device according to one embodiment of the invention; Figure 5 is a block diagram showing a cross-sectional view of an MGT device according to one embodiment of the invention; and
Figure 6 is a block diagram showing a cross-sectional view of a FET device according to one embodiment of the invention.
Detailed Description As discussed above, new semiconductor devices that have reduced surface fields are desired to increase the reliability of such devices. In one embodiment of the present invention, these surface fields may be modulated by increasing the mesa channel height of the semiconductor device to isolate the MOS channel from the high electric field. This isolation may be performed, for example, in any power switching device to increase its performance by reducing the chance of material breakdown.
Figure 1 shows a diagram of a type of conventional semiconductor device in whose structure may be modified according to various aspects of the invention. More particularly, Figure 1 shows a conventional DMOS IGBT device 100. Device 100 includes an emitter 101, collector 102, base 106A, 106B, and gate 103. Device 100 includes a semiconductor substrate 109, which may be, for example SiC, and may be P+ doped. Upon substrate 109, other layers may be formed. For instance, on this substrate is formed an N- buffer layer 108, and on top of buffer layer 108 is formed an N- drift layer 107. Device 100 also includes a number of N+ regions 105A-105B formed in P- base regions 106A-106B, respectively. P- base regions 106A-106B are deposited on N- drift layer 107. During normal operating mode, a MOS channel 110 is formed that traverses N+ region 105 A horizontally through P- base region 106A near the surface of the N- drift layer 107 that contacts oxide layer 104, and through this channel current flows. A similar MOS channel is formed through region 105B, P- base 106B and N- drift layer 107.
Oxide layer 104 forms a portion of gate 103 and may be made from SiO2 as discussed above. Also, as noted above, the SiO2/SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO2/Si interface due to the 8-10 time higher avalanche field in SiC. This high field is problematic, as it may be near to breakdown voltage limits of device 100 and may affect reliability.
Figure 2 shows a conventional DMOS MGT device 200, wherein the DMOS channel is formed similar to that of the IGBT as discussed above with reference to Figure 1. The structure of DMOS MGT device 200 may also be modified according to various aspects of the invention. As discussed above, this conventional device may include an oxide (e.g., SiO2) that contacts an SiC layer. As discussed above, when comparing SiC DMOS devices with Si DMOS devices, the electric field at the SiO2/SiC interface is higher than the corresponding SiO2/Si interface due to the 8-10 times higher avalanche field in SiC. As a result, there is a higher electric field produced near the DMOS channel.
Specifically, device 200 includes an on gate 201 for turning device 200 on, and an off gate 202 for turning device 200 off. Device 200 also includes a floating base 203, emitter 207, and collector 204. Device 200 includes an N+ substrate 211 upon which other layers are formed. For instance, an N- drift layer 210 may be formed on top of substrate 211. Device 200 also includes a number of N+ regions 205A, 205B formed in a P- base material 209 which is formed on N- drift layer 210. P+ region 206 is formed between N+ regions 205 A and 205B, and is in contact with floating base 203. N+ region 208 is formed on top of P- base region 209 and is in electrical contact with emitter 207.
An oxide layers 212, 213 are also used to form the on and off gates, respectively, and are in electrical contact with SiC material of device 100. For instance, oxide layer 212 interfaces with N- drift layer 210 near on gate 201. Also as discussed above, these gates may be made using the SiO2 oxide as discussed above. As noted above, the SiO2/SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO /Si interface due to the 8-10 time higher avalanche field in SiC. This high voltage is problematic, as it may be near to breakdown voltage limits of device 200 and this may affect reliability of device 200. According to one embodiment of the invention, it is realized there is a high electric field produced near the MOS channel due to the higher avalanche field of the SiC material. To alleviate this field, one embodiment of the present invention is directed to adjusting the height of the JFET region to reduce the field near the MOS channel. This may be accomplished, for example, by lengthening the height between the SiO2/SiC surface and the bottom portion of the JFET region. This lengthening increases the field drop along the vertical length of the region, thereby lowering the field near the MOS channel. The relation between mesa height and the magnitude of the electric field is shown with particularity in chart 300 of Figure 3.
Figure 3 shows a plot of the electric field at device breakdown along the center of the JFET region as a function of the trench depth (Td).
As shown in Figure 3, at the device breakdown voltage, the surface electric field in a 5000V conventional planar DMOS transistor (using SiO2 and SiC) is approximately 1.6 MV/cm, leading to an oxide field of 4MV/cm, which is at least five (5) times higher than an Si- based related device. This high oxide field should be avoided for reliability concerns.
If the channel length (mesa height) of the JFET region is increased independently with respect to the P-body junction depth, the surface field can be reduced with increasing mesa height. As shown in Figure 3, for a trench depth (Td) of zero (e.g., in the conventional SiO2/SiC device), the surface electric field is approximately 1.6 MV/cm. This field may be lowered by adjusting the trench depth (of mesa height) to a value greater than zero. For instance, the mesa height may be increased in this particular example to 2.5 μm or more, bringing the surface field down to a value that approaches the surface field of conventional Si planar DMOS devices.
In one embodiment of the present invention, a DMOS device is provided that includes an increased mesa height which in turn reduces the surface field near the DMOS channel. Figure 4 shows one embodiment of a DMOS IGBT device having an increased mesa height. Although an IGBT device is shown, it should be appreciated that this method of increasing the channel height may be applied to other types of semiconductor devices that are sensitive to overvoltage conditions. For instance, as shown in Figures 5 and Figure 6, aspects of the invention may be implemented in an MGT device and a power FET device, respectively.
The voltage drop across the JFET region significantly reduces the oxide/SiC field at the drain end of the DMOS channel near the wafer surface. In Figure 3, the electric field at device breakdown along the center of the JFET region is plotted as a function of trench depth. For trench depths larger than lμm, the oxide field is less than 1 MV/cm and similar in magnitude to that found in state-of-the-art silicon power DMOSFETs. Such a trenched DMOS process can also be applied to other power MOS devices such as the IGBT and MCT. Also, such a trench DMOS structure can also be used in the termination area to reduce the surface electric field.
As discussed above, Figure 4 shows an IGBT device 400 according to one embodiment of the present invention. Device 400 includes a gate 401, emitters 402A, 402B and a collector 403. Device 400 includes a semiconductor substrate 409, which may be, for example SiC, and may be P+ doped. Upon substrate 409, other layers may be formed using conventional methods for depositing semiconductor materials. For instance, layers may be epitaxially grown on 6H- and 4H-SiC substrates. On this substrate 409 is formed an N- drift layer 408, and on top of drift layer 408 is formed a number of P regions 406, 407. Device 100 also includes a number of N+ regions 410A-410B formed in P- regions 406, 407, respectively. P- regions 406, 407 are deposited on N- drift layer 408. During normal operating mode, a MOS channel 411 is formed that traverses N+ region 410A horizontally through P- region 406 near the surface of the N- drift layer 408 that contacts oxide layer 405, and through this channel current flows. A similar MOS channel 412 is formed through region 410B, P- region 407 and N- drift layer 408.
Oxide layer 405 forms a portion of gate 401 and may be made from SiO2 as discussed above. Also, as noted above, the SiO2/SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO /Si interface due to the 8-10 times higher avalanche field in SiC. However, this additional field is compensated for by isolating the MOS channel from the field by lengthening the JFET channel, thereby decreasing the field near the MOS channel. As is shown, this height h (item 404) may be adjusted such that the field is within acceptable limits. For instance, as shown in Figure 3, a distance of 1 μm or greater may be selected for a DMOS device operating at 5200V having a channel width of 8 μm. Figure 5 shows a view of an MGT device 500 according to one embodiment of the invention. Device 500 includes an on gate 501, an off gate 502 floating base 503, emitter 504 and collector 505. Device 500 also includes semiconductor substrate 507, which may be, for example, SiC, and may be N+ doped. Upon substrate 507, other layers may be formed. For instance, on the substrate may be formed an N- drift layer 506. A P- base region 510 may be deposited on N- drift layer 506. On layer 510, a number of additional regions may be formed, including N+ region 508A, N+ region 508B, N+ region 509 and P+ region 11.
Oxide layer 513 forms a portion of gate 501 and may be made form SiO2 as discussed above. Also, as noted above, the SiO /SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO2/Si interface due to the 8-10 times higher avalanche field in SiC. However, this additional field may be compensated for by isolating MOS channel 512 from the field by lengthening the JFET channel. As is shown, this height H (item 514) may be adjusted such that the field is within acceptable limits. As discussed above with reference to Figures 3 and 4.
Figure 6 shows a power FET device 600 according to one embodiment of the present invention. Device 600 includes a gate 601, sources 602A, 602B and a drain 603. Device 600 also includes a substrate 605, which may be, for example, SiC, and this substrate may be N+ doped. Upon substrate 605, other layers may be formed. For example, on substrate 605 may be formed an N- drift layer 604. Device 600 also includes a number of P regions 606A and 606B formed on N- drift layer 604. Upon P regions 606A, 606B are respectively formed N+ regions 607A and 607B. Device 600 also includes source regions 602A and 602B.
Oxide layer 611 forms a portion of gate 601 and may be made from SiO2 as discussed above. Also, as noted above, the SiO2/SiC interface has a correspondingly higher electric field at the interface than a corresponding SiO2/Si interface due to the 8-10 times higher avalanche field in SiC. However, this additional field may be compensated for by isolating the MOS channel (e.g., channel 609, 610) from the field by lengthening the JFET channel. As is shown in Figure 6, this height H (item 608) may be adjusted such that the field is within acceptable limits as discussed above with reference to Figures 3 and 4.
Power Applications
Due to the high blocking voltage rating (5000V) and the need for ease of control, MOS- gated power bipolar transistors (IGBT or MGT) and junction rectifiers are good candidates for high-voltage applications. As mentioned above, while unipolar transistors are fast switching, the on-resistance increases rapidly (varies as (BV)2,5) with increasing breakdown voltage (BV). Most importantly, unipolar devices are not attractive for BV over 2500 V. On the other hand, thyristors have nearly the highest level of conductivity modulation possible but have a limited safe-operating-area under forward and reverse bias conditions (called FBSOA and RBSOA respectively) due to the formation of current filaments, which must be suppressed to prevent device failure. Furthermore, the filamentation process is very sensitive to material defects and inhomogenities and is hence critical dependent on the progress in the SiC material technology.
Therefore, MOS-gated, voltage-control power bipolar transistors (IGBT and MGT), may be used for power applications, as these devices have minority carrier injection level higher than that of unipolar transistors but lower than that of thyristors and which exhibit current saturation in their I-V characteristics. The trenched DMOS (T-DMOS) according to one embodiment of the invention may be implemented to minimize the gate oxide field and maximize gate oxide reliability.
The Insulated Gate Bipolar Transistor (IGBT) is the most popular MOS-gated bipolar transistor in silicon because of its high input impedance, low forward drop and current saturation features. However, implementation in SiC is more difficult since a n-channel IGBT needs a heavily doped p+ substrate and a high substrate resistance is expected due to limited maximum doping level, carrier freezeout from relatively deep acceptor levels, and low hole mobility. Physically, the operation of the IGBT can be modelled as a n-channel MOSFET driving a wide-base pnp bipolar transistor connected in the Darlington configuration. The high substrate resistance is equivalent to adding extra emitter resistance to the pnp transistor, leading a higher forward drop. In silicon, the substrate resistance is not an issue because heavily doped n+ and p+ substrates are readily available. The use of the complementary p- channel IGBT circumvents the problem of the p+ substrate.
Nevertheless, the input MOSFET is now a p-channel device, resulting in a higher channel resistance and a lower transconductance, through its effect is tampered by the higher npn transistor gain. Also, the wide-base npn bipolar transistor has a narrower stability region than the pnp counterpart. Furthermore, the parasistic four-layer thyristor structure present in the IGBT must be suppressed to retain gate control and to prevent latchup, which is more likely to occur at elevated temperatures.
Fortunately, another MOS-gated power bipolar transistor, the MOS-gated bipolar transistor (MGT), which has been previously produced in silicon, is a viable alternative to the IGBT. In the n-channel MGT, the input n-channel MOSFET is driving a narrow-base npn bipolar transistor connected also in the Darlington configuration. Besides both transistors are n-type, only three-layer parasitics exist in the device structure so that latchup is not possible. In addition to the turn-on MOPSFET, a turn-off MOSFET can also be designed into the MGT. This MOSFET enhances the turn-off of the npn by providing a shunting path between the emitter and base of the npn transistor and performs active turn-off. In comparison, in the IGBT, the open base pnp transistor needs to be turned off by minority carrier recombination alone. Because the MGT also has a DMOS turn-on channel, the T-DMOS can also be applied to the MGT to lower the gate oxide field. Comparing the I-V characteristic of a 5000 V IGBT and MGT (both n-channel), the MGT is very similar to the IGBT. Both the MGT and IGBT may be developed for power applications using various aspects of the invention. The main advantage of the elongated trench DMOS structure is that it can reduce the electric field in the gate dielectric of SiC devices to that in conventional silicon power devices using conventional MOS processes. However, the increased parasitic JFET channel length results in a higher parasitic JFET resistance, and the need for trench etching leads to a non-planar device surface, when compared to planar DMOS.
The choice of the MGT eliminates the substrate doping problem of the n-channel SiC IGBT and has a better forward drop than IGBT at room temperature though it has slightly worse forward drop of 350°C. Also, the MGT allows active turn-off and generally has a faster turn-off transient than the IGBT. Furthermore, the safe-operating-area of the MGT is equal or close to that of the IGBT despite the main constituent transistor is npn (vs. pnp for the equivalent IGBT) because of the lightly doped n collector layer and the higher electron saturation velocity. However, it has a significantly better RBSOA and faster turn-off time (especially at elevated temperatures) than any thyristor structures, including the GTO, because of a lower level of conductivity modulation, though it also has a slightly higher forward drop. Another advantageous feature of the MGT and the IGBT is that they can be driven and controlled from an integrated circuit while additional discrete active devices (e.g., a MOSFET and rectifier) and passive elements (e.g., a snubber) are needed for the GTO. This invention is not limited in its application to the details of construction and the arrangement of components set forth in the previous description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing", "involving", and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. An integrated circuit device comprising: a semiconductor substrate having a surface and within which a JFET region is formed; and an oxide layer formed upon the surface of the semiconductor substrate, the device having an electrical configuration in which the JFET region is capable of being formed below the surface of the semiconductor substrate, the JFET region having a height that provides for a reduction in an electric field in the oxide layer within an operating region of the integrated circuit.
2. The device according to claim 1, further comprising a p-body junction formed below the JFET region, and wherein the height of the JFET region is independently determined with respect to p-body junction depth.
3. The device according to claim 1, wherein the oxide layer includes SiO2.
4. The device according to claim 1, wherein the substrate includes SiC.
5. The device according to claim 4, wherein the height of the JFET region is used that substantially reduces the field to a level approximating Si-based devices.
6. The device according to claim 1, wherein the integrated circuit device is a DMOS IGBT device.
7. The device according to claim 1, wherein the integrated circuit device is a
DMOS MGT device.
8. The device according to claim 1, wherein the integrated circuit device is a DMOS FET.
9. The device according to claim 1, wherein a MOS channel is formed during operation of the device, and wherein the height of the JFET region reduces the magnitude of the field in the MOS channel.
0. The device according to claim 3, wherein the substrate includes SiC.
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