WO2003100625A1 - Controleur de memoire et interface - Google Patents
Controleur de memoire et interface Download PDFInfo
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- WO2003100625A1 WO2003100625A1 PCT/US2000/020135 US0020135W WO03100625A1 WO 2003100625 A1 WO2003100625 A1 WO 2003100625A1 US 0020135 W US0020135 W US 0020135W WO 03100625 A1 WO03100625 A1 WO 03100625A1
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- memory
- access
- data
- controller
- requester
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- 230000015654 memory Effects 0.000 title claims abstract description 164
- 230000006870 function Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 description 20
- 238000012546 transfer Methods 0.000 description 9
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- 238000012508 change request Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
Definitions
- the present invention relates generally to a memory controller architecture, and more particularly to a processor to memory interface and a memory controller within an electronic program guide (EPG) system.
- EPG electronic program guide
- AMBA Advanced Microcontroller Bus Architecture
- ASB Advanced System Bus
- a simplified memory management controller that allows multiple device to access common memories without requiring the use of multiple access operation of the type used by AMBA would be beneficial.
- a memory controller has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM controller for connection with a RAM connected to the memory data and address buses and/or a ROM controller for connection with a ROM connected to the memory data and address buses. Each such RAM controller and/or ROM controller are connected to the access priority arbiter with one or more control lines.
- the access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter.
- FIG. 1 is a block diagram of a television incorporating an electronic program guide and a preferred embodiment of the invention.
- FIG. 2 is a block diagram Of a subsection of the television shown in FIG. 1 that includes a memory controller according to one embodiment of the invention.
- FIG. 3 is a block diagram of the a memory controller according to one embodiment of the invention.
- FIG. 1 is an overall system diagram of a television incorporating an EPG.
- Figure 1 depicts a typical television equipped with an EPG including a memory controller 10 that is the subject of the invention.
- Tuner A 20 or Tuner B 22 Two tuners are shown but a reasonable system can be J ⁇ constructed with only one tuner. Multiple tuners allow a television equipped with a special PIP Display Module 30 to provide a picture-in-picture service (PIP) which is often used to monitor alternate channels of programming in a small portion of the screen while watching a program on a main channel on the PIP
- the PIP display module performs horizontal and vertical scaling of the picture to typically 1/9 or 1/16 of the original area of the source video and provides that reduced size picture for inclusion on top of the main picture at the position requested.
- the Audio/Video Select box 40 selects a video and audio source for user viewing and a video source for the PIP.
- the video sources are the tuner input (s) and, if available, baseband video inputs 50 from external source's such as a VCR.
- the selection is made under control of the Host Processor 60, which is a master control processor for the entire television set.
- the Host Processor through an appropriate control mechanism (generally the industry standard I2C bus 70) , also makes channel change requests of the tuners; controls the Audio Processor 80, which determines the speaker 90 volume; controls picture quality of the TV Display 100; controls whether the PIP is displayed and on what
- the Host Processor optionally provides for the generation of certain Onscreen Display (OSD) graphics such as menuing systems or closed-
- a final Video Combiner 120 unites the main video picture, PIP display, Guide OSD, and Host OSD into a final picture for display on the TV Display.
- the EPG receives program information and ancillary
- VBI Vertical Blanking Interval
- the first tuner is normally the main channel that is being watched actively by the user.
- the EPG system scans the main channel VBI for closed caption and Extended Data Services (XDS) , which is used for the parental lockout function.
- the EPG system also scans the main channel VBI for EPG data if it happens to have any.
- the second tuner is for the PIP if the user calls for a PIP, and the rest of the time it is the main source of EPG data .
- the PIP VBI slicer 130 is a circuit capable of decoding the data from encoded lines of the VBI and depositing it in a specified area of RAM (a "buffer") by direct memory access (DMA) .
- DMA direct memory access
- the PIP VBI slicer requests and obtains control of the memory 140 bus via the Memory Controller.
- the Guide CPU 110 executes instructions contained in ROM. As one of its main tasks, the Guide CPU processes the decoded data, which was deposited in RAM by a VBI slicer. From the decoded data, the Guide CPU creates local databases appropriate to the particular television and its users. The Guide CPU extracts appropriate portions of data from the VBI data feed (stream of data encoded in the VBI representing program information and ancillary information) according to user defined criteria (e.g. postal code, cable vs. over-the-air, cable company's identity). These databases are stored in RAM.
- VBI data feed stream of data encoded in the VBI representing program information and ancillary information
- user defined criteria e.g. postal code, cable vs. over-the-air, cable company's identity
- the Guide CPU reacts to indications of Guide-related remote control button depressions sent to it by the Host Processor.
- the Guide CPU creates a display list with associated bitmap data in memory and causes it to be displayed by activating an OSD block.
- Activating an OSD block causes display commands and data to be read from memory by DMA and the final picture is delivered to the video combiner.
- the Guide OSD 150 fills the display except for a PIP in one portion of the screen that continues to show the program the user is watching or a user selected channel. The user selects a channel via an EPG Graphical User Interface (GUI) .
- GUI EPG Graphical User Interface
- VBI password control and viewing criteria
- XDS Extended Data Services
- the EPG GUI is used to overlay such text on top of the main video display.
- the Guide can lock out access to a particular program when it compares the XDS information on the program against its data base.
- the EPG can also prevent the selection of inappropriate programming via the Guide' s GUI using advance information of content provided in the EPG' s data feed.
- Direct monitoring of the main video XDS supplements this function by preventing the override of the protection function by, for example, manual retuning of a cable set top box.
- Figure 2 is a simplified block diagram of a subsection of television circuitry illustrating the memory controller architecture of a preferred embodiment of the invention. It includes the memory controller and the devices it interfaces with. Figure 2 shows the memory controller proper standing between the four memory-accessing controllers (CPU, OSD, Main VBI, and PIP VBI) and the memory arrays (ROM, DRAM) . The four memory-accessing controllers are each interfaced to the memory controller via a separate port.
- the four memory-accessing controllers are each interfaced to the memory controller via a separate port.
- the memory controller takes memory requests from multiple sources and makes sure that no two different memory requesters hold the memory bus at the same time.
- the modules requesting access to memory via the memory controller are the OSD, the two VBI data slicers, and the Guide CPU (collectively referred to as memory requesters) .
- the OSD processor module, the VBI modules, and the CPU are also called requesters because they request access to the memory controller. They are also called bus masters and controllers because they are able to be masters of the main Memory Bus, the bus of the external memory devices.
- the VBI modules are also called data slicers because they slice, i.e., extract, VBI data from a video signal.
- the memory controller arbitrates access to memory and determines which of the memory requesters shall be given access.
- the Memory Controller contains at least a ROM access controller and a RAM access controller.
- the memory requesters can provide advance information of the number of consecutive memory locations that they need to access in the form of a burst count.
- the Memory Controller decrements this number to zero as it processes the request while it increases the address starting from the initial address provided by the 0 requester.
- the automatic increment of the address in the memory controller allows the memory requesters to be simplified in that they do not have to have the duplicate function of an address incrementer. Not all memory requesters necessarily know in advance how many consecutive locations are required, but a persistent request for one access with an increasing address has the same effect.
- the ROM and RAM access controllers share an address path and data path but otherwise they are separate finite state machines.
- the ROM and RAM access controllers can be typical implementations Q that are well known to those of ordinary skill in the art and will not be described in detail here.
- the memory controller proper is comprised of the Address Path module 170, Data Path module 180, Read-Only Memory (ROM) Control module 190, Synchronous Dynamic Random Access Memory 5 (SDRAM) Control module 200, and Fast-Page Dynamic RAM (FP DRAM) Control module 210.
- External to the memory controller proper are the On-Screen Display (OSD) processor module 150, Picture-In- Picture Vertical Blanking Interval (PIP VBI) module 130, Main Vertical Blanking Interval (VBI) module 160, Central Processing Q Unit (CPU) 110, Read-Only Memory (ROM) 220, and Dynamic Random Access Memory (DRAM) 230.
- OSD On-Screen Display
- PIP VBI Picture-In- Picture Vertical Blanking Interval
- VBI Main Vertical Blanking Interval
- CPU Central Processing Q Unit
- ROM Read-Only Memory
- DRAM Dynamic Random Access Memory
- the OSD 150 is a subsystem for displaying graphics. It is used for the display of TV menus, program guide, closed caption and other graphical objects.
- the OSD Controller is responsible for requesting OSD control and display data from the memory controller. It obtains its information from DRAM by direct memory access.
- the VBI modules are Vertical Blanking Interval data processors.
- the Main 160 and PIP 130 VBI data modules are identical. They receive a video signal from a television tuner module at baseband (independently tuned) and attempt to retrieve/decode data encoded on certain scan lines in the vertical blanking interval. The distinction between the two is the kind of input they receive and how the VBI modules are used. The two VBI data modules get their names from the kind of input they receive. "Main" refers to the channel being watched.
- the Main VBI data module usually receives its input from a first and main tuner which is used to tune a television to the channel to be watched.
- the PIP data module usually receives its input from a second tuner which is ordinarily used for the PIP function.
- the Main VBI data module 160 processes data for the main picture and is important for acquiring Closed Caption data and Extended Data Services (XDS) for parental control functions.
- the PIP VBI data module 130 is a bit of a misnomer. It really relates to the Guide Data channel from which guide databases are derived.
- the Guide Data channel is sometimes via the first tuner, but is ordinarily via the second tuner in order to keep the Guide Data channel independent of the channel being watched.
- the second tuner when the PIP function is not turned on, the second tuner is available for data services even while someone is watching the television.
- data can be acquired from the channel being watched even while acquiring data from a channel not being watched.
- These modules receive instructions on which lines to scan from DRAM and write data to DRAM by direct memory access.
- the CPU 110 is the main control element of the electronic program guide.
- the CPU is either a slave of the television's host microcontroller (they communicate by serial communications bus) or is itself the central television controller and the electronic program guide function is one of its subfunctions .
- the ARB 240 is an access priority arbiter, which decides which of the multiple masters should obtain control of the memory controller at the next free cycle.
- the ARB ensures that only one requester at a time is allowed to initiate data transfers.
- the ARB does not attempt to equalize access among the OSD, PIP VBI, Main VBI, and the CPU.
- the ARB has a set priority scheme in which the OSD has highest priority, the two VBI controllers come next (with priority between the two assigned arbitrarily at design time) , and finally the CPU has lowest priority.
- the CPU is ordinarily granted access by default since it is the lowest priority requester in the arbitration chain.
- FPDRAM Fast-Page Dynamic RAM, the usual sort of dynamic RAM sold since the late 1970s. It has a close relative called Extended Data Output (EDO) DRAM, a memory design that holds its data valid after a read instead of three-stating the data lines when the column address strobe goes inactive.
- EDO Extended Data Output
- the FPDRAM controller 210 supports both memory techniques.
- the Synchronous DRAM (SDRAM) controller 200 implements the access control method for Synchronous DRAMs, a particular type of DRAM that has a clocked (synchronous) control interface.
- the FPDRAM controller implements the access method for fast page DRAMs.
- Both controllers, SDRAM control and FPDRAM control are finite state machines that sequence through a set of states as required to perform the required functions.
- the usual control lines of RAS, CAS, and MWE are encoded to form commands to the SDRAM that are committed to the chip at the rising edge of a clock.
- the level of these signals and the order in which they are asserted has continuous significance to the FPDRAM -- a change to any of these signals is a change of state of the access control.
- the ROM controller 190 controls both RAM and ROM.
- the Address path module 170 is used to determine the address of a read/write from/to memory.
- the Data path module 180 is used to read/write data from/to memory.
- the CPU bus in one embodiment of the invention is an Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB) as described in the AMBA specification Revision D (available from Advanced RISC Machines (ARM) Ltd.) which is hereby incorporated by reference as if set forth herein in its entirety.
- the ASB is capable of multiple access operation but the AMBA arbitration method is not implemented in this embodiment, preferring to regulate access of memory by the CPU
- a desirable result of the invention is to provide a simple method for many controllers to gain access to an external memory controller without having to implement the multiple access method such as the one prescribed in the AMBA specification. Using the invention's method of accessing memory simplifies memory access,
- the AMBA arbiter 35 would be regulated by an AMBA arbiter.
- the AMBA arbiter would have been on the outside of the memory controller and would involve a bus hand-over-like mechanism, such as a bus- request/bus-grant mechanism.
- the memory controller arbitration implemented in the current embodiment avoids using the ARM processor's multiple master interface.
- access to the memory controller is priortized from the top of figure 2 (OSD) to the bottom of figure 2 (CPU) .
- the OSD has the highest priority for accessing the memory controller;
- the PIP VBI has the second highest priority for accessing the memory controller;
- Main VBI has the third highest priority for accessing the memory controller; and the CPU has the lowest priority for accessing the memory controller.
- the arbitration algorithm of the embodiment described can be summarized as follows: if OSD request is asserted, OSD is granted next -,5 else if PIP VBI request is asserted, PIP VBI is granted next else if Main VBI request is asserted, Main VBI is granted next else if CPU request is asserted, CPU is granted next
- a burst count is the number of memory accesses that a requester is requesting
- a burst count is a count of memory accesses of a given size in bytes that is requested (Burst count times size in bytes equals total bytes requested) .
- the ability to provide a burst count provides predictable total access duration which can be used by the designer of the memory controller to control the arbitration algorithm such as by temporarily altering priorities to allow a very short request to take place before a much longer request made by a normally higher priority requester in order to minimize total wait time, or by suspending a long access in progress in order to accept a very short request before resuming the longer access.
- the method of providing pre-determined burst counts is implemented by having the requesters supply a starting address, a direction of the transfer (read or write) , a width of the transferred object (byte, word, etc.), and a count of the number of accesses. Once the memory controller acknowledges a request,
- the memory controller has all the address and control information it requires to complete the burst access (the requester has to continue to supply data to be written for a write burst) .
- This method presumes that the requester knows in advance how many consecutive memory objects it requires to transfer (this is often
- an arbiter in scheduling access to the bus. For example, unlike a fixed scheme, an arbiter might let through a one-word request from one requester in front of a 16-word request from another requester because it will minimize total wait time aggregated among all requesters.
- VBI slicers are peripherals of the main processor (CPU) and either interrupted the processor when they had new data available or they were polled by the CPU to ' deliver their data.
- CPU main processor
- Such systems typically contained a limited amount of temporary storage for VBI data to be held pending the CPU's reading the data and transferring it to a designated area of main memory.
- the CPU will be busy executing critical code from which it cannot be interrupted, allowing insufficient time to read the data from the VBI slicer before newer data supplants the still unread data. This is a problem of insufficient latency,
- the VBI slicers are designed as programmable direct memory access (DMA) , c controllers which are capable of requesting access to the main memory bus for the purpose of depositing new data in a designated area of main memory.
- DMA direct memory access
- c controllers which are capable of requesting access to the main memory bus for the purpose of depositing new data in a designated area of main memory.
- the CPU had only as much time as was available between the last byte of VBI data of one scan line and the first byte of VBI data of the next scan line to access the VBI slicer in order for the VBI slicer to take the data and transfer it to a designated area of main memory for further analysis.
- FIG. 3 provides more detail of the memory controller
- the ARB 240 decides which of the four sources, i.e., which of the four requesters (OSD, PIP VBI, Main VBI, or CPU), has won the right to control the memory controller bus.
- the memory controller bus is comprised of the enlarged paths shown in figure 3, i.e., the address path, write data path, and the
- the Address path module 170 generates the multiplexed DRAM address, saves the current open DRAM rows for comparison, and maintains the address counter to support burst accesses to consecutive addresses.
- the Data path module 180 steers bytes for the outbound and inbound data buses to assure proper data positioning and latches outbound and inbound data to assure proper timing for memory data transfers.
- the Refresh Request block 250 regulates the DRAM refresh process.
- the Refresh Request block generates a regular DRAM refresh request. The regular refreshes are required by the DRAM for proper data retention .
- the Aux Control/Byte Select module 260 maintains a counter for sub-accesses (intermediate accesses to fill out an access request that is wider than the physical device) , burst accesses (the number of consecutive locations required is decremented to zero) , and byte decode logic to control the Data Path byte steering .
- ROM Control 190, SDRAM Control 200, and FP DRAM Control 210 are finite state machines with synchronous control outputs.
- the SDRAM and FP DRAM control machines are mutually exclusive; a configuration bit chooses which of the two is active.
- Access can include multiple accesses in a burst to consecutive memory addresses.
- a requester can assert its request on the memory controller and have uninterrupted access for multiple memory cycles for as many memory cycles that it needs.
- memory requesters are designed to limit the number of consecutive accesses that they may request to a specified number, such as eight accesses, to try to prevent the memory controller from starving the other memory requesters. Given the limit on memory accesses, the memory controller does not have to try to make intelligent decisions in the memory controller about which memory requester should get access.
- Other systems may grant memory access to a requester which only needs a single-cycle access to memory, and thereafter continue with its priority scheme. However, in the preferred embodiment of the invention, the memory controller has an upper limit on access size.
- Whichever requester is accessing the memory bus gets priority over all of the other requesters and is expected to relinquish the bus once it does not need the memory bus. This is a simplification made in the design of the memory controller made possible by a restriction in the design of the alternate memory requesters.
- a single burst access request of count N is accepted by the memory controller when it returns an access acknowledge signal (ACK) .
- ACK access acknowledge signal
- requester If the requester needs to access even more data after these N accesses, it could keep its request asserted and may continue to have memory bus access. A requester can be "friendly" to the other requesters and rescind its request upon the acknowledgement -- the N accesses of the burst are still going to be made for it
- the memory controller is three controllers in one: ROM Controller 190, SDRAM Controller 200, and FPDRAM Controller 210.
- the synchronous DRAM controller and the fast page DRAM controller are mutually exclusive. They share a configuration register.
- An application uses either one of the DRAM controllers. There are different timing fields that are supplied in the configuration register for how many cycles of wait states to do ' in different states of the access.
- the SDRAM controller and the FPDRAM controller are two different controllers and they stay out
- the ROM controller 190 is actually a ROM/SRAM (Static RAM) controller for accessing traditional static RAM or read only memory devices, wherein access is made upon presentation of an address and assertion of a chip select signal.
- ROM/SRAM Static RAM
- the ROM controller is designed so that if a refresh cycle to the DRAM is needed (either of the two DRAM types, SDRAM or FPDRAM) , the DRAM can be refreshed while accessing the ROM. Thus, it is not necessary to suspend ROM activity while refreshing the DRAM since refreshing the DRAM does not require the use of the address or data buses.
- the ROM memory controller is designed so that the size of the device width can be programmed. Consequently, a 16 bit wide DRAM or a 32 bit wide DRAM array could be attached to the chip and has logic that executes the correct number of cycles to fill out the requested memory object. Thus, if a 32-bit word is to be written to a 16-bit wide DRAM, the ROM memory controller will do two consecutive write cycles to two consecutive memory addresses and the processor will only receive a single ready back. The processor does not, itself, have to break up the 32-bit word into multiple addresses. The ROM controller goes down to the byte level so that it can do four consecutive single byte accesses to fill out a 32-bit word access to an eight bit wide memory device.
- the signals emerging from the ARB are really pass-throughs of signals from the winning requester. That is, the aggregate of signals passing between the ARB and the memory controller modules are a memory bus equivalent to any one of the buses connecting each of the memory requesters to the ARB.
- Read Data inbound data from a read access
- ack access request acknowledge -- address, dir, bcount, etc. have been captured on local registers and the requester is free to remove the request or move on to the next request
- rdy data transfer ready -- the write data has been written or the read data is now available
- Adrs memory address, possibly from a burst counter that advances to the next higher address after the previous access completes
- rfreq fresh request -- regular refreshes are required by the DRAM for proper data retention, and this regulates this process
- ale address latch enable -- captures the address, dir, bcount, size at the next clock
- ainc address increment control -- causes the address counter to count up by the proper amount depending on width of memory device and size of access request
- row-match current address matches a previous valid row address and therefore may be qualified for DRAM burst access
- acc-done access of a narrow memory device is complete -- to fulfill a request that is wider than the physical device, multiple accesses are made and this signal indicates that a sufficient number of these "sub-accesses" have been completed)
- brst-done burst done -- the memory accesses requested in Bcount have been completed
- bsel byte select -- chooses a byte lane or set of byte lanes for steering data properly in a read or write access
- the Address Path unit maintains the current access address of the external memory device, computes the next address, and performs address multiplexing for dynamic RAMs as required.
- the address path unit also remembers up to four current row addresses that are eligible for burst access if the current address matches an open row. (If the current address doesn't match, the DRAM controller must close down the open row of the bank that contains the target address and open the row of the target address) .
- the Data path contains holding registers for outbound and inbound data and contains byte-steering logic to assure that the data bytes arrive at the appropriate set of data lines of the memory device on a write or from the memory device on a read.
- the Aux Control/ Byte Select logic counts sub-accesses for filling out a request for memory that is wider than the external device (if necessary) , counts out a multiple access burst (in our case, from 1 to 15 consecutive addresses), and computes byte selection strobes for proper steering of data based on the current address least-significant-bits (LSBs) and the access Size .
- LSBs least-significant-bits
- the ROM Controller is a finite state machine that governs timing and control for accessing a conventional SRAM or ROM device. Timing control fields are provided to the ROM controller from a configuration word in this embodiment, although they could also be fixed timing by design (programmable timing control is more versatile) .
- the SDRAM Controller is a finite state machine that governs timing and control for accessing a synchronous DRAM.
- the timing controls are programmable via a configuration word.
- the SDRAM controller also automatically configures the SDRAM for its initial setup at system start time based on the configuration word (for example, to enable burst access or to establish the access latency) .
- the SDRAM controller also refreshes the SDRAM in response to the refresh request from the Refresh Request block.
- the SDRAM controller generally attempts to use burst mode access of an open row for better system performance. There can be up to two rows open simultaneously in different banks of the SDRAM in smaller SDRAM devices (e.g. 16 megabit) and up to four rows open simultaneously in different banks of the SDRAM in larger SDRAM devices (e.g. 64 megabit).
- the FP DRAM Controller is a finite state machine that governs timing and control for accessing a fast page mode (FP) or extended data out (EDO) type of DRAM.
- the timing controls are programmable via a configuration word.
- the FP DRAM controller also refreshes the FP DRAM in response to the refresh request from the Refresh Request block.
- the FP DRAM controller generally attempts to use fast page mode burst access of a currently open row for better system performance. When this . is not possible, it automatically closes the open row by precharging it and opens a new row to begin the desired access.
- the Refresh Request block generates a regular DRAM refresh request by dividing a 1 MHz clock by a programmed constant governing the interval between refresh requests.
- a minimum number of refresh accesses must be accomplished within a specified time period (e.g. 4096 refreshes within 64 milliseconds) in order to ensure proper data retention of the device.
- refreshes may be made in bursts (e.g.. four back-to-back) or individually for better overall system performance.
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Abstract
Priority Applications (2)
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PCT/US2000/020135 WO2003100625A1 (fr) | 2000-07-26 | 2000-07-26 | Controleur de memoire et interface |
AU2000262348A AU2000262348A1 (en) | 2000-07-26 | 2000-07-26 | Memory controller and interface |
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PCT/US2000/020135 WO2003100625A1 (fr) | 2000-07-26 | 2000-07-26 | Controleur de memoire et interface |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8171187B2 (en) | 2008-07-25 | 2012-05-01 | Freescale Semiconductor, Inc. | System and method for arbitrating between memory access requests |
US8706928B2 (en) | 2009-11-26 | 2014-04-22 | Freescale Semiconductor, Inc. | Integrated circuit and method for reducing violations of a timing constraint |
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EP0322065A1 (fr) * | 1987-12-23 | 1989-06-28 | Laboratoires D'electronique Philips | Système graphique avec controleur graphique et controleur de DRAM |
EP0691616A1 (fr) * | 1994-07-08 | 1996-01-10 | Advanced Micro Devices, Inc. | Unité de commande de mémoire morte et de mémoire vive |
JPH11191075A (ja) * | 1997-08-28 | 1999-07-13 | Oki Electric Ind Co Ltd | メモリアーキテクチャーのための優先符号化及び復号化 |
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2000
- 2000-07-26 AU AU2000262348A patent/AU2000262348A1/en not_active Abandoned
- 2000-07-26 WO PCT/US2000/020135 patent/WO2003100625A1/fr active Application Filing
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Cited By (2)
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US8171187B2 (en) | 2008-07-25 | 2012-05-01 | Freescale Semiconductor, Inc. | System and method for arbitrating between memory access requests |
US8706928B2 (en) | 2009-11-26 | 2014-04-22 | Freescale Semiconductor, Inc. | Integrated circuit and method for reducing violations of a timing constraint |
Also Published As
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AU2000262348A1 (en) | 2003-12-12 |
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