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WO2003038878A2 - Procede de fabrication de structures semi-conductrices - Google Patents

Procede de fabrication de structures semi-conductrices Download PDF

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Publication number
WO2003038878A2
WO2003038878A2 PCT/US2002/032345 US0232345W WO03038878A2 WO 2003038878 A2 WO2003038878 A2 WO 2003038878A2 US 0232345 W US0232345 W US 0232345W WO 03038878 A2 WO03038878 A2 WO 03038878A2
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Prior art keywords
monocrystalline
layer
depositing
oxide
alkaline earth
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PCT/US2002/032345
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English (en)
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WO2003038878A3 (fr
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Zhiyi Yu
Ravindranath Droopad
Corey Overgaard
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Motorola Inc.
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Publication of WO2003038878A2 publication Critical patent/WO2003038878A2/fr
Publication of WO2003038878A3 publication Critical patent/WO2003038878A3/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing

Definitions

  • This invention relates generally to semiconductor structures and to a method for their fabrication, and more specifically to semiconductor structures and to the fabrication of semiconductor structures that include a monocrystalline material layer comprised of semiconductor material and/or compound semiconductor material formed overlying a monocrystalline insulator layer.
  • Semiconductor devices often include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and band gap of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases.
  • a variety of semiconductor devices could advantageously be fabricated in or using that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material.
  • a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material.
  • the monocrystalline material layer may be comprised of a semiconductor material or a compound semiconductor material.
  • FIGS. 1, 2, and 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer
  • FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer
  • FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer
  • FIGS. 9-12 illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention.
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a monocrystalline material layer 26.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline material layer 26.
  • the template layer which may also include a wetting layer, helps to initiate the growth, and especially to initiate high quality two dimensional growth, of the monocrystalline material layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22, in accordance with an embodiment of the invention is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter.
  • the wafer can be of, for example, a material from Group IV of the periodic table.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24.
  • the amo ⁇ hous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer.
  • monocrystalline material layer 26 which may comprise a semiconductor material, a compound semiconductor material, or another type of material such as a metal or a non-metal.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer.
  • the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer.
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal/transition metal oxides such as alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafhates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, gadolinium oxide, and other perovskite oxide materials. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements. As will be explained more fully below, proper preparation of the underlying substrate is advantageous to the growth of the monocrystalline accommodating buffer layer.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 nanometers (nm).
  • the material for monocrystalline material layer 26 can be selected, as desired, for a particular structure or application.
  • the monocrystalline material of layer 26 may comprise a compound semiconductor which can be selected, as needed for a particular semiconductor structure, from any of the Group IHA and VA elements (III- N semiconductor compounds), mixed IH-N compounds, Group II (A or B) and VIA elements (II- VI semiconductor compounds), mixed UNI compounds, Group IN and VI elements (IN-NI semiconductor compounds), mixed IV- VI compounds, Group IN element (Group IV semiconductors), and mixed Group IV compounds.
  • Examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), lead selenide (PbSe), lead telluride (PbTe), lead sulfide selenide (PbSSe), silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon germanium carbide (SiGeC), and the like.
  • GaAs gallium arsenide
  • GaAs gallium indium arsenide
  • GaAlAs gallium aluminum arsenide
  • InP indium phosphide
  • CdS cadmium sulfide
  • CdHgTe cadmium mercury tell
  • monocrystalline material layer 26 may also comprise other semiconductor materials, metals, or non-metal materials which are used in the formation of semiconductor structures, devices and/or integrated circuits.
  • Appropriate materials for template 30 are discussed below. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of monocrystalline material layer 26.
  • template layer 30 has a thickness ranging from about 1 to about 10 monolayers.
  • the template may also incorporate a wetting layer which helps to initiate high quality two dimensional crystalline growth.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional monocrystalline layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer may then be optionally exposed to an anneal process to convert at least a portion of the monocrystalline accommodating buffer layer to an amorphous layer.
  • Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and additional monocrystalline layer 26 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing— e.g., monocrystalline material layer 26 formation.
  • Additional monocrystalline layer 38 may include any of the materials described throughout this application in connection with either of monocrystalline material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline Group IN or monocrystalline compound semiconductor materials.
  • additional monocrystalline layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent monocrystalline layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline material.
  • additional monocrystalline layer 38 comprises monocrystalline material (e.g., a material discussed above in connection with monocrystalline layer 26) that is thick enough to form devices within layer 38.
  • monocrystalline material e.g., a material discussed above in connection with monocrystalline layer 26
  • a semiconductor structure in accordance with the present invention does not include monocrystalline material layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one monocrystalline layer disposed above amorphous oxide layer 36.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of Sr z Ba. ⁇ - z TiO 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the monocrystalline material layer 26 from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.
  • monocrystalline material layer 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer is formed by capping the oxide layer.
  • the template layer is preferably 0.5-10 monolayers of Ti-As, Ti-O-As, Ti-O-Ga, Sr-O-As, Sr-Ga-O, or Sr-Al-O.
  • 0.5-2 monolayers of Ti-As or Ti- O-As have been illustrated to successfully grow GaAs layers.
  • the template layer can also include a wetting layer on its upper surface.
  • the wetting layer is formed of a material that changes the surface energy of accommodating buffer layer to aid in the monocrystalline growth. Suitable materials for the wetting layer include, for example, metals, intermetallics, and metal oxides having a cubic crystalline structure.
  • the thickness of the wetting layer is preferably 0.5-5.0 monolayers.
  • monocrystalline substrate 22 is a silicon substrate as described above.
  • the accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer.
  • the accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 4 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO 3 , BaZrO 3 , SrHfO 3 , BaSnO 3 or BaHfO 3 .
  • a monocrystalline oxide layer of BaZrO 3 can grow at a temperature of about 700 degrees C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.
  • an accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of a monocrystalline material layer which comprises compound semiconductor materials in the indium phosphide (InP) system.
  • the compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGalnAsP), having a thickness of about 1.0 nm to 10 ⁇ m.
  • a suitable template for this structure is about 0.5-1 monolayers of one of a material M-N and a material M-O-N, wherein M is selected from at least one of Zr, Hf, Ti, Sr, and Ba and N is selected from at least one of As, P, Ga, Al, and In.
  • the template may comprise 0.5-10 monolayers of zirconium-arsenic (Zr-
  • zirconium-phosphorus Zr-P
  • hafnium-arsenic Hf-As
  • hafnium-phosphorus Hf- P
  • strontium-oxygen-arsenic Sr-O-As
  • strontium-oxygen-phosphorus Sr-O-P
  • barium-oxygen-arsenic Ba-O-As
  • indium-strontium-oxygen In-Sr-O
  • barium- oxygen-phosphorus Ba-O-P
  • the surface is terminated with 0.5-2 monolayers of zirconium followed by deposition of 0.5-2 monolayers of arsenic to form a Zr-As template.
  • the template layer may be completed with an appropriate wetting layer to facilitate the two dimensional monocrystalline growth of a subsequent layer.
  • a monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer.
  • the resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
  • a structure is provided that is suitable for the growth of an epitaxial film of a monocrystalline material comprising a II- VI material overlying a silicon substrate.
  • the substrate is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer material is Sr x Ba ⁇ x TiOs, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 3-10 nm.
  • the II- VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe).
  • a suitable template for this material system includes 0.5-10 monolayers of zinc-oxygen (Zn-O) followed by 0.5-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface.
  • a template can be, for example, 0.5-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSSe.
  • the template can also include an appropriate wetting layer.
  • This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, accommodating buffer layer 24, and monocrystalline material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AlhiP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • buffer layer 32 includes a GaAs x P ⁇ - x superlattice, wherein the value of x ranges from 0 to 1.
  • buffer layer 32 includes an InyGa ⁇ -yP superlattice, wherein the value of y ranges from 0 to 1.
  • the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying monocrystalline material which in this example is a compound semiconductor material.
  • the compositions of other compound semiconductor materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • the superlattice period can have a thickness of about 2-15 nm, preferably, 2-10 nm.
  • the template for this structure can be the same of that described in example 1.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about 0.5-2 monolayers can be used as a nucleating site for the subsequent growth of the monocrystalline material layer which in this example is a compound semiconductor material.
  • the formation of the oxide layer is capped with either a 0.5-1 monolayer of strontium or a 0.5-1 monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the layer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • the same wetting agents described above in example 1 can be used to initiate high quality two dimensional growth of the germanium layer.
  • Substrate material 22, accommodating buffer layer 24, monocrystalline material layer 26 and template layer 30 can be the same as those described above in example 2.
  • additional buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline material layer.
  • the buffer layer a further monocrystalline material which in this instance comprises a semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs).
  • additional buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 50%.
  • the additional buffer layer 32 preferably has a thickness of about 10-30 nm.
  • Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline material which in this example is a compound semiconductor material.
  • Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline material layer 26.
  • Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above).
  • amorphous layer 36 may include a combination of SiO x and Sr z Ba ⁇ - z TiO 3 (where z ranges from 0 to 1), which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of monocrystalline material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 1 nm to about
  • Layer 38 comprises a monocrystalline material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
  • layer 38 includes the same materials as those comprising layer 26.
  • layer 38 may include materials different from those used to form layer 26.
  • layer 38 is about 1 nm to about 500 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal.
  • the thickness of achievable, high quality crystalline layer decreases rapidly.
  • the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amo ⁇ hous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal.
  • the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr x Bai- x TiOs, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide.
  • the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal.
  • a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is oriented on axis or, at most, about 6° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate may encompass other structures.
  • the term "bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • a thin silicon oxide is then intentionally grown on the semiconductor substrate.
  • the thin silicon oxide is grown immediately prior to the formation of the monocrystalline accommodating buffer layer, and can be grown by thermal or chemical oxidation of the silicon surface.
  • the thin silicon oxide is grown by exposing the substrate surface to an ultraviolet (UN) lamp in the presence of ozone for a time period of up to about 20 minutes.
  • the wafer is initially at room ambient temperature, but heats to a temperature of between 20°C and 100°C by the end of the treatment.
  • the semiconductor substrate can be exposed to an rf or an ultraviolet (UN) lamp in the presence of ozone for a time period of up to about 20 minutes.
  • the thin silicon oxide can be grown by exposing the substrate to an ozone ambient at an elevated temperature in the same processing apparatus, such as a molecular beam epitaxy (MBE) reactor, used for the subsequent deposition of the accommodating buffer layer.
  • MBE molecular beam epitaxy
  • Use of ozone treatment to grow the oxide has the beneficial effect of removing carbon contamination from the surface of the substrate.
  • the native and/or grown oxide layer must first be removed to expose the crystalline structure of the underlying substrate.
  • the following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer (preferably 1-3 monolayers) of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus.
  • the substrate is then heated to a temperature above 700° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface may exhibit an ordered 2x1 structure.
  • the structure may be exposed to additional strontium until an ordered (2x1) structure is obtained.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkaline earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of above 700°C.
  • the surface reconstruction changes at least from 3x2 to 2x1 to 5x1 to 7x1 and then to 3x1.
  • the temperature is maintained at between about 200°C and 700°C during the additional deposition.
  • Surface reconstruction can be monitored in real time by using reflection high energy electron diffraction (RHEED).
  • the substrate is cooled to a temperature in the range of about 200-800°C, preferably 300-500°C, and a layer of a monocrystalline perovskite oxide such as strontium titanate is grown on the template layer by molecular beam epitaxy. Any of the other materials described elsewhere in this detailed description as suitable materials for the accommodating buffer layer may also be grown or deposited on the substrate.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.1-0.8nm per minute, preferably 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the stoichiometry of the oxide layer can be controlled during growth by monitoring RHEED patterns and adjusting the individual fluxes, for example, by partially shutting the appropriate shutter.
  • the ove ⁇ ressure of oxygen causes the growth of an amo ⁇ hous silicon oxide layer at the interface between the underlying substrate and the strontium titanate layer. This step may be applied either during or after the growth of the SrTiO 3 layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered (100) monocrystal with the (100) crystalline orientation rotated by 45° with respect to the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amo ⁇ hous silicon oxide intermediate layer.
  • the crystalline quality of the accommodating buffer layer, in this example SrTiO 3 is improved, in accordance with a further embodiment of the invention by forming the buffer layer by an interrupted growth process.
  • the growth of the buffer layer is initiated, stopped, and then reinitiated.
  • This interrupted growth process may be repeated more than once.
  • the quality of the growing layer can be monitored by RHEED and appropriate corrections made to the growth conditions, including the steps of repeating the interrupted process.
  • the growth process as described above, can be stopped after the growth of 2-10, and preferably after the growth of 3-5 unit cells of the buffer layer have been deposited. The process is stopped by closing the shutters on the titanium and strontium sources.
  • the partial pressure of oxygen in the apparatus can be increased or decreased depending on the indications from the RHEED measurement. For example, during the growth initiation phase the partial pressure of oxygen may be about 5x10 " -5x10 " mbar.
  • the partial pressure of oxygen may be increased to as much as about 5xl0 "7 - 10 "5 mbar or may be decreased to as little as about 10 "8 mbar.
  • the temperature of the substrate may be increase from a nominal growth temperature of 400°C to a temperature in the range of
  • the stoppage in growth may last, for example, from 10 seconds to 10 minutes. Additionally, after the initial growth of the layer having a thickness of 2-10 unit cells, the temperature and/or the pressure can be ramped as the growth of the layer continues. The temperature and pressure ranges during the ramped growth can be those described above.
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 0.5-2 monolayers of titanium, 0.5-2 monolayers of titanium-oxygen or with 0.5-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As bond.
  • gallium arsenide monocrystalline layer is subsequently introduced to the reaction with the arsenic and gallium arsenide forms.
  • gallium can be deposited on the capping layer to form a Sr-O-Ga bond, or a Ti-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
  • the template layer before growth of the GaAs layer, is enhanced by adding a wetting layer to the top thereof. Without the wetting layer, three dimensional growth of the compound semiconductor layer often occurs at the initial nucleation stage. The occurrence of three dimensional growth is due to low surface and interface energies associated with the oxide (in this example strontium titanate) surface. Oxides are typically chemically and energetically more stable than metals and most electronic materials such as GaAs. The three dimensional growth results in the spotty localized growth of discrete GaAs patches. Upon further growth the patches may grow together, but not as a monocrystalline layer.
  • a wetting layer is epitaxially grown on the upper surface of the accommodating buffer layer to raise the surface energy at the surface of the oxide layer.
  • Useful wetting agents include materials having a cubic crystalline structure selected from the group of metals, intermetallics, and metal oxides.
  • Representative materials meeting these criteria include NiAl, FeAl, CoAl, Ni, Co, Fe,
  • the selected wetting agent is deposited to a thickness of 0.5 - 5.0 monolayers on and as part of the template layer in the same process apparatus used for the deposition of the accommodating buffer layer.
  • the accommodating buffer layer is strontium titanate, barium titanate, or barium stontium titanate and the desired monocrystalline compound semiconductor layer is GaAs or AlGaAs
  • 0.5 - 5.0 monolayers of NiAl form a suitable wetting layer.
  • the deposition of the NiAl is initiated with the deposition of Ni.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention.
  • Single crystal SrTiO 3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22.
  • amo ⁇ hous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
  • GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on a structure including GaAs monocrystalline layer 26 comprising GaAs grown on silicon substrate 22 using accommodating buffer layer 24.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the additional buffer layer 32 is formed overlying the template layer before the deposition of the monocrystalline material layer.
  • the buffer layer is a monocrystalline material comprising a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template, including a wetting layer, as described above.
  • the buffer layer is a monocrystalline material layer comprising a layer of germanium
  • the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then depositing a wetting layer formed of one of the wetting agents described above.
  • the germanium buffer layer can then be deposited directly on this template/wetting layer.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amo ⁇ hous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amo ⁇ hous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amo ⁇ hous, thereby forming an amo ⁇ hous layer such that the combination of the amo ⁇ hous oxide layer and the now amo ⁇ hous accommodating buffer layer form a single amo ⁇ hous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amo ⁇ hous oxide layer, and monocrystalline layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 5 seconds to about 20 minutes.
  • a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 5 seconds to about 20 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amo ⁇ hous layer in accordance with the present invention.
  • laser annealing, electron beam annealing, or "conventional" thermal annealing processes may be used to form layer 36.
  • an ove ⁇ ressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an ove ⁇ ressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • a single crystal SrTiO 3 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amoiphous interfacial layer forms as described above.
  • additional monocrystalline layer 38 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amo ⁇ hous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including additional monocrystalline layer 38 comprising a GaAs compound semiconductor layer and amo ⁇ hous oxide layer 36 formed on silicon substrate 22.
  • the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amo ⁇ hous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCND), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PND), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • CVD chemical vapor deposition
  • MOCND metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PND physical vapor deposition
  • CSD chemical solution deposition
  • PLD pulsed laser deposition
  • alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other monocrystalline material layers comprising other HI-V, II-NI, and IV-NI monocrystalline compound semiconductors, semiconductors, metals and non-metals can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • each of the variations of monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer.
  • the accommodating buffer layer is an alkaline earth metal zirconate
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
  • hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively.
  • strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen.
  • each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • high quality two dimensional growth of the monocrystalline material layers overlying the monocrystalline oxide accommodating buffer layer can be promoted by inco ⁇ orating an appropriate wetting layer into the template layer.
  • the wetting layer deposited to a thickness of 0.5-5.0 monolayers in the same apparatus used for the deposition or growth of the monocrystalline material layer, serves to alter the surface energy of the monocrystalline oxide.
  • the accommodating buffer layer is SrTiO and the monocrystalline material layer is GaAs
  • the monocrystalline material layer is GaAs
  • a wetting agent containing template layer aids in the formation of a compliant substrate for the monolithic integration of various material layers including those comprised of Group HI-V compounds to form high quality semiconductor structures, devices and integrated circuits.
  • a wetting agent containing template may be used for the monolithic integration of a monocrystalline material layer such as a layer comprising Germanium (Ge), for example, to form high efficiency photocells.
  • FIGS. 9-12 the formation of a device structure in accordance with still another embodiment of the invention is illustrated in cross-section.
  • This embodiment utilizes the formation of a compliant substrate which relies on the epitaxial growth of single crystal oxides on silicon followed by the epitaxial growth of single crystal silicon onto the oxide.
  • An accommodating buffer layer 74 such as a monocrystalline oxide layer is first grown on a substrate layer 72, such as silicon, with an amo ⁇ hous interface layer 78 as illustrated in FIG. 9.
  • Monocrystalline oxide layer 74 may be comprised of any of those materials previously discussed with reference to layer 24 in FIGS. 1 and 2, while amo ⁇ hous interface layer 78 is preferably comprised of any of those materials previously described with reference to the layer 28 illustrated in FIGS. 1 and 2.
  • Substrate 72 although preferably silicon, may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
  • a silicon layer 81 is deposited over monocrystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like as illustrated in FIG.
  • Monocrystalline oxide layer 74 preferably has a thickness of about 2 to 10 nm.
  • Rapid thermal annealing is then conducted in the presence of a carbon source such as acetylene or methane, for example at a temperature within a range of about 800°C to 1000°C to form capping layer 82 and silicate amo ⁇ hous layer 86.
  • a carbon source such as acetylene or methane
  • other suitable carbon sources may be used as long as the rapid thermal annealing step functions to amo ⁇ hize the monocrystalline oxide layer 74 into a silicate amo ⁇ hous layer 86 and carbonize the top silicon layer 81 to form capping layer 82 which in this example would be a silicon carbide (SiC) layer as illustrated in FIG. 11.
  • the formation of amo ⁇ hous layer 86 is similar to the formation of layer 36 illustrated in FIG. 3 and may comprise any of those materials described with reference to layer 36 in FIG. 3 but the preferable material will be dependent upon the capping layer 82 used for silicon layer 81.
  • a compound semiconductor layer 96 such as gallium nitride (GaN) is grown over the SiC surface by way of MBE, CND, MOCVD, MEE, ALE, PND, CSD, PLD, or the like to form a high quality compound semiconductor material for device formation as illustrated in FIG. 12. More specifically, the deposition of Ga ⁇ and Ga ⁇ based systems such as Galn ⁇ and AlGa ⁇ will result in the formation of dislocation nets confined at the silicon/amo ⁇ hous region.
  • the resulting nitride containing compound semiconductor material may comprise elements from groups in, IN and N of the periodic table and is defect free.
  • this embodiment of the invention possesses a one step formation of the compliant substrate containing a SiC top surface and an amo ⁇ hous layer on a Si surface. More specifically, this embodiment of the invention uses an intermediate single crystal oxide layer that is amo ⁇ hized to form a silicate layer which adsorbs the strain between the layers. Moreover, unlike past use of a SiC substrate, this embodiment of the invention is not limited by wafer size which is usually less than 50mm in diameter for prior art SiC substrates.
  • nitride containing semiconductor compounds containing group Ifl-V nitrides and silicon devices can be used for high temperature and high power RF applications and optoelectronics.
  • Ga ⁇ systems have particular use in the photonic industry for the blue/green and UV light sources and detection.
  • High brightness light emitting diodes (LEDs) and lasers may also be formed within the Ga ⁇ system.
  • the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal and non-metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits.
  • a monocrystalline semiconductor or compound semiconductor wafer can be used in forming monocrystalline material layers over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for compound semiconductor devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g. conventional compound semiconductor wafers).

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Abstract

Selon l'invention, il est possible de faire croître des couches épitaxiales de qualité élevée de matériaux monocristallins (26) recouvrant des substrats monocristallins, (22) notamment des tranches semi-conductrices de grande taille, par formation d'un substrat conforme à la croissance de couches monocristallines. Une couche tampon adéquate (24) comprend une couche d'oxyde monocristallin séparée d'une tranche semi-conductrice par une couche d'interface amorphe (28) d'oxyde de silicium. La couche d'interface amorphe dissipe les contraintes et permet la croissance d'une couche tampon adéquate d'oxyde monocristallin de haute qualité. Le réseau cristallin de la couche tampon adéquate correspond à la fois à celui de la tranche semi-conductrice de silicium et à celle de la couche supérieure de matériau monocristallin. Tout défaut de correspondance de réseau cristallin entre la couche tampon adéquate et le substrat de silicium sous-jacent est pris en compte par la couche d'interface amorphe. La surface de la tranche semi-conductrice sous-jacente est préparée par croissance sélective et réduction subséquente d'un oxyde de surface, puis par reconstruction correcte de la surface de silicium par dépôt d'une couche mince d'un métal alcalino-terreux. La croissance monocristalline de la couche tampon adéquate est améliorée par une procédure de croissance interrompue.
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