+

WO2003036723A2 - Structure a semi-conducteur dotee d'un composant decouple du substrat de maniere capacitive - Google Patents

Structure a semi-conducteur dotee d'un composant decouple du substrat de maniere capacitive Download PDF

Info

Publication number
WO2003036723A2
WO2003036723A2 PCT/EP2002/009705 EP0209705W WO03036723A2 WO 2003036723 A2 WO2003036723 A2 WO 2003036723A2 EP 0209705 W EP0209705 W EP 0209705W WO 03036723 A2 WO03036723 A2 WO 03036723A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
insulating layer
layer
semiconductor structure
component
Prior art date
Application number
PCT/EP2002/009705
Other languages
German (de)
English (en)
Other versions
WO2003036723A3 (fr
Inventor
Josef Boeck
Thomas Meister
Herbert Schaefer
Reinhard Stengl
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2003036723A2 publication Critical patent/WO2003036723A2/fr
Publication of WO2003036723A3 publication Critical patent/WO2003036723A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to a semiconductor structure with a semiconductor component which is capacitively decoupled from a substrate of the semiconductor structure.
  • the increasingly higher integration density of semiconductor components in semiconductor chips has the consequence, among other things, that the semiconductor components have increasingly smaller distances from one another.
  • the capacitive coupling can take place directly within the component layer of the chip and indirectly via the underlying substrate, which generally has an electrical conductivity.
  • SOI Silicon On Insulator
  • the (silicon) component layer is electrically insulated from the substrate by an insulating layer, which is usually formed by a buried oxide layer.
  • the component is an integrated coil, its electrical quality is influenced or deteriorated by a capacitive coupling to another component.
  • the power loss is further increased by the capacitive coupling between individual components of a chip and between a component and semiconductor material that is not part of a component.
  • a requirement in the design and construction of semiconductor structures is therefore the greatest possible reduction in the capacitive coupling between the individual components.
  • Another requirement is the most effective full dissipation of power loss of the components of the semiconductor structure.
  • CMOS complementary metal oxide semiconductor
  • Examples are given in the article "Impact of 0.18 ⁇ m SOI CMOS Technology using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF / Analog Applications” by S. Maeda et al., 2000 Symposium on VLSI Technology - Digest of Technical Papers (Cat No00CH37104), pp. 154-155, and in the article “Impact of 0.10 ⁇ m SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break Through the Scaling Crisis of Silicon Technology” by Y. Hirano et al., IEDM 2000, Technical Digest (Cat. No. 00CH37138), pp. 467-470.
  • a trench or trench is a trench in a component layer, which is preferably filled with an electrically insulating material, for the isolation of two laterally adjacent regions in the component layer.
  • a partial or shallow trench or a shallow trench is a trench that does not extend to the buried oxide layer of the SOI structure, in which silicon therefore remains between the trench and the buried oxide layer.
  • An STI (shallow trench isolation) brought about by a shallow trench is thus similar to isolation by trenches on a normal bulk or bulk wafer without an SOI structure, in which a current path between two components in the wafer separated by the trench constricted and extended, but not completely interrupted.
  • the partial trench is characterized by a comparatively small etching depth which is in the range of the minimal lateral lithography resolution, for example the depth of a partial Trench typically 0.3 ⁇ m in the case of a 0.25 ⁇ m CMOS process.
  • a filling trench or a complete trench is a trench between components of a chip with an SOI structure, in which the silicon is etched or interrupted up to the buried oxide or insulator layer, so that current paths between the components are completely interrupted ,
  • a filling trench can separate larger transistor areas from one another, as is also described in the above-mentioned article by S. Maeda. Larger passive components can be arranged above a filling trench.
  • a deep trench or a deep trench is described, for example, in the article "An SOI-Based High Performance Self-Aligned Bipolar Technology Featuring 20 ps Gate Delay and a 8.6 fJ Power Delay Product" by E. Bertagnolli et al., 1993 Symposium on VLSI Technology, Digest of Technical Papers (Cat. No .: 93CH3303-5) pp. 63-64)
  • This article presents a bipolar process on SOI in which a bipolar transistor is isolated by a deep trench , which extends to the buried oxide layer of the SOI structure and has a depth-to-width ratio> 1.
  • the deep trench is not wide enough to be able to integrate passive components in their full dimensions. Rather, the deep trench is used exclusively for dielectric component isolation - the principle of the deep
  • Trench or isolation with a deep trench is in that Article "Process yields 50-MHZ op amp.”
  • a capacitive decoupling of a semiconductor component in a semiconductor structure from an underlying substrate a thick insulating layer, which is usually at least about 1 micron thick, is used, which usually consists of an oxide. Since this has a very poor specific thermal conductivity, the thick insulating layer hinders the heat dissipation of components into the substrate and thus the dissipation of power loss. This disadvantage is all the more serious the greater the integration density of components in the semiconductor structure and the faster the semiconductor structure is clocked.
  • the object of the present invention is to provide an improved semiconductor structure and a method for its production.
  • a semiconductor structure comprises a substrate, an insulating layer which is arranged on a surface of the substrate, a component layer which is arranged on a surface of the insulating layer which faces away from the substrate, a semiconductor component which is arranged in the component layer and a region for capacitive decoupling of the semiconductor component from the substrate, which is formed by a space charge zone formed in a region of the substrate adjoining the insulating layer.
  • the substrate preferably has a flat pn junction aligned parallel to the surface of the substrate.
  • the space charge zone can be generated by applying a voltage to the substrate, by means of which an inversion layer adjoining the insulating layer is also generated in the substrate.
  • the insulating layer preferably has a thickness that is less than 1 ⁇ m.
  • the thickness of the insulating layer is particularly preferably in the range from 3 nm to 400 nm, this range including all values greater than 3 nm and less than 400 nm.
  • the insulating layer preferably has a thermal resistance in the direction perpendicular to the insulating layer, which is smaller or substantially smaller than the thermal resistance of the substrate.
  • a method for producing a semiconductor structure according to the present invention comprises the following steps:
  • the present invention is based on the knowledge that the functions of electrostatic or dielectric insulation and the capacitive decoupling of a component layer and a substrate in a semiconductor structure do not require a thick insulating layer, but instead by means of a very thin insulating layer and an adjoining high-resistance layer Space charge zone can be fulfilled, wherein the insulating layer can in particular be thinner or significantly thinner than 1 ⁇ m.
  • An advantage of the present invention is that it simultaneously enables excellent capacitive decoupling of a semiconductor component in a semiconductor structure from its substrate and unhindered dissipation of heat loss from the semiconductor component into the substrate.
  • FIG. 1 shows a schematic sectional illustration of a preferred exemplary embodiment of the present invention
  • FIG. 2 shows a schematic sectional illustration of a further preferred exemplary embodiment of the present invention
  • FIG. 4 shows a diagram which shows schematically for two different substrate doping a relationship between a voltage to be applied to a substrate contact and a doping implantation dose
  • FIG. 5 shows a schematic sectional illustration of the semiconductor structure shown in FIG. 1 in a first phase during a production method according to an exemplary embodiment of the present invention
  • FIG. 6 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a second phase of the production method from FIG. 5;
  • FIG. 7 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a third phase of the production method from FIG. 5;
  • FIG. 8 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a first phase of a production method according to a further exemplary embodiment of the present invention
  • FIG. 9 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a second phase of the production method from FIG. 8;
  • FIG. 10 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a third phase of the production method from FIG. 8.
  • the semiconductor structure comprises a substrate 10 with a surface 12 on which an insulating layer 14 is arranged.
  • a component layer 18 Arranged on a surface 16 of the insulating layer 14 facing away from the substrate is a component layer 18 with a surface 20 facing away from the insulating layer 14, in which a first bipolar transistor 30a and a second bipolar transistor 30b are in turn arranged.
  • the first bipolar Transistor 30a and the second bipolar transistor 30b each have an emitter 32, a base 34 and a collector 36.
  • the second bipolar transistor 30b has the same structure as the first bipolar transistor 30a.
  • the emitter 32 adjoins the base 34 and is open on the surface 20 of the component layer 18, so that it is accessible for electrical contacting. Compared to other areas of the semiconductor structure, the emitter 32 is electrically insulated by a spacer or an emitter insulating layer 42, which surrounds it essentially in a cylindrical manner.
  • the base 34 also borders on the collector 36 and a first base contacting area 44.
  • a second base contacting area 46 extends from the surface 20 of the component layer 18 to the first base contacting area 44.
  • the collector 36 also borders on a first collector contacting area 48 which passes through a buried layer of the bipolar transistor is formed.
  • a second collector contact area 50 extends from the surface 20 of the component layer 18 to the first collector contact area 48.
  • the first and second bipolar transistors 30a, 30b are electrically isolated from one another and to the outside by electrically insulating material as follows.
  • a first component insulating layer 60 borders on the insulating layer 14 and in the lateral direction on the first collector contacting areas 48.
  • a second component insulating layer 62 borders on the first component insulating layer 60, the first collector contacting areas 48, ie the buried layer, and laterally to the second collector contact areas 50 and the collectors 36.
  • a third component insulation layer 64 borders on the second component insulation layer 62, the collectors 36 and laterally on the bases 34 and the second collector contact layers. animal regions 50.
  • a fourth component insulation layer 66 borders the third component insulation layer 64 and laterally the first base contact regions 44 and the second collector contact regions 50.
  • a fifth component insulation layer 68 borders the fourth component insulation layer 66, the first base contact regions 44 and laterally to the second base contact areas 46, the emitter insulating layers 42 and the second collector contact areas 50.
  • a substrate contact region 80 extends from the surface 20 of the component layer 18 through all component insulating layers 60 to 68 and the insulating layer 14 into the substrate 10 and is laterally spaced apart from the bipolar transistors 30a, 30b.
  • the emitters 32, the bases 34, the collectors 36, the base contact regions 44, 46 and the collector contact regions 48, 50 have doped and thus electrically conductive monocrystalline or polycrystalline silicon.
  • the emitters 32 and the collectors 36 are n-doped, the bases 34 are p-doped and the bipolar transistors 30a, 30b are thus npn-bipolar transistors.
  • the insulating layer 14, the emitter insulating layers 42 and the component insulating layers 60-68 have one or more electrically insulating materials, for example a silicon oxide or a silicon nitride, and bring about galvanic or dielectric or electrostatic insulation.
  • the emitter insulation layers 42 completely enclose the emitters 32 in the lateral direction and thus isolate them from the respectively adjacent first base contact area 44.
  • the first collector contact areas 48 and the substrate contact area 80 each adjoin the first component insulation layer 60 in the lateral direction along their entire circumference or outer edge
  • the collectors 36, the second collector contacting areas 50 and the substrate contacting area 80 each border in the lateral direction along their the entire circumference to the second component insulating layer 66.
  • the bases 34, the second collector contacting regions 50 and the substrate contacting region 80 each border in the lateral direction along the entire circumference of the third component insulating layer 64.
  • the first base contacting regions 44, the second collector contacting regions 50 and the In the lateral direction, substrate contacting regions 80 each adjoin the fourth component insulating layer 66 along their entire circumference.
  • the second base contacting regions 46, the second collector contacting regions 50 and the substrate contacting region 80 in each case adjoin the fifth component insulating layer 68 in the lateral direction along their entire circumference.
  • the collectors 36 of the bipolar transistors 30a, 30b in particular are insulated by a shallow trench or a shallow trench, which is essentially formed by the second component insulating layer 62.
  • Ccs collector-substrate capacitances are reduced.
  • the substrate 10 has p-doped silicon with a doping concentration of 10 13 cm -3 to 10 14 cm -3 and a specific resistance of 1000 ⁇ cm to 100 ⁇ cm. Interrupt areas are on the surface 12 of the substrate 10
  • a first interruption region 90a is arranged on the left in FIG. 1 on the edge of the semiconductor structure shown, a second one Interruption area 90b is between the bipolar transistors 30a, 30b is arranged, and a third interruption region 90c is arranged adjacent to the substrate contacting region 80.
  • An electrostatic potential which is independent of potentials of the bipolar transistors 30a, 30b can be applied to the substrate 10 via the substrate contacting region 80 and the third interruption region 90c.
  • Typical potential ratios are +5 V at the collector 36 and 0 V at the substrate 10.
  • a thin inversion layer 94 is formed in the substrate 10 immediately adjacent to the surface 12 and then a much thicker space charge zone 96 the concentration of the majority charge carriers (holes) is greatly reduced in relation to a region 98 of the substrate which is further away from the surface 12, so that the space charge zone 96 has an almost vanishing electrical conductivity.
  • the inversion layer 94 is produced by a movement of minority charge carriers, in the case of the p-type substrate electrons, to the interface between the insulator and the semiconductor. It has finite electrical conductivity.
  • interruption regions 90a, 90b, 90c and the inversion layer 94 are formed between the interruption regions 90a, 90b, 90c and the inversion layer 94, so that different regions of the inversion layer 94, which are spatially separated from one another by interruption regions 90a, 90b, 90c, are also electrically are isolated from each other.
  • the bipolar transistors 30a, 30b are not only completely electrically isolated from one another, but moreover are also largely capacitively decoupled.
  • One of the reasons for the extensive capacitive decoupling of the two bipolar transistors 30a, 30b from one another is that a space 102 between them is completely filled by the component insulating layers 60 to 68 and thus contains no semiconductor material which is not a necessary component one of the bipolar transistors 30a, 30b.
  • the effective distance determining the size of the capacitive coupling between them is maximally increased. Capacities between the bipolar transistors 30a, 30b or their components are therefore minimal for a given spatial arrangement.
  • a further consequence of the described construction of the component layer 18 is a reduction in parasitic currents which can be induced in semiconductor material, for example, by adjacent coils.
  • the semiconductor structure illustrated with reference to FIG. 1 has a very low capacitive coupling of each of the bipolar transistors 30a, 30b to the substrate 10 and via this to the other of the bipolar transistors 30a, 30b.
  • the semiconductor structure shown has a very good heat-conductive connection between the bipolar transistors 30a, 30b and the substrate 10.
  • an electrostatic isolation and a capacitive decoupling of components in the component layer from the substrate is brought about by a thick insulating layer between the component layer and the substrate
  • the bipolar transistors 30a, 30b or also other components in the component layer 18 capacitively decoupled from the substrate by the insulating layer 14 and the space charge zone 96 are examples of the bipolar transistors 30a, 30b or also other components in the component layer 18 capacitively decoupled from the substrate by the insulating layer 14 and the space charge zone 96.
  • the insulating layer 14 can be made so thin that it just barely fulfills the function of the electrostatic insulation.
  • a lower limit for the thickness of the insulating layer 14 is approximately 3 nm. In the case of an even thinner insulating layer, a tunnel current occurs which results in finite conductivity.
  • the thickness of the insulating layer 14 is particularly preferably in the range from 20 nm to approximately 100 nm, the thickness in particular also all Can assume values between 20 nm and 100 nm. Further preferred thicknesses of the insulating layer 14 are in the range up to approximately 400 nm.
  • the insulating layer 14 with a thickness in the range from 3 nm to 400 nm sufficiently isolates the bipolar transistors 30a, 30b from the substrate 10, at the same time it has a significantly higher thermal conductivity than an insulating layer according to the prior art. Since the oxide of the insulating layer 14 has a thermal conductivity which is approximately 100 times lower than that of silicon, the insulating layer 14 significantly influences the dissipation of power loss or of heat generated by the bipolar transistors 30a, 30b to the substrate and via this to the environment. Practice the semiconductor structure. Effective removal of waste heat generated by components is of great and increasing importance with an increasing integration density and an increasingly faster clocking of the components in modern semiconductor structures. The small thickness of the insulating layer 14 and the associated high thermal conductivity thereof are made possible in that, according to the present invention, the capacitive decoupling of the bipolar transistors from the substrate 10 is effected by the thick space charge zone 96.
  • the substrate contact 80 it is possible to determine the electrostatic potential of the inversion zone 94 or also the space charge zone 96 in the substrate 10 below the insulating layer 14.
  • an inversion layer naturally already arises under the insulating layer 14 due to positive oxide charges.
  • the first collector contact region 48 of the npn bipolar transistor 30a, 30b has a positive polarity with respect to the substrate, the formation of a space charge zone is supported , This is the deeper or thicker the higher the specific resistance of the substrate 10.
  • the thickness of the space charge zone 96 below the inversion layer 94 about 9 microns. This corresponds to an effective thickness of the insulating layer 14 of approximately 3 ⁇ m.
  • the inversion layer 94 at the interface or surface 12 of the substrate 10 to the insulating layer 14 has a finite sheet resistance which is generally greater than approximately 10 k ⁇ / D, as described, for example, in the article “Modeling and Measurement of Substrate Coupling in Si-Bipolar IC s up to 40 GHz "by M. Pfost et al., IEEE Journal of Solid State Circuits, Vol. 33, No. 4, April 1998, pp.
  • the inversion layer 94 is interrupted by the interruption areas or channel stops 90a, 90b, 90c, the interruption areas the bipolar transistors 30a, 30b or sections 94a, 94b of the inversion layer 94 lying underneath the same, preferably laterally completely enclose and electrically isolate them from one another This condition does not result in indirect coupling between the bipolar transistors 30a, 30b.
  • the interruption or insulation effect of the interruption regions 90a, 90b, 90c is based on the fact that they each form two pn junctions connected to one another with respect to the inversion layer 94, of which one always depends on the potential difference between the different sections 94a, 94b of the inversion layer 94 Is blocked.
  • the interruption regions 90a, 90b, 90c in the direction perpendicular to the surface 12 of the substrate 10 must have a thickness which is greater than the thickness of the inversion layer 94. Since the layer resistance of the interruption regions 90a, 90b, 90c with approximately 600 ⁇ / D (see the above-mentioned article by M.
  • the interruption regions 90a, 90b, 90c point laterally in the direction from one section 94a to the other section 94b of the inversion layer 94 preferably has the smallest possible width.
  • a typical doping density of the interruption regions 90a, 90b, 90c is 2 x 10 17 cm "3 .
  • FIG. 2 is a schematic sectional illustration of a further exemplary embodiment of a semiconductor structure according to the present invention.
  • the semiconductor structure shown in FIG. 2 differs from that shown in FIG. 1 in that the substrate 10 has an n-doped region 110 which is adjacent to the surface 12 of the substrate and thus to the insulating layer 14 and the substrate contacting region 80.
  • a voltage of approximately 5 V is preferably applied to the substrate contact 80 and to the collectors 36 of the bipolar transistors 30a, 30b with respect to the substrate 10 or the region 98 of the substrate 10.
  • the n-doped region 110 of the substrate 10 is blocked with respect to the region 98 of the substrate 10, and a space charge zone 96 is formed in the substrate 10.
  • This space charge zone 96 fulfills the same function as the space charge zone 96 in that shown in FIG. 1 Embodiment, namely the capacitive decoupling of the component layer 18 or the bipolar transistors 30a, 30b in the component layer 18 from the substrate 10 or the region 98 in which the substrate is conductive.
  • the embodiment shown in FIG. 2 has no inversion layer 94.
  • the N layer or N well or the n-doped region 110 is formed by implanting an n-doping in the originally p-doped substrate.
  • the implantation dose and thus the doping density in the n-doped region 110 is to be selected such that the n-doped region 110 is completely cleared of the voltage applied to the substrate contacting region 80 or has a minimal charge carrier density and the high-impedance space charge zone 96 through the n-doped region 110 extends right up to the insulating layer 14 or adjacent to this.
  • a typical doping concentration is 10 15 cm "3.
  • p + -doped channel stops or interruption regions 90a, 90c are only required and provided at the edge of the chip in order to delimit the space charge zone 96 in a controlled manner or define their edge.
  • the capacitance between the bipolar transistors 30a, 30b and the substrate or its region 98 outside the space charge zone 96 can practically disappear to be brought.
  • a space charge zone 96 of almost 50 ⁇ m thickness at a voltage of 20 V is possible to create.
  • the pn junction formed by the n-doped region 110 and the rest of the substrate 10 does not have to be fully polarized in the reverse direction, but is sufficient if it is in the region and is blocked in the vicinity of the bipolar transistor.
  • FIG. 3 is a schematic sectional illustration of three variants of the design or the spatial extent of the n-doped region 110 in the substrate 10, only the substrate 10 with the interruption regions 90a, 90c and the one-part or multi-part n-doped region 110 in each case and the insulating layer 14 and a section 120 of the component layer 18 are shown.
  • the section 120 of the component layer 18 shown represents a section in or on the component, for example that in FIGS. 1 and 2
  • the bipolar transistors 30a, 30b shown are formed or are formed in a later phase of the production process.
  • the n-doped region 110 is continuous between the interruption regions 90a, 90c and thus has the shape already shown in FIG. 2.
  • Such an n-doped region 110 is preferably formed by implanting the n-doping in the substrate 10 before the section 120 is applied, it being possible for the implantation to be carried out easily through the thin insulating layer 14 already applied.
  • FIG. 3b shows a variant in which the n-doped region 110 was only produced by implantation after the section 120 had been formed on the insulating layer 14.
  • the section 120 is protected during the implantation of the n-doping by a protective layer (not shown) on its surface 122 facing away from the insulating layer 14.
  • the implantation does not have to take place homogeneously within the n-doped region 110, as shown in FIG. 3b, but can also be carried out, for example, by means of a grating mask which reduces the mean implantation dose and results in a spatially variable doping concentration or an inhomogeneously n-doped Area 110 leads as shown in FIG. 3c.
  • the lateral dimensions of section 120 are not much larger than the typical space charge zone width, the one shown is formed by diffusion of the doping atoms into edge regions under section 120 and, above all, by diffusion of charge carriers
  • Space charge zone 96 which also extends completely below section 120 in FIGS. 3b and 3c and fulfills the function described with reference to FIGS. 1 and 2.
  • the diffusion regions of the doping atoms need not overlap, but only the space charge zones generated by all parts of the n-doped region 110.
  • An application of this knowledge is described in the following.
  • implantation doses larger than or equal to 1 x 10 11 cm "2 are used.
  • FIG. 4 is a schematic representation of a relationship between the voltage of the substrate contacting region 80 with respect to the substrate 10 and the dose to be implanted into the substrate 10 to form the n-doped region 110 under the boundary condition that the space charge zone 96 generated by the voltage borders directly on the insulating layer 14.
  • This relationship is for a substrate with a basic doping concentration of 1 x 10 13 cm “3 (specific resistance approx. 1000 ⁇ cm; curve 124) and for a substrate with a basic doping concentration of 1 x 10 14 cm “ 3 (specific resistance approx. 100 ⁇ cm; curve 126).
  • the more the n-doped region 110 is doped the greater the voltage of the substrate contacting region 80 with respect to the substrate if the high-resistance space charge zone is to connect directly to the insulating layer 14.
  • the smaller the implantation dose used for doping the n-doped region 110 the lower voltages between the substrate contact region 80 and the substrate 10 are sufficient to create a space charge zone which extends directly to the insulating layer 14.
  • the semiconductor structure shown in FIG. 1 is shown in different phases of a manufacturing method according to an embodiment of the present invention.
  • the manufacturing method shown is based on an SOI structure in which there is the insulating layer 14 on the substrate 10 and a monocrystalline silicon layer thereon, in which the first collector contact areas 48 are later formed.
  • the interruption areas 90a, 90b, 90c have already been introduced into the substrate 10 and the insulating layer 14 has been produced on the surface 12.
  • An n + -doped buried layer or buried layer with a thickness of 600 nm and a doping concentration of approximately 10 ⁇ 10 20 cm 3 was produced in the silicon layer of the SOI structure on the surface 16 of the insulating layer 14 facing away from the substrate 10 , which later forms the first collector contact areas 48.
  • the n + -doped buried layer has already been structured laterally by etching in Fig. 5.
  • the first base contact regions 44 each contain a hole 134 which extends to the base 34.
  • the second, third and fourth component insulating layers 62, 64, 66 have holes 150 which extend to the first collector contact areas 48.
  • the first, second, third and fourth component insulating layers 60, 62, 64, 66 and the insulating layer 14 have a hole 180 which extends up to the surface 12 of the substrate 10 or at that point below the surface 12 interruption area 90c reached.
  • the holes 134, 150, 180 are filled with monocrystalline or polycrystalline semiconductor material in the following method steps in order to form the emitters 32, the second collector contacting regions 50 and the substrate contacting region 80.
  • the first base contact region 44 has p + -doped polycrystalline semiconductor material and is in each case in
  • the base contact regions 44 are now except in the vicinity of the bases 34 in capacitively decoupled areas with thick dielectric insulation.
  • the p + -doped polycrystalline semiconductor material is a material that is also used for passive integrated resistors.
  • FIGS. 8, 9 and 10 show different phases in a method for producing the semiconductor structure according to the invention Use of a full-surface collector epitaxy and two CMP steps, whereby this method also starts from an SOI structure.
  • FIG. 8 shows a state of the semiconductor structure according to the invention shown in FIG. 1, in which the insulating layer 14 and the interruption regions 90a, 90b, 90c on or below the surface 12 of the substrate 10 and a silicon layer on the surface 16 of the insulating layer 14 ge - were formed.
  • An n + doping was diffused over the entire surface of the silicon layer in order to form the buried layer, which will later form the first collector contacting regions 48.
  • a silicon layer was epitaxially applied to the buried layer, which will later form the collectors 36. Both layers were structured together by photolithography and anisotropic etching, deep trenches or filling trenches 130 being produced which extend in the vertical direction to the surface 16 of the insulating layer 14. The state thus generated is shown in Fig. 8.
  • FIG. 9 it can be seen that the complete trenches 130 are filled with an oxide in a subsequent process step, which oxide forms the first and second component insulating layers 60, 62.
  • a flat surface 182 of the collectors 36 and the oxide is formed in a CMP step.
  • FIG. 10 shows a state of the semiconductor structure according to the invention in which, starting from the state shown in FIG. 9, edge regions 184 of the collectors 36 and the first collector contact regions 48 have been structured by etching in order to reduce the lateral expansion of the collectors 36.
  • a further oxide layer 186 was then applied, which forms parts of the second component insulation layer 62 and the third component insulation layer 64.
  • the trenches 184 represent shallow trenches.
  • a second CMP step follows for planarization of the surface 188 of the oxide layer 186 facing away from the substrate 10, after essentially the same structure as that shown in FIG. 6 is present.
  • the method is to avoid side wall defects which can arise during the selective epitaxy of the collectors 36.
  • a disadvantage is that two planarization steps are necessary.
  • the electrically insulating material surrounding the bipolar transistors instead of the layers shown in FIGS. 1 and 2 can also have a different (layer) structure, as long as it does Gap 102 completely fills up between the bipolar transistors 30a, 30b.
  • the semiconductor structure according to the invention can also have reversed doping signs, ie pnp bipolar transistors on an essentially n-doped substrate. In this case, the signs of all other doping must also be reversed.
  • An important aspect of the present invention is that the bipolar transistors 30a, 30b are completely surrounded and separated from each other by insulating material and that no further semiconductor material is arranged in the space 102 between the bipolar transistors 30a, 30b.
  • this requirement is to be restricted if components of the two bipolar transistors 30a, 30b are short-circuited to one another directly via semiconductor material.
  • the space 102 from the region in which the bipolar transistors 30a, 30b are short-circuited to one another is completely filled with insulating material.
  • the semiconductor structure according to the invention can have one or more other arbitrary active or passive semiconductor components instead of two bipolar transistors 30a, 30b.
  • the present invention is therefore not limited to bipolar technology, but can equally well be applied to CMOS technology, BiCMOS technology, etc. LIST OF REFERENCE NUMBERS
  • first component insulation layer 62 second component insulation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Structure à semi-conducteur qui comporte un substrat (10), une couche d'isolation (14) placée sur une surface (12) du substrat (10), une couche (18) pour composants placée sur une surface (16) de la couche d'isolation (14) opposée au substrat (14), un composant semi-conducteur (30a, 30b) placé dans la couche (18) pour composants et une zone destinée au découplage capacitif du composant semi-conducteur (30a, 30b) par rapport au substrat (10), ladite zone étant formée par une zone de charge d'espace (96) formée dans une région du substrat (10) adjacente à la couche d'isolation (14).
PCT/EP2002/009705 2001-10-17 2002-08-30 Structure a semi-conducteur dotee d'un composant decouple du substrat de maniere capacitive WO2003036723A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10151132.9 2001-10-17
DE10151132A DE10151132A1 (de) 2001-10-17 2001-10-17 Halbleiterstruktur mit einem von dem Substrat kapazitiv entkoppelten Bauelementen

Publications (2)

Publication Number Publication Date
WO2003036723A2 true WO2003036723A2 (fr) 2003-05-01
WO2003036723A3 WO2003036723A3 (fr) 2003-10-23

Family

ID=7702731

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/009705 WO2003036723A2 (fr) 2001-10-17 2002-08-30 Structure a semi-conducteur dotee d'un composant decouple du substrat de maniere capacitive

Country Status (2)

Country Link
DE (1) DE10151132A1 (fr)
WO (1) WO2003036723A2 (fr)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371401A (en) * 1992-08-31 1994-12-06 Hitachi, Ltd. Semiconductor integrated circuit fully isolated from the substrate
US5624854A (en) * 1992-09-02 1997-04-29 Motorola Inc. Method of formation of bipolar transistor having reduced parasitic capacitance
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
US5994759A (en) * 1998-11-06 1999-11-30 National Semiconductor Corporation Semiconductor-on-insulator structure with reduced parasitic capacitance
FR2779869A1 (fr) * 1998-06-15 1999-12-17 Commissariat Energie Atomique Circuit integre de type soi a capacite de decouplage, et procede de realisation d'un tel circuit
US6084270A (en) * 1997-03-28 2000-07-04 Nec Corporation Semiconductor integrated-circuit device having n-type and p-type semiconductor conductive regions formed in contact with each other
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6215155B1 (en) * 1997-12-19 2001-04-10 Advanced Micro Devices, Inc. Silicon-on-insulator configuration which is compatible with bulk CMOS architecture
US20010008284A1 (en) * 1999-08-31 2001-07-19 Feng-Yi Huang Silicon-germanium BiCMOS on SOI

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4441724A1 (de) * 1994-11-23 1996-05-30 Siemens Ag SOI-Substrat

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371401A (en) * 1992-08-31 1994-12-06 Hitachi, Ltd. Semiconductor integrated circuit fully isolated from the substrate
US5624854A (en) * 1992-09-02 1997-04-29 Motorola Inc. Method of formation of bipolar transistor having reduced parasitic capacitance
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6084270A (en) * 1997-03-28 2000-07-04 Nec Corporation Semiconductor integrated-circuit device having n-type and p-type semiconductor conductive regions formed in contact with each other
US6215155B1 (en) * 1997-12-19 2001-04-10 Advanced Micro Devices, Inc. Silicon-on-insulator configuration which is compatible with bulk CMOS architecture
FR2779869A1 (fr) * 1998-06-15 1999-12-17 Commissariat Energie Atomique Circuit integre de type soi a capacite de decouplage, et procede de realisation d'un tel circuit
US5994759A (en) * 1998-11-06 1999-11-30 National Semiconductor Corporation Semiconductor-on-insulator structure with reduced parasitic capacitance
US20010008284A1 (en) * 1999-08-31 2001-07-19 Feng-Yi Huang Silicon-germanium BiCMOS on SOI

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BURGHARTZ J N ET AL: "A LOW-CAPACITANCE BIPOLAR/BICMOS ISOLATION TECHNOLOGY, PART 1- CONCEPT, FABRICATION PROCESS, AND CHARACTERIZATION" IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, Bd. 41, Nr. 8, 1. August 1994 (1994-08-01), Seiten 1379-1386, XP000483758 ISSN: 0018-9383 *

Also Published As

Publication number Publication date
DE10151132A1 (de) 2003-05-08
WO2003036723A3 (fr) 2003-10-23

Similar Documents

Publication Publication Date Title
DE102009049774B4 (de) BiCMOS-Schaltungsanordnung
DE3587255T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit einer Wanne, z.B. einer komplementären Halbleiteranordnung.
EP2100330B1 (fr) Dispositif semi-conducteur bipolaire complementaire et methode de fabrication
DE10250832B4 (de) MOS-Transistor auf SOI-Substrat mit Source-Durchkontaktierung und Verfahren zur Herstellung eines solchen Transistors
DE102007006853B4 (de) ESD-Schutzvorrichtung und elektrische Schaltung mit derselben
DE3686490T2 (de) Halbleiterstruktur.
DE69330298T2 (de) Multifunktionale elektronische Vorrichtung, insbesondere Element mit dynamischem, negativem Widerstandsverhalten und Zugehöriges Herstellungsverfahren
EP1692720B1 (fr) Dispositif semi-conducteur bipolaire complementaire
EP1631990B1 (fr) Procede de fabrication d'un transistor a effet de champ
DE102021201635A1 (de) Halbleitervorrichtung mit Vertikalem DMOS und Herstellungsverfahren derselben
EP0687013A1 (fr) Transistor bipolaire et procédé de fabrication
DE102020133745A1 (de) Integrierte schaltung mit pn-übergang und vertikal ausgerichtetem feldeffekttransistor und verfahren zur herstellung von selbigem
EP1415339B1 (fr) Procede de production parallele d'un transistor mos et d'un transistor bipolaire
DE19824242A1 (de) Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung
DE10250204B4 (de) Verfahren zur Herstellung von Kollektorbereichen einer Transistorstruktur
DE102004002181B4 (de) Integrierter Transistor, insbesondere für Spannungen größer 40 Volt, und Herstellungsverfahren
DE3688030T2 (de) Bipolare integrierte schaltung mit isolationsstruktur und substratkontakt und verfahren zur herstellung.
EP1436840B1 (fr) Structure a semi-conducteur a couplage capacitif reduit entre des composants
DE69324911T2 (de) Halbleiterbauelement mit hoher Spannungsfestigkeit und dielektrischer Isolierung
WO2003036723A2 (fr) Structure a semi-conducteur dotee d'un composant decouple du substrat de maniere capacitive
WO2007137729A2 (fr) Procédé de réalisation d'un ensemble semi-conducteur, ensemble semi-conducteur et son utilisation
EP0981833B1 (fr) Configuration de circuit cmos integre et mode de fabrication
DE10038955C2 (de) Verfahren zur Herstellung eines Bipolartransistors
DE102007041407A1 (de) Verfahren zur Herstellung einer Halbleiteranordnung, Verwendung einer Grabenstruktur und Halbleiteranordnung
DE102004055213B4 (de) Verfahren zur Herstellung einer integrierten Schaltung auf einem Halbleiterplättchen

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载