+

WO2003034492A3 - Apparatus and methods for semiconductor ic failure detection - Google Patents

Apparatus and methods for semiconductor ic failure detection Download PDF

Info

Publication number
WO2003034492A3
WO2003034492A3 PCT/US2002/033154 US0233154W WO03034492A3 WO 2003034492 A3 WO2003034492 A3 WO 2003034492A3 US 0233154 W US0233154 W US 0233154W WO 03034492 A3 WO03034492 A3 WO 03034492A3
Authority
WO
WIPO (PCT)
Prior art keywords
test structure
voltage
substructures
voltage contrast
large conductive
Prior art date
Application number
PCT/US2002/033154
Other languages
French (fr)
Other versions
WO2003034492A8 (en
WO2003034492A2 (en
Inventor
Kurt H Weiner
Gaurav Verma
Original Assignee
Kla Tencor Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/264,625 external-priority patent/US7067335B2/en
Priority claimed from US10/265,051 external-priority patent/US6995393B2/en
Application filed by Kla Tencor Tech Corp filed Critical Kla Tencor Tech Corp
Priority to JP2003537118A priority Critical patent/JP4505225B2/en
Publication of WO2003034492A2 publication Critical patent/WO2003034492A2/en
Publication of WO2003034492A3 publication Critical patent/WO2003034492A3/en
Publication of WO2003034492A8 publication Critical patent/WO2003034492A8/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

An improved voltage contrast test structure (100, 200, 250, 300) is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures (102, 104, 202, 204, 252, 254, 302, 304) which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures (102, 202, 252, 302) are coupled to a relatively large conductive structure (110, 210, 260, 302, 308), such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.
PCT/US2002/033154 2001-10-17 2002-10-16 Apparatus and methods for semiconductor ic failure detection WO2003034492A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003537118A JP4505225B2 (en) 2001-10-17 2002-10-16 Apparatus and method for semiconductor IC defect detection

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US32980401P 2001-10-17 2001-10-17
US60/329,804 2001-10-17
US10/265,051 2002-10-02
US10/264,625 US7067335B2 (en) 2000-08-25 2002-10-02 Apparatus and methods for semiconductor IC failure detection
US10/264,625 2002-10-02
US10/265,051 US6995393B2 (en) 2000-08-25 2002-10-02 Apparatus and methods for semiconductor IC failure detection

Publications (3)

Publication Number Publication Date
WO2003034492A2 WO2003034492A2 (en) 2003-04-24
WO2003034492A3 true WO2003034492A3 (en) 2003-07-10
WO2003034492A8 WO2003034492A8 (en) 2003-11-13

Family

ID=27401722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/033154 WO2003034492A2 (en) 2001-10-17 2002-10-16 Apparatus and methods for semiconductor ic failure detection

Country Status (2)

Country Link
JP (1) JP4505225B2 (en)
WO (1) WO2003034492A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
US9805994B1 (en) 2015-02-03 2017-10-31 Pdf Solutions, Inc. Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
US9799575B2 (en) 2015-12-16 2017-10-24 Pdf Solutions, Inc. Integrated circuit containing DOEs of NCEM-enabled fill cells
US10593604B1 (en) 2015-12-16 2020-03-17 Pdf Solutions, Inc. Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
US10978438B1 (en) 2015-12-16 2021-04-13 Pdf Solutions, Inc. IC with test structures and E-beam pads embedded within a contiguous standard cell area
US9653446B1 (en) 2016-04-04 2017-05-16 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells
US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US9905553B1 (en) 2016-04-04 2018-02-27 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268717B1 (en) * 1999-03-04 2001-07-31 Advanced Micro Devices, Inc. Semiconductor test structure with intentional partial defects and method of use
US6452412B1 (en) * 1999-03-04 2002-09-17 Advanced Micro Devices, Inc. Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144901A (en) * 1991-11-21 1993-06-11 Oki Electric Ind Co Ltd Detection of defective point of device having fine pattern
JP3356056B2 (en) * 1998-05-15 2002-12-09 日本電気株式会社 Wiring fault detecting circuit, wiring fault detecting semiconductor wafer, and wiring fault detecting method using the same
JP3708763B2 (en) * 1999-08-31 2005-10-19 株式会社東芝 Defect detection method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268717B1 (en) * 1999-03-04 2001-07-31 Advanced Micro Devices, Inc. Semiconductor test structure with intentional partial defects and method of use
US6452412B1 (en) * 1999-03-04 2002-09-17 Advanced Micro Devices, Inc. Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography

Also Published As

Publication number Publication date
WO2003034492A8 (en) 2003-11-13
JP4505225B2 (en) 2010-07-21
JP2005519260A (en) 2005-06-30
WO2003034492A2 (en) 2003-04-24

Similar Documents

Publication Publication Date Title
WO2003034492A3 (en) Apparatus and methods for semiconductor ic failure detection
US7067335B2 (en) Apparatus and methods for semiconductor IC failure detection
US6995393B2 (en) Apparatus and methods for semiconductor IC failure detection
US6452412B1 (en) Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography
US6236222B1 (en) Method and apparatus for detecting misalignments in interconnect structures
US9213060B2 (en) Probe-able voltage contrast test structures
US7486097B2 (en) Proximity sensitive defect monitor
US6268717B1 (en) Semiconductor test structure with intentional partial defects and method of use
EP0334680A3 (en) Mask repair system
JP2005519260A5 (en)
DE102019201202B4 (en) Method of improving heterodyne performance in semiconductor devices
Halder et al. Inspection challenges for triple patterning at sub-14 nm nodes with broadband plasma inspection platforms
DE10010285A1 (en) Test structure with integrated semiconductor
US7160650B2 (en) Method of inspecting a mask
Okoroanyanwu et al. Assessing EUV mask defectivity
TW558785B (en) New application of electron microscope and contact formation method using the electron microscope
Patterson et al. Voltage contrast inspection methodology for inline detection of missing spacer and other nonvisual defects
US6741733B1 (en) Drawing pattern verifying method
TW200839428A (en) Lithography method for forming a circuit pattern
US5614420A (en) Method of preventing mask tone error
Hendricks et al. Characterization of a new automated electron-beam wafer inspection system
US6068955A (en) Methods of inspecting for mask-defined, feature dimensional conformity between multiple masks
KR100524626B1 (en) A semiconductor mask where other layers are overlapped and its design method
Longo et al. An evaluation of X-ray lithography using a 0.175/spl mu/m (0.245/spl mu/m/sup 2/cell area) 1 Gb DRAM technology
Keil et al. Design verification for sub 70 nm DRAM nodes via metal fix using e-beam direct write

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

WR Later publication of a revised version of an international search report
WWE Wipo information: entry into national phase

Ref document number: 2003537118

Country of ref document: JP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载