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WO2003034201A3 - Late resolving instructions - Google Patents

Late resolving instructions Download PDF

Info

Publication number
WO2003034201A3
WO2003034201A3 PCT/GB2002/004555 GB0204555W WO03034201A3 WO 2003034201 A3 WO2003034201 A3 WO 2003034201A3 GB 0204555 W GB0204555 W GB 0204555W WO 03034201 A3 WO03034201 A3 WO 03034201A3
Authority
WO
WIPO (PCT)
Prior art keywords
instructions
pipelines
late
control transfer
subsequent
Prior art date
Application number
PCT/GB2002/004555
Other languages
French (fr)
Other versions
WO2003034201A2 (en
Inventor
Nigel Peter Topham
Nicholas Paul Joyce
Original Assignee
Siroyan Ltd
Nigel Peter Topham
Nicholas Paul Joyce
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0124557A external-priority patent/GB2380828A/en
Application filed by Siroyan Ltd, Nigel Peter Topham, Nicholas Paul Joyce filed Critical Siroyan Ltd
Priority to AU2002329475A priority Critical patent/AU2002329475A1/en
Publication of WO2003034201A2 publication Critical patent/WO2003034201A2/en
Publication of WO2003034201A3 publication Critical patent/WO2003034201A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Techniques are disclosed for handling control transfer instructions in parallel pipelined processors. Such instructions may cause the sequence of subsequent instructions to change, and thus may require subsequent instructions to be deleted from the processor's pipelines. The deletion of subsequent instructions from the pipelines is delayed until the control transfer instruction is in a pipeline stage in which corresponding instructions in different pipelines are aligned with each other. This may allow the mechanism required to delete unwanted instructions to be simplified.
PCT/GB2002/004555 2001-10-12 2002-10-07 Late resolving instructions WO2003034201A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002329475A AU2002329475A1 (en) 2001-10-12 2002-10-07 Late resolving instructions

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0124557A GB2380828A (en) 2001-10-12 2001-10-12 Simplified method of deleting unwanted instructions in a pipeline processor
GB0124557.0 2001-10-12
US33824101P 2001-12-06 2001-12-06
US60/338,241 2001-12-06

Publications (2)

Publication Number Publication Date
WO2003034201A2 WO2003034201A2 (en) 2003-04-24
WO2003034201A3 true WO2003034201A3 (en) 2003-11-27

Family

ID=26246652

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/004555 WO2003034201A2 (en) 2001-10-12 2002-10-07 Late resolving instructions

Country Status (2)

Country Link
AU (1) AU2002329475A1 (en)
WO (1) WO2003034201A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7370136B2 (en) * 2005-01-26 2008-05-06 Stmicroelectronics, Inc. Efficient and flexible sequencing of data processing units extending VLIW architecture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0649086A1 (en) * 1993-10-18 1995-04-19 Cyrix Corporation Microprocessor with speculative execution
US5450556A (en) * 1990-09-05 1995-09-12 North American Philips Corporation VLIW processor which uses path information generated by a branch control unit to inhibit operations which are not on a correct path
US6055626A (en) * 1996-05-30 2000-04-25 Matsushita Electric Industrial Co., Ltd. Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control
GB2343973A (en) * 1998-02-09 2000-05-24 Mitsubishi Electric Corp Delayed execution of conditional instructions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450556A (en) * 1990-09-05 1995-09-12 North American Philips Corporation VLIW processor which uses path information generated by a branch control unit to inhibit operations which are not on a correct path
EP0649086A1 (en) * 1993-10-18 1995-04-19 Cyrix Corporation Microprocessor with speculative execution
US6055626A (en) * 1996-05-30 2000-04-25 Matsushita Electric Industrial Co., Ltd. Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control
GB2343973A (en) * 1998-02-09 2000-05-24 Mitsubishi Electric Corp Delayed execution of conditional instructions

Also Published As

Publication number Publication date
AU2002329475A1 (en) 2003-04-28
WO2003034201A2 (en) 2003-04-24

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