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WO2003034200A1 - Compteur parallele et circuit logique executant une multiplication - Google Patents

Compteur parallele et circuit logique executant une multiplication Download PDF

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Publication number
WO2003034200A1
WO2003034200A1 PCT/GB2001/004455 GB0104455W WO03034200A1 WO 2003034200 A1 WO2003034200 A1 WO 2003034200A1 GB 0104455 W GB0104455 W GB 0104455W WO 03034200 A1 WO03034200 A1 WO 03034200A1
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WIPO (PCT)
Prior art keywords
logic
binary
inputs
logic circuit
outputs
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PCT/GB2001/004455
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English (en)
Inventor
Dmitriy Rumynin
Sunil Talwar
Peter Meulemans
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Arithmatica Limited
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Publication date
Application filed by Arithmatica Limited filed Critical Arithmatica Limited
Publication of WO2003034200A1 publication Critical patent/WO2003034200A1/fr
Priority to US10/817,752 priority Critical patent/US20050021585A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Definitions

  • the present invention generally relates to digital electronic devices and more particularly to a digital electronic device performing binary logic.
  • the present invention relates to a parallel counter and in another aspect the present invention relates to a logic circuit which implements the multiplication of binary numbers.
  • a full adder is a special parallel counter with a three-bit input and a two-bit output.
  • a current implementation of higher parallel counters i.e. with a bigger number of inputs is based on using full adders (C. C. Foster and F. D. Stockton, Counting Responders in an Associative Memory, IEEE Trans. Comput. C-20: 1580-1583 (1971)) (the content of which is hereby incorporated by reference).
  • the least significant bit of an output is the fastest bit to produce in such implementation while other bits are usually slower.
  • a full adder denoted FA, is a three-bit input parallel counter shown in figure 1. It has three inputs X ls X 2 , X 3 , and two outputs S and C. Logical expressions for outputs are
  • a half adder denoted HA, is a two bit input parallel counter shown in figure 1. It has two inputs Xi, X 2 and two outputs S and C. Logical expressions for outputs are
  • Multiplication is a fundamental operation. Given two n-digit binary numbers
  • P 2n- ,2 2n'1 +P 2n-2 2 2n - 2 +...+P ⁇ 2+Po may have up to 2n digits.
  • Logical circuits generating all Pj as outputs generally follow the scheme in figure 14.
  • Wallace has invented the first fast architecture for a multiplier, now called the Wallace-tree multiplier (Wallace, C. S., A Suggestion for a Fast Multiplier, IEEE Trans. Electron. Comput. EC-13: 14-17 (1964)) (the content of which is hereby incorporated by reference).
  • Dadda has investigated bit behaviour in a multiplier (L. Dadda, Some Schemes for Parallel Multipliers, Alta Freq 34: 349-356 (1965)) (the content of which is hereby incorporated by reference). He has constructed a variety of multipliers and most parallel multipliers follow Dadda' s or Wallace's scheme.
  • Dadda' s multiplier uses the scheme in on figure 22. If inputs have 8 bits then 64 parallel AND gates generate an array shown in figure 23. The AND gate sign ⁇ is omitted for clarity so that A, ⁇ BJ becomes AjBj.
  • the rest of figure 23 illustrates array reduction that involves full adders (FA) and half adders (HA). Bits from the same column are added by half adders or full adders. Some groups of bits fed into a full adder are in rectangles. Some groups of bits fed into a half adder are in ovals.
  • the result of array reduction is just two binary numbers to be added at the last step. One adds these two numbers by one of the fast addition schemes, for instance, conditional adder or carry-look-ahead adder.
  • the present invention provides a parallel counter based on algebraic properties of elementary symmetric functions.
  • Each of the plurality of binary output bits is generated as an elementary symmetric function of a plurality of binary input bits.
  • the elementary symmetric functions comprise logically AND combining sets of one or more binary inputs and logically OR or exclusive OR logic combining the logically combined sets of binary inputs to generate a binary output.
  • the OR and the exclusive OR symmetric functions are elementary symmetric functions and the generated output binary bit depends only on the number of high inputs among the input binary bits. For the OR symmetric function, if the number of high inputs is m, the output is high if and only if m >k, where k is the size of the sets of binary inputs. Similarly, the generated output binary bit using the exclusive OR symmetric function is high if and only if m >k and the number of subsets of inputs of the set of high inputs is an odd number. In one embodiment the size of the sets can be selected.
  • the i th output bit can be generated using the symmetric function using exclusive OR logic by selecting the set sizes to be of size 2 1 , where i is an integer from 1 to N, N is the number of binary outputs, and i represents the significance of each binary output.
  • the sets of binary inputs used in the elementary symmetric functions are each unique and they cover all possible combinations of binary inputs.
  • the logic circuit is divided into a plurality of logic units.
  • Each logic unit is arranged to generate logic unit binary outputs as a symmetric function of the binary inputs to the logic unit.
  • the binary inputs are divided into inputs into a plurality of the logic units, and the binary outputs are generated using binary outputs of a plurality of the logic units.
  • This embodiment reduces the amount of fan-out in the circuit and increases the amount of logic sharing. It thus makes parallel counters for a large binary number more practicable.
  • the logic circuit is divided into a plurality of logic units arranged hierarchically. Each logic unit is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic unit.
  • Logic units at the or each lower level of the hierarchy are included in the logic of logic units at the or each higher level in the hierarchy and have more inputs.
  • the logic and inputs of the parallel counter are divided in accordance with a binary tree.
  • the logic circuit is divided into a plurality of logic units. Each logic unit is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic unit.
  • the binary inputs are divided into inputs into the plurality of logic units, and the binary outputs of the plurality of outputs are generated using binary outputs of a plurality of the logic units.
  • each of the logic units is arranged to receive 2 n of the binary inputs, where n is an integer indicating the level of the logic units in the binary tree, the logic circuit has m logic units at each level, where m is a rounded up integer determined from (the number of binary inputs)/ 2 n , logic units having a higher level in the binary tree comprise logic of logic units at lower levels in the binary tree, and each logic unit is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic unit.
  • each logic unit at the first level is arranged to generate logic unit binary outputs as a smallest elementary symmetric function of the binary inputs to said logic circuit.
  • each logic unit at the first level is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic circuit using OR logic for combining the binary inputs.
  • each logic unit at the first level is arranged to logically AND each of the binary inputs to the logic unit and to logically OR each of the binary inputs to the logic unit to generate the logic unit binary outputs.
  • each logic unit at the first level is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic circuit using exclusive OR logic for combining the binary inputs.
  • each logic unit at the first level is arranged to logically AND each of the binary inputs to the logic unit and to logically exclusively OR each of the binary inputs to the logic unit to generate the logic unit binary outputs.
  • elementary logic units are provided as the logic units at the first level for performing elementary symmetric functions, outputs from each of two primary elementary logic units receiving four logically adjacent binary inputs from said plurality of inputs are input to two secondary elementary logic units, an output from each of the secondary elementary logic units is input to a tertiary elementary logic unit, and the primary, secondary and tertiary elementary logic units form a secondary logic unit at a second level of the binary tree having a binary output comprising a binary output from each of the secondary elementary logic units and two binary outputs from the tertiary elementary logic unit.
  • tertiary logic units at a third level of the binary tree each comprise two secondary logic units receiving eight logically adjacent binary inputs from the plurality of inputs, four elementary logic units receiving as inputs the outputs of the two secondary logic units, and further logic for generating binary outputs as an elementary symmetric function of the binary inputs to the tertiary logic unit using the binary outputs of the four elementary logic units.
  • quaternary logic units at a fourth level of the binary tree each comprise two tertiary logic units receiving sixteen logically adjacent binary inputs from the plurality of inputs, four elementary logic units receiving as inputs the outputs of the two tertiary logic units, and further logic for generating binary outputs as an elementary symmetric function of the binary inputs to the quaternary logic unit using the binary outputs of the four elementary logic units.
  • elementary logic units are provided as the logic units at the first level for performing the smallest elementary symmetric functions, and logic units for higher levels comprise logic units of lower levels.
  • the logic units for higher levels above the second level comprise logic units of an immediately preceding level and elementary logic units.
  • each logic unit at each level is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic circuit using OR logic for combining the binary inputs.
  • each logic unit at each level is arranged to generate logic unit binary outputs as an elementary symmetric function of the binary inputs to the logic circuit using exclusive OR logic for combining the binary inputs.
  • each of the binary outputs can be generated using an elementary symmetric function which uses exclusive OR logic.
  • exclusive OR logic is not as fast as OR logic.
  • at least one of the binary outputs is generated as an elementary symmetric function of the binary inputs using OR logic for combining a variety of sets of one or more binary inputs. The logic is arranged to logically AND members of each set of binary inputs and logically OR the result of the AND operations.
  • the set size is set to be 2 N_1 , where N is the number of binary outputs and the N th binary output is the most significant.
  • a plurality of possible binary outputs for a binary output less significant than the N th are generated as elementary symmetric functions of the binary inputs using OR logic for combining a plurality of sets of one or more binary inputs, where N is the number of binary outputs.
  • Selector logic is provided to select one of the possible binary outputs based on a more significant binary output value.
  • the size of the sets used in such an arrangement for the (N-l) th bit is preferably 2 N_1 + 2 n"2 and 2 N"2 respectively and one of the possible binary outputs is selected based on the N th binary output value.
  • the circuit is designed in a modular form.
  • a plurality of subcircuit logic modules are designed, each for generating intermediate binary outputs as an elementary symmetric function of some of the binary inputs.
  • Logic is also provided in this embodiment for logically combining the intermediate binary outputs to generate binary outputs.
  • the logic units are arranged hierarchically and at least one logic unit in at least one level of the hierarchy implements an inverted elementary symmetric function.
  • the logic units at an odd number of levels in the hierarchy implement inverted elementary symmetric functions
  • logic units at an even number of levels in the hierarchy implement symmetric functions
  • the inputs to the logic units at the first level of the hierarchy are inverted.
  • logic units at an even number of levels in the hierarchy implement inverted elementary symmetric functions
  • logic units at an even number of levels in the hierarchy implement symmetric functions
  • the inputs to the logic units at the first level of the hierarchy are input to logic units in a first level in the hierarchy uninverted.
  • the subcircuit logic modules implement the elementary symmetric functions using OR logic.
  • the subcircuit modules can be used for generating some binary outputs and one or more logic modules can be provided for generating other binary outputs in which each logic module generates a binary output as an elementary symmetric function of the binary inputs exclusive OR logic for combining a plurality of sets of one or more binary inputs.
  • Another aspect of the present invention provides a method of designing a logic circuit comprising: providing a library of logic module designs each for performing a small elementary symmetric function; designing a logic circuit to perform a large elementary symmetric function; identifying small elementary symmetric functions which can perform said elementary symmetric function; selecting logic modules from said library to perform said small elementary symmetric functions; identifying a logic circuit in the selected logic circuit which performs an elementary symmetric function and which can be used to perform another elementary symmetric function; selecting the logic circuit corresponding to the identified elementary symmetric function and using the selected logic circuit with inverters to perform said other elementary symmetric function using the relationship between the elementary symmetric functions:
  • OR_n_k(X ⁇ ...X n ) -.OR_n_(n+l-k)(-,X ⁇ ...-,X n ) where -i denotes an inversion, n is the number of inputs, and k is the number of sets of inputs AND combined together.
  • Another aspect of the present invention provides a conditional parallel counter having m possible high inputs out of n inputs, where m ⁇ n, and n and m are integers, the counter comprising the parallel counter for counting inputs to generate p outputs for m inputs, wherein the number n of inputs to the counter is greater than 2 P , where p is an integer.
  • these aspects of the present invention provide a fast circuit that can be used in any architecture using parallel counters. The design is applicable to any type of technology from which the logic circuit is built.
  • the parallel counter in accordance with this aspect of the present invention is generally applicable and can be used in a multiplication circuit that is significantly faster than prior art implementations.
  • conditional parallel counter having m possible high inputs out of n inputs, where m ⁇ n, and n and m are integers.
  • the conditional parallel counter comprises the parallel counter as described hereinabove for counting inputs to generate p outputs for m inputs, wherein the number n of inputs to the counter is greater than 2 P .
  • the conditional multiplier can be used in a digital filter for example.
  • a technique for multiplying binary numbers comprises an array generation step in which an array of logical combinations between the bits of the two binary numbers is generated which is of reduced size compared to the prior art.
  • a logic circuit for multiplying two binary numbers comprises array generation logic for performing a logical binary operation between each bit in one binary number and each bit in the other binary number to generate an array of logical binary combinations comprising an array of binary values, and for further logically combining logically adjacent values to reduce the maximum depth of the array to below N bits, where N is the number of bits of the largest of the two binary numbers; array reduction logic for reducing the depth of the array to two binary numbers; and addition logic for adding the binary values of the two binary numbers.
  • each bit A; of the first binary number is logically combined with each bit B j of the second number to generate the array which comprises a sequence of binary numbers represented by the logical combinations, A; and B j .
  • the further logical combinations are carried out by logically combining the combinations A] and B N -2, AI and BN-I, A 0 and BN-2, and Ao and BN- I , where N is the number of bits in the binary numbers. In this way the size of the maximal column of numbers to be added together in the array is reduced.
  • the array generation logic is arranged to combine the combinations A ⁇ AND B n-2 and A 0 AND B n-1 using exclusive OR logic to replace these combinations and to combine A ⁇ AND B N - I and A 0 AND B n-2 to replace the A] AND B n - ⁇ combination.
  • the array reduction logic can include at least one of: at least one full adder, at least one half adder, and at least one parallel counter.
  • the or each parallel counter can comprise the parallel counter in accordance with the first aspects of the present invention.
  • This aspect of the present invention provides a reduction of the maximal column length in the array thereby reducing the number of steps required for array reduction.
  • an even more efficient multiplication circuit is provided.
  • One embodiment of the present invention provides a multiply-accumulate logic circuit comprising the logic circuit as described hereinabove, wherein said array generation logic is arranged to include an accumulation of previous multiplications.
  • Another aspect of the present invention provides a logic circuit comprising at least four inputs for receiving a binary number as a plurality of binary inputs; at least one output for outputting binary code; and logic elements connected between the plurality of inputs and the or each binary output and for generating the or each binary output in accordance with a threshold function implemented as a binary tree and having a threshold of at least 2.
  • a threshold function is a function which is high if, and only if, at least a threshold number k of the inputs are high, where k>2.
  • the logic elements are arranged to generate the or each binary output as an elementary symmetric function of the binary inputs i.e. the threshold function is implemented as an elementary symmetric function.
  • Another aspect of the present invention provides a logic circuit comprising at least four inputs for receiving a binary number as a plurality of binary inputs; at least one output for outputting binary code; and logic elements connected between the plurality of inputs and the plurality of binary outputs arranged to generate the or each of the plurality of binary outputs as an elementary symmetric function of the binary inputs.
  • a further aspect of the present invention provides a method and system for designing a logic circuit comprising a plurality of inputs for receiving a binary number as a plurality of binary inputs, at least one output for outputting binary code, and logic elements connected between the plurality of inputs and the or each binary output and arranged to generate the or each binary output as a threshold function of the binary inputs.
  • the method comprises determining logic elements for performing the threshold functions; and reducing the logic elements by identifying logic elements performing a logical AND of two threshold functions and reducing the identified logic elements to logic elements for performing the threshold function having the higher threshold, and identifying logic elements performing a logical OR of two threshold functions and reducing the identified logic elements to logic elements for performing the threshold function having the lower threshold.
  • This aspect of the present invention can be implemented in software using a computer system comprising one or multiple networked computers.
  • the invention thus encompasses program code for controlling a computer system.
  • the code can be provided to the computer system on any suitable carrier medium such as a storage medium e.g. a floppy disk, hard disk, CD ROM, or programmable memory device, or a transient medium e.g. an electrical, optical, microwave, acoustic, or RF signal.
  • a transient medium is a signal carrying the code over a network such as the Internet.
  • a further aspect of the present invention provides a method and system for designing a logic circuit comprising a plurality of inputs for receiving a binary number as a plurality of binary inputs, at least one output for outputting binary code, and logic elements connected between the plurality of inputs and the binary outputs and arranged to generate each binary output as a symmetric function of the binary inputs.
  • the method comprises designing the logic circuit using exclusive OR logic; identifying any logic which cannot have inputs that are high at the same time; and replacing the identified exclusive OR logic with OR logic.
  • the logic circuit is designed to generate each binary output as an elementary symmetric function of the binary inputs.
  • the logic circuit comprises a parallel counter.
  • This aspect of the present invention can be implemented in software using a computer system comprising one or multiple networked computers.
  • the invention thus encompasses program code for controlling a computer system.
  • the code can be provided to the computer system on any suitable carrier medium such as a storage medium e.g. a floppy disk, hard disk, CD ROM, or programmable memory device, or a transient medium e.g. an electrical, optical, microwave, acoustic, or RF signal.
  • a transient medium is a signal carrying the code over a network such as the Internet.
  • a further aspect of the present invention provides a method and system for designing a logic circuit comprising providing a library of logic module designs each for performing a small symmetric function; designing a logic circuit to perform a large symmetric function; identifying small symmetric functions which can perform said symmetric function; selecting logic modules from said library to perform said small symmetric functions; identifying a logic circuit in the selected logic circuit which performs a symmetric function and which can be used to perform another symmetric function; and selecting the logic circuit corresponding to the identified symmetric function and using the selected logic circuit with inverters to perform said other symmetric function using the relationship between the symmetric functions:
  • OR_n_k(Xj...X consent) -,OR n_(n+l-k)(-,X ⁇ ...- ⁇ X n ) where -i denotes an inversion, n is the number of inputs, and k is the number of sets of inputs AND combined together.
  • the symmetric functions are elementary symmetric functions.
  • This aspect of the present invention can be implemented in software using a computer system comprising one or multiple networked computers.
  • the invention thus encompasses program code for controlling a computer system.
  • the code can be provided to the computer system on any suitable carrier medium such as a storage medium e.g. a floppy disk, hard disk, CD ROM, or programmable memory device, or a transient medium e.g. an electrical, optical, microwave, acoustic, or RF signal.
  • a transient medium is a signal carrying the code over a network such as the Internet.
  • the present invention can be implemented using standard cells wherein standard cells can be designed specifically for implementation in the logic circuit or parallel counter.
  • the invention encompasses a method and system for designing the standard cells, e.g. a computer system implementing computer code, and a method and system for designing a logic circuit using the standard cells, e.g. a computer system implementing computer code.
  • the standard cells can be represented after their design as code defining characteristics of the standard cells.
  • This code can then be used by a logic circuit (e.g. a parallel counter circuit) design program for the design of the logic circuit.
  • the end result of the design of the logic circuit can comprise code defining the characteristics of the logic circuit.
  • This code can then be passed to a chip manufacturer to be used in the manufacture of the logic circuit in semiconductor material, e.g. silicon.
  • Figure 1 is a schematic diagram of a full adder and a half adder in accordance with the prior art
  • FIG. 2 is a schematic diagram of a parallel counter using full adders in accordance with the prior art
  • Figure 3 is a schematic diagram illustrating the logic modules executing the symmetric functions for the generation of binary outputs and the multiplexor (selector) used for selecting outputs,
  • Figure 4 is a diagram illustrating the logic for implementing the symmetric function OR_3_l according to one embodiment of the present invention
  • Figure 5 is a diagram illustrating the logic for implementing the symmetric function OR_4_l according to one embodiment of the present invention
  • Figure 6 is a diagram illustrating the logic for implementing the symmetric function OR_5_l using 2 3 input OR gates according to one embodiment of the present invention
  • Figure 7 is a diagram illustrating the logic for implementing the symmetric function EXOR_7_l using two input exclusive OR gates according to one embodiment of the present invention
  • Figure 8 is a diagram illustrating the logic for implementing the symmetric function OR_3_2 according to one embodiment of the present invention
  • Figure 9 is a diagram illustrating the logic for implementing the symmetric function EXOR_5_3 according to one embodiment of the present invention
  • Figure 10 is a diagram illustrating a parallel counter using the two types of symmetric functions and having seven inputs and three outputs according to one embodiment of the present invention
  • Figure 11 is a diagram illustrating splitting of the symmetric function OR_7_2 into sub modules to allow the reusing of smaller logic blocks according to one embodiment of the present invention
  • Figure 12 is a diagram of a parallel counter using the EXOR_7_l symmetric function for the generation of the least significant output bit from all of the input bits, and smaller modules implementing symmetric functions using OR logic to generate the second and third output bits according to one embodiment of the present invention
  • Figure 13 is a another diagram of a parallel counter similar to that of Figure 12 accept that the partitioning of the inputs is chosen differently to use different functional sub modules according to one embodiment of the present invention
  • Figure 14 is a diagram schematically illustrating the binary tree organisation of the logic in a parallel counter according to a second aspect of the invention.
  • Figure 15 is a diagram illustrating the logic block (Block 1) for implementing the elementary symmetric functions OR_2_2 and OR_2_l according to one embodiment of the present invention
  • Figure 16 is a diagram illustrating the logic block (Block 2) for implementing the secondary symmetric functions OR_4_4, OR_4_3, OR_4_2 and OR_4_l according to one embodiment of the present invention
  • Figure 17 is a diagram illustrating the logic block (Block 3) for implementing the tertiary symmetric functions OR_8_8, OR_8_7, OR_8_6, OR_8_5, OR_8_4, OR_8_3,
  • Figure 18 is a diagram illustrating the logic block (Block 4) for implementing the symmetric functions OR_15_12, OR_15_8 and OR_15_4 according to one embodiment of the present invention
  • Figure 19 is a diagram illustrating the logic block (Block 5) for implementing the elementary symmetric functions EXOR_4_2 and OR_4_l according to one embodiment of the present invention
  • Figure 20 is a diagram illustrating the logic block (Block 6) for implementing the elementary symmetric functions EXOR 15 2 and OR 15 1 according to one embodiment of the present invention
  • Figure 21 is a diagram schematically illustrating a parallel counter using the logic blocks of Figures 15 to 20 according to one embodiment of the present invention
  • Figure 22 is a diagram illustrating a hierarchical structure for logic units in accordance with an embodiment of the present invention.
  • Figure 23 is a diagram illustrating another hierarchical structure for logic units in accordance with an embodiment of the present invention.
  • Figure 24 is a diagram illustrating a further hierarchical structure for logic units in accordance with an embodiment of the present invention
  • Figure 25 is a diagram illustrating the hierarchical organisation of logic units in a tree structure to implement the elementary symmetric function OR_8_4 in accordance with an embodiment of the present invention
  • Figure 26 is a diagram of the logic for a high speed implementation of the first level the circuit of figure 25,
  • Figure 27 is a diagram of the logic for a high speed implementation of the second level the circuit of figure 25,
  • Figure 28 is a diagram of the logic for a high speed implementation of the third level the circuit of figure 25,
  • Figure 29 is a diagram of the steps used in the prior art for multiplication
  • Figure 30 is a schematic diagram of the process of Figure 29 in more detail
  • Figure 31 is a diagram illustrating the properties of diagonal regions in the array
  • Figure 32 is a diagram illustrating array deformation in accordance with the embodiment of the present invention and the subsequent steps of array reduction and adding,
  • Figure 33 is a diagram of logic used in this embodiment for array generation.
  • Figure 34 is a diagram of a logic circuit for generating an output as a threshold function.
  • the first aspect of the present invention relates to a parallel counter counting the number of high values in a binary number.
  • the counter has i outputs and n inputs where i is determined as being the integer part of log 2 n plus 1
  • a mathematical basis for the first aspect of the present invention is a theory of symmetric functions.
  • C the number of distinct k element subsets of a set of n elements.
  • the functions EXOR_n_k and OR_n_k are elementary symmetric functions.
  • OR n k is much faster to produce since EXOR-gates are slower than OR-gates.
  • n is the number of inputs and k is the size of the subset of inputs selected.
  • Each set of k inputs is a unique set and the subsets comprise all possible subsets of the set of inputs.
  • OR_3_l has three inputs X ls X 2 and X 3 and the set size is 1.
  • the sets comprise Xi, X 2 and X 3 .
  • Each of these sets is then logically OR combined to generated the binary output. The logic for performing this function is illustrated in Figure 4.
  • Figure 5 illustrates the logic for performing the symmetric OR_4_l.
  • Figure 6 illustrates the use of two OR gates for implementing the symmetric function OR_5_l.
  • Figure 7 similarly illustrates the logic for performing EXOR_7_l .
  • the sets comprise the inputs Xi, X 2 , X 3j , X 5 ,X 6 , and X . These inputs are input into three levels of exclusive OR gates.
  • Figure 8 illustrates logic for performing the symmetric function OR_3_2.
  • the inputs Xi and X 2 comprise the first set and are input to a first AND gate.
  • the inputs Xi and X 3 constitute a second set and are input to a second AND gate.
  • the inputs X 2 and X 3 constitute a third set and are input to a third AND gate.
  • the output of the AND gates are input to an OR gate to generate the output function.
  • Figure 9 is a diagram illustrating the logic for performing the symmetric function EXOR_5_3. To perform this function the subsets of size 3 for the set of five inputs comprise ten sets and ten AND gates are required.
  • the output of the AND gates are input to an exclusive OR gate to generate the function.
  • the parallel counter of each output is generated using a symmetric function using exclusive OR logic.
  • the parallel counter have n inputs X ls ... X n and t+1 outputs S t , S t - ⁇ , ... S 0 .
  • S 0 is the least significant bit and S t is the most significant bit. For all i from 0 to t,
  • the most significant output bit is generated using a symmetric function using OR logic.
  • OR_n_k functions are faster than EXOR_n_k functions.
  • An arbitrary output bit can be expressed using OR_n_k functions if one knows bits that are more significant. For instance, the second most significant bit is given by
  • Si OR_7_6(X h X 2 , X 3 , X4, X 5 , X 6 , X 7 ) v ((-,S 2 ) ⁇ OR_7_2(X ⁇ , X 2 , X 3 , X4, Xs, X ⁇ , X7)).
  • a multiplexer MU shown in figure 3, implements this logic. It has two inputs X 0 , Xi, a control C, and an output Z determined by the formula It is not practical to use either EXORj ⁇ Jk functions or OR_n_k functions exclusively. It is optimal to use OR_n_k functions for a few most significant bits and EXOR_n_k functions for the remaining bits. The fastest, in TSMC.25, parallel counter with 7 inputs is shown in figure 10.
  • OR 7 2 An implementation of OR 7 2 is shown in figure 11.
  • the 7 inputs are split into two groups: five inputs from Xi to X 5 and two remaining inputs X 6 and X . Then the following identity is a basis for the implementation in figure 11.
  • OR_7_2(X ⁇ ,... , X 7 ) OR_5_2(X l5 ..., X 5 ) v
  • OR_7_4(X ⁇ ,... , X 7 ) OR_5_4(X l5 ..., X 5 ) v
  • OR_7_6(X l5 ..., X 7 ) (OR_5_5(X ls ... X 5 ) ⁇ OR_2_l(X 6 , X 7 )) v (OR_5_4(X l5 ... X 5 ) ⁇ OR_2_2(X 6 , X 7 )).
  • OR_n_k functions in a parallel counter. For instance, an implementation of a parallel counter based on partitioning seven inputs into groups of two and five is in figure 12.
  • OR_7_2(X ⁇ , ..., X 7 ) OR_4_2(X ⁇ , X 2 , X 3 , X,) v
  • OR_7_4(Xj, ..., X 7 ) OR_4_4(X l5 X 2 , X 3 , X 4 ) v
  • Parallel counters with 6, 5, and 4 inputs can be implemented according to the logic for the seven input parallel counter. Reducing the number of inputs decreases the area significantly and increases the speed slightly. It is advantageous to implement a six input parallel counter using partitions of 6, 3 + 3 or 4 + 2.
  • OR_n_k or EXOR_n_k function in two levels of logic, the fan-out of each input is very high and the fan-in of the OR gate is also very high. It is known that both high fan-out and high fan-in contribute significantly to the delay of the circuit. It is often required that more than one OR n k or EXOR_n_k function be computed from the same inputs. A two level implementation does not allow sharing of logic thus resulting in high area.
  • FIG. 14 illustrates schematically the organisation of the logic.
  • elementary logic blocks 1 are used each having two of the binary inputs and providing 2 outputs.
  • the elementary logic blocks 1 of the first level perform elementary symmetric functions. These can either be exclusive OR symmetric functions or OR symmetric functions.
  • secondary logic blocks 2 each use the logic of two elementary logic blocks 1 and hence have four inputs and four outputs.
  • the secondary logic blocks 2 perform larger symmetric functions.
  • two tertiary logic blocks 3 each use the logic of two secondary logic blocks 2 and hence have eight inputs and eight outputs.
  • the tertiary logic blocks 3 perform larger symmetric functions.
  • the parallel counter 4 uses the logic of two tertiary logic blocks 3 and hence has sixteen inputs and sixteen outputs.
  • the binary tree arrangement of the logic enables the logic for performing smaller symmetric functions to be used for the parallel counter. Also the arrangement provides for significant logic sharing. This significantly reduces fan-out .
  • OR 16 8 OR_16_4 and OR_16_12 are constructed from the set of inputs Xi, X 2 ...X 16 .
  • OR_n_k functions the same construction applies to EXOR_n_k functions after replacing every OR gate by an EXOR gate.
  • OR_(r+s)_t can be computed as the OR of the functions OR r k ⁇ OR_s_t-k as t runs through 0,l,2...k,
  • OR_(r+s)_t(X,...X r+s ) v ⁇ o' [OR_r_k(X ⁇ ...X r ) ⁇ OR_s_(t-k)(X r+1 ...X r+s )].
  • the 16 inputs are divided into 8 subsets - ⁇ X ⁇ ,X 2 ⁇ , each subset containing two inputs.
  • a logic block 1 that computes OR_2_l and OR_2_2 is constructed.
  • the 8 blocks form the first level of the tree. Since each input fans out into an OR gate and an AND gate we see that each input has a fan-out of two. Also the first layer is very regular consisting of 8 identical blocks.
  • the logic block 1 for computing the symmetric functions OR_2_l and OR_2_2 is illustrated in figure 15.
  • 4 logic blocks 2 are formed by combining outputs from two adjacent logic blocks 1 at level one. These 4 blocks comprise the second layer of the tree. Each block has as inputs the outputs of two adjacent blocks from level one. The inputs are combined to form the functions OR_4_l, OR_4_2, OR_4_3, OR_4_4.
  • the logic block 2 for computing these symmetric functions is illustrated in figure 16.
  • the indices 1 and 2 are used in the equations below to distinguish functions formed on different subsets of the set of inputs.
  • the symmetric functions can be represented as:
  • OR_4_l [OR_2_l]j v [OR_2_l] 2 ,
  • OR_4_2 ([OR_2_l] ⁇ ⁇ [OR_2_l] 2 ) v ([OR_2_2] 1 +[OR_2_2] 2 ),
  • OR_4_3 ([OR_2_l] ⁇ A [OR_2_2] 2 ) v ([OR_2_2] ⁇ ⁇ [OR_2_l] 2 ),
  • OR_4_4 [OR_2_2] 1 ⁇ [OR_2_2] 2 .
  • 2 logic blocks 3 are formed by combining outputs from two adjacent logic blocks 2 at level two. These 2 blocks comprise the third layer of the tree. Each block has as inputs the outputs of two adjacent blocks from level two. The inputs are combined to form the functions OR_8_l, OR_8_2, OR_8_3, OR_8_4, OR_8_5, OR_8_6, OR_8_7 and OR_8_8.
  • the logic block 3 for computing these symmetric functions is illustrated in figure 17.
  • the symmetric functions can be represented as:
  • OR_8_l [OR_4_l] ! v [OR_4_l] 2 ,
  • OR_8_2 ([OR_4_l] ⁇ ⁇ [OR_4_l] 2 ) v [OR_4_2] ! v [OR_4_2] 2 ,
  • OR_8_3 ([OR_4_l] 1 ⁇ [OR_4_2] 2 ) v
  • OR_8_4 ([OR_4_l] 1 ⁇ [OR_4_3] 2 ) v ([OR_4_2] ⁇ ⁇ [OR_4_2] 2 ) v
  • OR_8_5 ([OR_4_l]j ⁇ [OR_4_4] 2 ) v ([OR_4_2] ! ⁇ [OR_4_3] 2 ) v
  • OR_8_6 ([OR_4_2] 1 A [OR_4_4] 2 ) v
  • OR_8_7 ([OR_4_3] ⁇ ⁇ [OR_4_4] 2 ) v ([OR_4_4] ! ⁇ [OR_4_3] 2 ),
  • OR_8_8 [OR_4_4] ⁇ ⁇ [OR_4_4] 2 .
  • OR_16_4 ([OR_8_l] ⁇ ⁇ [OR_8_3] 2 ) v ([OR_8_2] ! ⁇ [OR_8_2] 2 ) v
  • OR_16_8 ([OR_8_l] 1 ⁇ [OR_8_7] 2 ) v ([OR_8_2] ⁇ ⁇ [OR_8_6] 2 ) v
  • OR_16_12 ([OR_8_4] ⁇ ⁇ [OR_8_8] 2 ) v ([OR_8_5] ! ⁇ [OR_8_7] 2 ) v ([OR_8_6] 1 ⁇ [OR_8_6] 2 ) v ([OR_8_7]! ⁇ [OR_8_5] 2 ) v ([OR_8_8] ! A [OR_8_4] 2 ).
  • Figure 19 is a diagram of a logic block 5 for determining the symmetric functions EXOR_4_2 and EXOR_4_l.
  • EXOR_4_2 the faster OR gate replaces an EXOR gate, according to:
  • Four of these logic blocks 5 are provided to take the 16 inputs. Thus the logic block 5 can be considered to be a combined level 1 and 2 implementation.
  • Figure 20 is a diagram of a logic block 6 for determining the symmetric functions EXOR_15_2 and EXOR 15 1 which comprise the least two significant bits output from the parallel counter of this embodiment.
  • This logic block comprises level 3 in the binary tree and it uses four of the logic blocks 5. Thus even in this parallel determination of the least significant two bits, there is reuse of logic using the binary tree structure.
  • Figure 21 is a diagram of the parallel counter of this embodiment of the invention in which the logic of block 4 is used to determine the most significant bits and the logic of block 6 is used to determine the least significant bits.
  • the multiplexor (MU) generates Si using OR(7,4), OR(7,6) and OR(7,2).
  • OR(7,4) For example, in the circuit of figure 10, the multiplexor (MU) generates Si using OR(7,4), OR(7,6) and OR(7,2).
  • OR(7,4) In unreduced for the logic to generate Si is:
  • OR_4_l [OR_2_l] ⁇ v [OR_2_l] 2 ,
  • OR_4_2 ([OR_2_1] I ⁇ [OR_2_1] 2 ) V [OR_2_2] ⁇ v [OR_2_2] 2 ,
  • OR_4_3 [OR_2_1]I ⁇ [OR_2_1] 2 ⁇ ([OR_2_2] ⁇ v [OR_2_2] 2 ),
  • OR_4_4 [OR_2_2] i ⁇ [OR_2_2] 2 .
  • Block 3 is a circuit implementing logic of level three.
  • the reductions afford the following expressions for functions OR_8_l, OR_8_2, OR_8_3, OR_8_4, OR_8_5, OR_8_6, OR_8_7, and OR_8_8,
  • OR_8_l [OR_4_l] ⁇ v [OR_4_l] 2 ,
  • OR_8_2 ([OR__4_l] ⁇ ⁇ [OR_4_l] 2 ) v ([OR_4_2] ⁇ v [OR_4_2] 2 ),
  • OR_8_3 [([OR_4_l] ⁇ ⁇ [OR_4_l] 2 ) ⁇
  • OR_8_4 [([OR_4_l] ⁇ ⁇ [OR_4_l] 2 ) ⁇ ([OR_4_3] ⁇ v [OR_4_3] 2 )] v
  • OR_8_5 [([OR_4_l] ⁇ ⁇ [OR_4_l] 2 ) A ([OR_4_4] ⁇ v [OR_4_4] 2 )] v t([OR_4_2] ⁇ ⁇ [OR_4_2] 2 ) ⁇ ([OR_4_3] ⁇ v [OR_4_3] 2 )] ,
  • OR_8_6 [([OR_4_2] ⁇ A [OR_4_2] 2 ) A ([OR_4_4] ⁇ v [OR_4_4] 2 )] v
  • OR_8_7 ([OR_4_3] ⁇ ⁇ [OR_4_3] 2 ) ⁇
  • OR_8_8 [OR_4_4] ⁇ ⁇ [OR_4_4] 2 .
  • Block 4 is a circuit implementing logic for level 4.
  • the implementation of functions OR_16_8, OR_16_4, and OR_16_12 follows reduced formulas,
  • OR_16_4 [([OR_8_l] ⁇ ⁇ [OR_8_l] 2 ) ⁇ ([OR_8_3] ⁇ v [OR_8_3] 2 )] v
  • OR_16_8 [([OR_8_l] ⁇ ⁇ [OR_8_l] 2 ) A ([OR_8_7] ⁇ v [OR_8_7] 2 )] v
  • OR_16_12 [([OR_8_4] ⁇ ⁇ [OR_8_4] 2 ) ⁇ ([OR_8_8] ⁇ v [OR_8_8] 2 )] v
  • the binary tree principle of this embodiment of the present invention can be implemented using either OR or EXOR symmetric functions.
  • EXOR_n_k AND ieS EXOR_n_2 j .
  • the most efficient circuit can comprise a mixture of OR and EXOR symmetric function logic circuits. Further reductions can be applied to logic for a parallel counter based on OR elementary symmetric functions.
  • the generation of an output bit below the most significant bit can be explained as at least one AND combination of the output of one symmetric function with an inverted output of another symmetric function and OR combining the result of the AND combinations.
  • a conditional parallel counter is a module with n inputs. Let Q be a subset of ⁇ 0,1...n ⁇ . The subset determines a condition. The module produces the binary representation of the number of high inputs if this number of high inputs belongs to Q. If the number of high inputs does not belong to Q, the outputs can be any logical function. Such a module can replace a parallel counter if the number of high inputs is in Q.
  • the present invention is applicable to any hierarchical arrangement of logic units.
  • the splitting of the inputs need not be on a binary basis and all inputs need not be input to logic units for performing small elementary symmetric functions.
  • figure 22 illustrates a hierarchical arrangement in which only four of the inputs are input to elementary logic units.
  • Four of the inputs are only input into a logic unit at the third level of the hierarchy.
  • Each logic unit at each level of the hierarchy comprises the logic of logic units at preceding levels.
  • the logic units at level 2 on the left comprise the logic of two logic units at the first level and the logic unit at level 3 on the left comprises two of the logic units at the second level.
  • the logic unit at the third level on the right is not formed of sub units of logic in this embodiment.
  • the logic unit at the fourth level comprises all of the logic units and comprises the logic circuit.
  • Figure 23 is another example illustrating the division of the logic circuit of figure 12 into two hierarchical levels.
  • one logic unit at the first level has five inputs and the other has two.
  • the logic unit having five inputs comprises the logic for performing the OR_5_l, OR_5_2, OR_5_3 , OR_5_4 and OR_5_5 symmetric functions as can be seen in figure 12.
  • the logic unit having two inputs comprises the logic for performing the EXOR_7_l symmetric function as can be seen in figure 12.
  • the logic unit at the second level comprises the logic units at the first level and comprises the complete logic circuit.
  • Figure 24 is a further example illustrating the division of the logic circuit of figure 13 into two hierarchical levels.
  • one logic unit at the first level has four inputs and the other has three.
  • the logic unit having four inputs comprises the logic for performing the OR_4_l, OR 4 2, OR 4 3 and OR_4_4 symmetric functions as can be seen in figure 13.
  • the logic unit having three inputs comprises the logic for performing the OR_3_l, OR_3_2 and OR_3_3 symmetric functions as can be seen in figure 13.
  • the logic unit at the second level comprises the logic units at the first level and comprises the complete logic circuit.
  • OR_n_k(X ⁇ ...X consent) -,OR_n_(n+l-k)(-.X ⁇ ...-.Xn).
  • OR_4_2 enables the generation of OR 4 3.
  • the logic units can comprise standard cells available from a library of standard cells.
  • threshold functions are implemented as elementary symmetric functions.
  • OR_n_k(-,X ⁇ ... iX n ) OR_n_(n+l-k)(X ⁇ ...X n ) (c)
  • equation (a) can be written as:
  • Figure 25 illustrates the binary tree implementation of the elementary symmetric function OR_8_4 in which there are three levels of logic.
  • the circuit receives inverted inputs XI ' ...X8'.
  • This logic circuit receives inverted inputs and implements an elementary symmetric function.
  • FIG 28 The logic circuit realizing these logic equations is shown in figure 28.
  • This logic circuit receives inverted inputs and implements an elementary symmetric function. It can thus be seen from figures 25 to 29 that symmetric functions and inverted symmetric functions are implemented at alternate levels of the hierarchical arrangement of logic units. If there are an odd number of levels, the inputs to the circuit must be inverted, as is the case for the illustrated example [8,4].
  • This use of inverted symmetric functions enables faster NAND gates to be used instead of AND gates (it should be noted that AND gates are implemented as a NAND gate with an inverter and thus the use of a NAND gate instead of an AND gate reduces the logic required to implement the function). The reduction of logic required also reduces the area of the logic circuit.
  • each level of the hierarchical logic structure includes inversion logic.
  • a constant multiplier is a module whose inputs form binary representations of two numbers A, B, and outputs comprise the binary representation of the product A*B whenever A is a number that belongs to a set of allowed constants. Since constant multipliers are smaller and faster then multipliers, it is beneficial to use them whenever one can choose one multiplicand from the set of allowed constants. One can do it, for instance, designing a digital filter.
  • Multiplication is a fundamental operation in digital circuits. Given two n-digit binary numbers
  • P 2n- ⁇ 2 2n - 1 +P 2n-2 2 2n - 2 +...+P ⁇ 2+Po has up to 2n digits.
  • Logical circuits generating all Pj as outputs generally follow the scheme in figure 14.
  • Wallace has invented the first fast architecture for a multiplier, now called the Wallace-tree multiplier (Wallace, C. S., A Suggestion for a Fast Multiplier, IEEE Trans. Electron. Comput. EC-13: 14-17 (1964))(the content of which is hereby incorporated by reference).
  • Dadda has investigated bit behaviour in a multiplier (L. Dadda, Some Schemes for Parallel Multipliers, Alta Freq 34: 349-356 (1965)) (the content of which is hereby incorporated by reference). He has constructed a variety of multipliers and most multipliers follow Dadda's scheme.
  • Dadda's multiplier uses the scheme in on figure 29. If inputs have 8 bits then 64 parallel AND gates generate an array shown in figure 30. The AND gate sign ⁇ is omitted for clarity so that A; ⁇ BJ becomes AjBj. The rest of figure 30 illustrates array reduction that involves full adders (FA) and half adders (HA). Bits from the same column are added by half adders or full adders. Some groups of bits fed into a full adder are in rectangles. Some groups of bits fed into a half adder are in ovals. The result of array reduction is just two binary numbers to be added at the last step. One adds these two numbers by one of fast addition schemes, for instance, conditional adder or carry-look-ahead adder.
  • FA full adders
  • HA half adders
  • This aspect of the present invention comprises two preferred steps: array deformation and array reduction using the parallel counter in accordance with the first aspect of the present invention.
  • Some parts of the multiplication array, formed by AjB j such as on figure 30, have interesting properties. One can write simple formulas for the sum of the bits in these parts. Examples of such special parts are on figure 31. In general, chose an integer k, and those AjB j in the array such that the absolute value of i-j-k is less or equal to 1 comprise a special part.
  • the array in figure 32 is for an 8-bit multiplication.
  • the AND gate sign ⁇ is omitted for clarity so that Aj ⁇ BJ becomes AjB j .
  • Array deformation logic generates X, Y, and Z:
  • the advantage of this array over one in figure 30 is that the maximal number of bits in a column is smaller.
  • the array in figure 30 has a column with 8 bits.
  • the array on figure 32 has 4 columns with 7 bits but none with 8 or more bits.
  • the logic for the generation of X Y and Z is illustrated in figure 33. This logic can be used in parallel with the first two full adders (illustrated in Figure 2) in the array reduction step thus avoiding delays caused by additional logic.
  • Array reduction is illustrated in figure 32.
  • the first step utilizes 1 half adder, 3 full adders, 1 parallel counter with 4 inputs, 2 parallel counters with 5 inputs, 1 parallel counter with 6 inputs, and 4 parallel counters with 7 inputs.
  • the bits X, Y, and Z join the group of two in the partition.
  • the remaining counters should not be partitioned.
  • the locations of full adders are indicated by ovals.
  • the half adder is shown by a rectangle.
  • An adder for adding the final two binary numbers is designed based on arrival time of bits in two numbers. This gives a slight advantage but it is based on common knowledge, that is conditional adder and ripple-carry adder.
  • the invention is applicable to any N bit binary number addition.
  • the array reduction will reduce the middle column height from 16 to 15 thus allowing two seven bit full adders to be used for the first layer to generate two 3 bit outputs and the left over input can be used with the other two 3 outputs as an input to a further seven input full adder thus allowing the addition of the 16 bits in only two layers.
  • this embodiment of the present invention has been described with reference to the formation of the array by logical AND binary combination, this aspect of the present invention encompasses any method of forming the array including any method of logically combining bits of two binary numbers e.g. OR combining, EXOR combining and NAND combining and forming the array using Booth encoding. Further, the length of the two binary numbers need not be the same.
  • the present invention also applies to any logic circuit that performs multiplication including a multiply-accumulate logic circuit (which can be viewed as a special case of a multiplication logic circuit).
  • a multiply-accumulate logic circuit the operation AxB+C is implemented where C is the accumulation of previous multiplications.
  • the multiply-accumulate logic circuit operates by generating the array of AxB as described hereinabove for the multiplication logic circuit. An additional row is added in the array for the bits of C. C can have many more bits than A or B due to previous accumulations. This enlarged array then undergoes array reduction as described hereinabove.
  • This aspect of the present invention can be used with the parallel counter of the first aspects of the present invention to provide a fast circuit.
  • the parallel counter of the first aspects of the present invention has other applications, other than used in the multiplier of one aspect of the present invention. It can be used in RSA and reduced area multipliers. Sometimes, it is practical to build just a fragment of the multiplier. This can happen when the array is too large, for instance in RSA algorithms where multiplicands may have more than more than 1000 bits. This fragment of a multiplier is then used repeatedly to reduce the array. In current implementations, it consists of a collection of full adders. One can use 7 input parallel counters followed by full adders instead.
  • a parallel counter can also be used in circuits for error correction codes.
  • the Hamming distance has to be computed in certain types of decoders, for instance, the Niterbi decoder or majority-logic decoder.
  • the Hamming distance between them is the number of indices i between 1 and n such that Aj and Bi are different. This distance can be computed by a parallel counter whose n inputs are
  • the multiply-and-add operation is fundamental in digital electronics because it includes filtering. Given 2n binary numbers Xi, X 2 , ... X n , Yi, Y 2 , ... Y n , the result of this operation is
  • Figure 34 illustrates an embodiment of another aspect of the present invention.
  • This embodiment generates an output in accordance with a threshold function having a threshold of 2 and implemented as a binary tree.
  • the circuit thus implements an elementary symmetric function for the generation of the output when the number of input that are high (k) is at least 2.
  • OR_4_2 XI ⁇ X 2 v XI ⁇ X 3 V XI ⁇ X 4 V X 2 ⁇ X 3 V X 2 ⁇ XI V X 3 ⁇ X 4
  • the circuit can thus act as a switch to provide an output when a certain number of inputs are high.
  • the output can comprise any elementary symmetric function e.g. OR_n_k where n is the number of inputs and k is the number of high inputs.
  • the principles of this aspect of the present invention can be used to generate more than one output each being OR_n_k.
  • one output could be OR_4_2 and another OR_4_3.
  • the present invention encompasses logic circuits that provide outputs using threshold functions. This can be used for parallel counter outputs or for other logic circuits.
  • a standard cell array design employs a library of pre-characterized custom designed cells which are optimized for silicon area and performance. The cells are designed to implement a specific function. Thus the design of a circuit using standard cells requires the choosing of a set of standard cells from the library which, when connected together form the required function. Cells are normally designed to have a uniform height with variable width when implemented in silicon. It is known in standard cell design that logic functions can be combined in a single standard cell to reduce area, reduce power consumption, and increase speed.
  • the present invention encompasses the use of standard cell techniques for the design and implementation of counters and multipliers in accordance with the present invention.
  • the present invention encompasses a standard cell design process in which a design program is implemented by a designer in order to design standard cells which implement either the complete logic function of the parallel counter in accordance with the present invention, or elementary symmetric functions which comprise integral parts of the parallel counter.
  • the design process involves designing, building and testing the standard cells in silicon and the formation of a library of data characterizing the standard cells which have been successfully tested.
  • This library of data characterizing standard cell designs contains information which can be used in the design of a logic circuit using the standard cells.
  • the data or code in the library thus holds characteristics for the logic circuit which defines a model of the standard cell.
  • the data can include geometry, power, and timing information as well as a model of the function performed by the standard cell.
  • a vender of standard cell designs can make the library of standard cell code available to logic circuit designers to facilitate the designing of logic circuits to perform specific functions using the functionality of the library of standard cells.
  • a logic circuit designer can use the library of code for standard cells in a computer modelling implementation to assemble a logic circuit, i.e. the parallel counter or a multiplication circuit using the standard cell code.
  • the designer therefore implements a design application which uses the code to build the model of the desired logic circuit.
  • the resultant data defines the characteristics of the logic circuit, e.g. parallel counter or multiplication logic circuit in terms of a combination of standard cells. This data can thus be used by a chip manufacturer to design and build the chip using the model data generated by the logic circuit designer.
  • the present invention encompasses the design of standard cells for implementing the functions in accordance with the present invention, i.e. the generation of model data defining the characteristics of standard cells implementing the inventive functions.
  • the present invention also encompasses the method of designing the inventive parallel counter circuit or multiplication circuit using the library of standard cell data, i.e. the steps of using a computer program to generate data modelling the characteristics of the inventive parallel counter or multiplication logic circuit.
  • the present invention also encompasses the process of manufacturing the parallel counter or multiplication logic circuit using the design data.
  • the standard cells designed can implement the complete functionality of the parallel counter or the functionality of a sub-unit of the counter.
  • the parallel counter can be designed either to be implemented by a single standard cell, or by the combination of a plurality of standard cells.
  • a standard cell is designed to implement at least two OR symmetric functions and has at least three inputs.
  • a standard cell is designed to implement at least two elementary symmetric functions and has at least two inputs and at least one output which is generated based on at least one of the symmetric functions.
  • a standard cell can implement a number of symmetric functions.
  • the standard cell can thus include logic for implementing a combination of OR and XOR symmetric functions. These standard cells can thus be combined in the design of the logic or implementing the parallel counter.
  • a standard cell could implement two of the OR symmetric functions.
  • a standard cell could implement the OR_7_2 symmetric function and the EXOR_7_l symmetric function.
  • the present invention encompasses the implementation of any of the modules described hereinabove for the previous embodiments as standard cells.
  • a modular design using standard cells which implements one or more units illustrated in Figures 14, 22, 23 and 24 can be provided.
  • Standard cells can be designed to implement any level of functionality of sub-units within the parallel counter or logic circuit. Standard cells can thus be used for the implementation of a single symmetric function, or a combination of symmetric functions.
  • the present invention further encompasses any method of designing and manufacturing any inventive logic circuit, parallel counter or multiplication logic circuit as hereinabove described.
  • the invention further encompasses code or data characterizing the inventive logic circuit, parallel counter or multiplication circuit.
  • the present invention encompasses code for modelling the inventive functionality of the logic circuit, parallel counter, or multiplication circuit as hereinabove described.
  • the code for designing, and the code for defining characteristics or functions of the standard cells, logic circuit or parallel counter can be made available on any suitable carrier medium such as a storage medium, e.g. a floppy disk, hard disk, CD-ROM, tape device or solid state memory device, or a transient medium such as any type of signal, e.g. an electric signal, optical signal, microwave signal, acoustic signal or a magnetic signal (e.g. a signal carried over a communications network).
  • a storage medium e.g. a floppy disk, hard disk, CD-ROM, tape device or solid state memory device
  • a transient medium such as any type of signal, e.g. an electric signal, optical signal, microwave signal, acoustic signal or a magnetic signal (e.g. a signal carried over a communications network).
  • the logic circuits of the embodiments of the present invention described hereinabove can be implemented in an integrated circuit, or in any digital electronic device.

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Abstract

L'invention concerne un circuit logique, tel qu'un compteur parallèle, comprenant une logique permettant de générer des bits de sortie sous forme de fonctions symétriques élémentaires des bits d'entrée. Le compteur parallèle peut être utilisé dans un circuit de multiplication. L'invention concerne également un circuit de multiplication, dans lequel une matrice de combinaisons de chaque bit d'un nombre binaire avec chaque bit d'un autre nombre binaire est générée, ladite matrice présentant une forme réduite, afin de permettre de réduire les étapes requises dans une réduction de matrice.
PCT/GB2001/004455 2000-08-04 2001-10-05 Compteur parallele et circuit logique executant une multiplication WO2003034200A1 (fr)

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