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WO2003032160A3 - Architecture de circuits protegee contre des perturbations - Google Patents

Architecture de circuits protegee contre des perturbations Download PDF

Info

Publication number
WO2003032160A3
WO2003032160A3 PCT/FR2002/003484 FR0203484W WO03032160A3 WO 2003032160 A3 WO2003032160 A3 WO 2003032160A3 FR 0203484 W FR0203484 W FR 0203484W WO 03032160 A3 WO03032160 A3 WO 03032160A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuits
circuit architecture
protected against
against perturbations
perturbations
Prior art date
Application number
PCT/FR2002/003484
Other languages
English (en)
Other versions
WO2003032160A2 (fr
Inventor
Michael Nicolaidis
Original Assignee
Iroc Technologies
Michael Nicolaidis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iroc Technologies, Michael Nicolaidis filed Critical Iroc Technologies
Priority to EP02785543A priority Critical patent/EP1451688A2/fr
Priority to US10/492,294 priority patent/US20040255204A1/en
Publication of WO2003032160A2 publication Critical patent/WO2003032160A2/fr
Publication of WO2003032160A3 publication Critical patent/WO2003032160A3/fr
Priority to US11/904,762 priority patent/US20080028278A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne une architecture de circuit numérique comprenant des circuits combinatoires (10, 12), des circuits de mémoire de courte durée (11) non suseptibles de stocker des données pendant plus de k cycles de fonctionnement, des circuits de mémoire de longue durée (13) susceptibles de stocker des données pendant plus de k cycles de fonctionnement du circuit. Des systèmes de protection contre les perturbations distincts sont utilisées pour les différents types de circuits et selon la fonctionnalité de ces circuits.
PCT/FR2002/003484 2001-10-12 2002-10-11 Architecture de circuits protegee contre des perturbations WO2003032160A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP02785543A EP1451688A2 (fr) 2001-10-12 2002-10-11 Architecture de circuits protegee contre des perturbations
US10/492,294 US20040255204A1 (en) 2001-10-12 2002-10-11 Circuit architecture protected against perturbations
US11/904,762 US20080028278A1 (en) 2001-10-12 2007-09-27 Circuit architecture protected against perturbations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0113241A FR2830972B1 (fr) 2001-10-12 2001-10-12 Architecture de circuits protegee contre des perturbations
FR01/13241 2001-10-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/904,762 Division US20080028278A1 (en) 2001-10-12 2007-09-27 Circuit architecture protected against perturbations

Publications (2)

Publication Number Publication Date
WO2003032160A2 WO2003032160A2 (fr) 2003-04-17
WO2003032160A3 true WO2003032160A3 (fr) 2004-06-17

Family

ID=8868280

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/003484 WO2003032160A2 (fr) 2001-10-12 2002-10-11 Architecture de circuits protegee contre des perturbations

Country Status (4)

Country Link
US (2) US20040255204A1 (fr)
EP (1) EP1451688A2 (fr)
FR (1) FR2830972B1 (fr)
WO (1) WO2003032160A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790887B1 (fr) * 1999-03-09 2003-01-03 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires
DE102006027448B4 (de) * 2006-06-12 2008-05-15 Universität Potsdam Schaltungsanordnung

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199810A (en) * 1977-01-07 1980-04-22 Rockwell International Corporation Radiation hardened register file
US4612632A (en) * 1984-12-10 1986-09-16 Zenith Electronics Corporation Power transition write protection for PROM
US5173905A (en) * 1990-03-29 1992-12-22 Micron Technology, Inc. Parity and error correction coding on integrated circuit addresses
EP0547412A2 (fr) * 1991-12-16 1993-06-23 International Business Machines Corporation Conception à tolérance de fautes pour défauts dépendant du temps
US5410550A (en) * 1990-04-13 1995-04-25 Vlsi Technology, Inc. Asynchronous latch circuit and register
US5508634A (en) * 1993-02-10 1996-04-16 Fujitsu Limited Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity
FR2790887A1 (fr) * 1999-03-09 2000-09-15 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942516A (en) * 1970-12-28 1990-07-17 Hyatt Gilbert P Single chip integrated circuit computer architecture
US5336939A (en) * 1992-05-08 1994-08-09 Cyrix Corporation Stable internal clock generation for an integrated circuit
US5699365A (en) * 1996-03-27 1997-12-16 Motorola, Inc. Apparatus and method for adaptive forward error correction in data communications
US5931959A (en) * 1997-05-21 1999-08-03 The United States Of America As Represented By The Secretary Of The Air Force Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance
US6519715B1 (en) * 1998-05-22 2003-02-11 Hitachi, Ltd. Signal processing apparatus and a data recording and reproducing apparatus including local memory processor
US6636991B1 (en) * 1999-12-23 2003-10-21 Intel Corporation Flexible method for satisfying complex system error handling requirements via error promotion/demotion

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199810A (en) * 1977-01-07 1980-04-22 Rockwell International Corporation Radiation hardened register file
US4612632A (en) * 1984-12-10 1986-09-16 Zenith Electronics Corporation Power transition write protection for PROM
US5173905A (en) * 1990-03-29 1992-12-22 Micron Technology, Inc. Parity and error correction coding on integrated circuit addresses
US5410550A (en) * 1990-04-13 1995-04-25 Vlsi Technology, Inc. Asynchronous latch circuit and register
EP0547412A2 (fr) * 1991-12-16 1993-06-23 International Business Machines Corporation Conception à tolérance de fautes pour défauts dépendant du temps
US5508634A (en) * 1993-02-10 1996-04-16 Fujitsu Limited Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity
FR2790887A1 (fr) * 1999-03-09 2000-09-15 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JANUSZ SOSNOWSKI: "TRANSIENT FAULT TOLERANCE IN DIGITAL SYSTEMS", IEEE MICRO, IEEE INC. NEW YORK, US, vol. 14, no. 1, 1 February 1994 (1994-02-01), pages 24 - 35, XP000433306, ISSN: 0272-1732 *
SAXENA N ET AL: "ERROR DETECTION AND HANDLING IN A SUPERSCALAR, SPECULATIVE OUT-OF-ORDER EXECUTION PROCESSOR SYSTEM", 25TH. INTERNATIONAL SYMPOSIUM ON FAULT TOLERANT COMPUTING. DIGEST OF PAPERS. PASADENA, JUNE 27 - 30, 1995, INTERNATIONAL SYMPOSIUM ON FAULT TOLERANT COMPUTING, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. SYMP. 25, 27 June 1995 (1995-06-27), pages 464 - 471, XP000573655, ISBN: 0-7803-2965-1 *

Also Published As

Publication number Publication date
US20080028278A1 (en) 2008-01-31
US20040255204A1 (en) 2004-12-16
EP1451688A2 (fr) 2004-09-01
FR2830972A1 (fr) 2003-04-18
WO2003032160A2 (fr) 2003-04-17
FR2830972B1 (fr) 2004-09-10

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