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WO2003019213A1 - Instrument d'essai de semi-conducteurs - Google Patents

Instrument d'essai de semi-conducteurs Download PDF

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Publication number
WO2003019213A1
WO2003019213A1 PCT/JP2002/008702 JP0208702W WO03019213A1 WO 2003019213 A1 WO2003019213 A1 WO 2003019213A1 JP 0208702 W JP0208702 W JP 0208702W WO 03019213 A1 WO03019213 A1 WO 03019213A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage
test
output
driver
Prior art date
Application number
PCT/JP2002/008702
Other languages
English (en)
Japanese (ja)
Inventor
Shoji Kojima
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Publication of WO2003019213A1 publication Critical patent/WO2003019213A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Definitions

  • the present invention relates to a semiconductor testing apparatus using a single transmission connection that can perform a high-speed test as in the case where a transmission line in a test head is a dual transmission connection.
  • FIG. 3 The configuration and operation of a conventional example will be described with reference to FIGS. 3 and 4.
  • FIG. 3 The configuration and operation of a conventional example will be described with reference to FIGS. 3 and 4.
  • the main circuit of the single transmission connection in the test head of the conventional semiconductor test equipment is composed of the pin electronics 40 and the transmission line 30.
  • the semiconductor test apparatus tests the DUT 60 of the device under test.
  • the DUT 60 of the device under test has many test pins, and pin electronics also has many channels corresponding to the test pins, but for simplicity, only the channels for one pin are displayed. Others are omitted. Also, the configurations of connectors, boards, etc., on which the device under test is mounted are omitted for simplicity of the figure and description.
  • the pin electronics 40 has a driver 41 for outputting a test signal, a resistor R of a transmitting end having one end connected to the driver output and the other end connected in series to the transmission line 30, and a signal received on the transmission line 30. It consists of a comparator 42 that compares signals with voltage.
  • Transmission line 30 is connected to pin electronics 40 and the DUT
  • the device under test, DUT 60 is an IC device such as logic or memory, and has many test pins.
  • the delay time of the signal by the transmission line 30 is T
  • the output impedance Ru of the DUT 60 is the characteristic impedance Zo of the transmission line 30 and the transmission impedance of the driver 41 side. The same value as the resistance R at the end.
  • test signal (Dr1) when the test signal (Dr1) is output from the driver 41 end, it is output almost simultaneously to the comparator end 42, and after a delay time T, the write signal (W1 ).
  • the read signal (R 1) read from the DUT 60 reaches the end of the comparator 42 via the transmission line 30 via the delay time T.
  • test signal (Dr2) is output from the dryno 41 end, it is output to the comparator 42 end almost at the same time, and reaches the DUT60 end via the delay time T as a write signal (W2).
  • a signal overlap period occurs between the test signal (Dr2) output at the end of the comparator 42 and the read signal (R1) read from the DUT 60.
  • the overlap period is a dead band period (TX2) during which the comparator 42 cannot perform the comparison operation.
  • TX 2 delay time due to the transmission line 30 must be waited in order to avoid dead band. Therefore, when speeding up the test head of a conventional semiconductor test device, the connection is made by the dual transmission line shown in FIG.
  • the dual transmission connection in the test head is composed of bin electronics 50 and transmission lines 31 and 32.
  • the semiconductor test apparatus tests the DUT 60 of the device under test.
  • the DUT 60 of the device under test has many test pins, and bin electronics also has channels corresponding to each I / O pin, but for simplicity of illustration and explanation, only the channel for one pin is displayed. The rest is omitted and explained.
  • the pin electronics 50 includes a channel for outputting a test signal from the driver 51 to the transmission line 31 via the transmitting end resistor R, and a signal received by terminating the signal transmitted by the transmission line 32 with the resistor R. It is composed of two channels, one for comparison and the other for comparison.
  • the delay times of the signals due to the transmission lines 31 and 32 are respectively Tl and ⁇ 2, and the output impedance Ru of the DU ⁇ 60 is represented by the transmission lines 31 and 3 2 characteristic impedance Z 0 and dryno 5
  • the resistance R at the sending end on the 1 side and the terminating resistance R on the comparator side are the same.
  • test signal (Dr1) when the test signal (Dr1) is output from the driver 51 end, it reaches the DUT 60 end via the delay time T1 as the write signal (W1).
  • the test signal (Dr 1) arrives at the end of the comparator 52 after the time (T 1 + T 2).
  • the read signal (R 1) read from the DUT 60 reaches the end of the driver 51 via the transmission line 31 via the delay time T 1, and reaches the delay time T 2 via the transmission line 32. After that, it reaches the comparator 52 end.
  • the read signal (R1) read from the DUT 60 and the test signal (Dr2) output from the driver 51 overlap with the signal.
  • the test signal (Dr 1) output to the comparator and the read signal (R 1) read from the DUT 60 are delayed by the same delay time (T 1 + T 2), respectively. Signals do not overlap because they have arrived.
  • the dual transmission connection method requires two transmission lines for each DUT 60 test pin.
  • the drive voltage of the dryno 51 is terminated by a resistor R on the side of the comparator 52, so that when a predetermined voltage is applied to the DUT 60, the drive voltage is lower than in the case of single transmission connection.
  • Driver 51 1 Output voltage must be increased.
  • an object of the present invention is to provide a semiconductor test apparatus capable of performing a high-speed test similar to a dual transmission connection by a single transmission connection method.
  • the first aspect of the present invention made to achieve the above object is as follows.
  • a transmitting end resistor connected to the output of the driver
  • Amplifying means for amplifying a signal voltage on the transmission line side of the transmitting end resistor and outputting a signal
  • Subtraction means for subtracting the signal voltage on the driver side of the transmission end resistor from the signal voltage output from the amplification means and outputting a signal
  • the gist of the present invention is a semiconductor test apparatus characterized by having:
  • a second aspect of the present invention, which has been made to achieve the above object, is a gist of the semiconductor test apparatus according to the first aspect of the present invention, wherein the amplifying means is a double amplifier for amplifying a signal voltage by a factor of two.
  • a third aspect of the present invention, which has been made to achieve the above object, is a semiconductor test apparatus,
  • a transmitting end resistor connected to the output of the driver
  • Voltage dividing means for dividing a signal voltage on the driver side of the transmitting end resistor and outputting a signal
  • Subtracting means for subtracting the output signal voltage of the voltage dividing means from the signal voltage on the transmission line side of the transmitting end resistor and outputting a signal
  • the gist of the present invention is a semiconductor test apparatus characterized by having:
  • a fourth aspect of the present invention, which has been made to achieve the above object, is a semiconductor test apparatus,
  • a transmitting end resistor connected to the output of the driver
  • Voltage dividing means for dividing a signal voltage on the driver side of the transmitting end resistor and outputting a signal
  • a comparator for receiving both signals output from the offset applying means and comparing the voltages
  • the gist of the present invention is a semiconductor test apparatus characterized by having:
  • a fifth aspect of the present invention, which has been made to achieve the above object, is:
  • the gist of the present invention is the semiconductor test apparatus according to the third or fourth aspect of the present invention, wherein the voltage dividing means is a resistance voltage dividing circuit that divides a signal voltage by half.
  • the sixth aspect of the present invention made to achieve the above object is as follows.
  • a matching resistor is provided in series with a test pin of the device under test when the output impedance of the device under test is lower than the characteristic impedance of the transmission line.
  • the device is the gist.
  • the semiconductor test apparatus according to the first, third, or fourth aspect of the present invention, wherein a matching resistor is provided in parallel with the test pin of the device under test when the output impedance of the device under test is higher than the characteristic impedance of the transmission line.
  • a matching resistor is provided in parallel with the test pin of the device under test when the output impedance of the device under test is higher than the characteristic impedance of the transmission line.
  • FIG. 1 is a main part circuit diagram of a semiconductor test apparatus of the present invention.
  • FIG. 2 is a main circuit diagram of the semiconductor test apparatus of the present invention using a matching resistor ( FIG. 3 shows a single transmission connection of the conventional semiconductor test apparatus).
  • FIG. 3 shows a single transmission connection of the conventional semiconductor test apparatus.
  • FIG. 4 is a circuit diagram of a conventional semiconductor test apparatus based on double transmission connection.
  • FIG. 5 is an example of a specific timing chart of the present invention.
  • FIG. 6 is a first applied configuration example of the configuration of FIG.
  • FIG. 7 is a second applied configuration example of the configuration of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 An embodiment of the present invention will be described with reference to FIG. 1 and FIG.
  • the main circuit of the single transmission connection system in the test head of the semiconductor test apparatus of the present invention is composed of pin electronics 20 and a transmission line 30.
  • the semiconductor test apparatus tests the DUT 60 of the device under test.
  • the DUT 60 of the device under test has a large number of test pins, and the pin electronics also has the number of channels corresponding to the test pins, but for simplicity, only the channels for one pin are displayed. Is omitted. Also, the configuration of connectors, boards, etc., on which the device under test is mounted is omitted for simplicity of the figure and description.
  • Pin electronics 20 consists of a driver 21 that outputs a test signal, a resistance R at the sending end, a comparator 22 that compares the voltage of the signal, a 2 ⁇ amplifier 23, and a subtraction circuit 24. I have.
  • the 2x amplifier 23 doubles the voltage on the transmission line 30 side of the sending end resistance R. It is an amplifying means.
  • the internal delay of the double amplifier 23 is an ideal amplifier with zero. In an actual circuit, there is an internal delay of about several hundreds of picoseconds. Therefore, a buffer amplifier (or signal delay) with the same delay and a gain of 1 between the output terminal of the driver 21 and the negative input terminal of the subtraction circuit 24 Means or a minute variable delay means) is inserted to cancel the skew error between the two signals.
  • the subtraction circuit 24 subtracts the signal voltage on the driver 21 side of the transmitting end resistor R from the signal voltage of the output of the double amplifier, and outputs a signal.
  • test bin of the DUT 60 of the device under test is the memory I / O pin and the read / write is continuously tested.
  • the output impedance Ru of the DUT 60 shown in FIG. 1 has the same value as the characteristic impedance Zo of the transmission line 30 and the resistance R of the transmitting end of the driver 21 for the sake of simplicity. .
  • the output voltage of the driver 21 is Va, and the output voltage of the DUT 60 is Vu.
  • Vb (Va + Vu) / 2 (1)
  • Vc of the subtraction circuit 24 is expressed by the following equation (2).
  • Vc2 2 xVb—Va Vu (2) That is, in the semiconductor test apparatus of the present invention, the comparator 22 can compare the output voltage of the DUT 60 without being affected by the output voltage of the driver 21. Therefore, the reading and writing can be continuously performed at a high speed.
  • the case where the output resistance of the DUT 60 and the characteristic impedance of the transmission line 30 match has been described, but the output resistance 1 ⁇ u of the 0111 60 is equal to the characteristic impedance Z 0 of the transmission line. Match if not matched The method will be described next.
  • FIG. 5 is an example of a specific timing chart of the present invention. This will be described.
  • the output terminal of the DUT 60 outputs a pulse of 1.Ov output voltage Vu (see FIG. 5A), and the output terminal of the driver 21 outputs 1.0 V output voltage V a (FIG. 5A).
  • the delay time T of the transmission line 30 is assumed to be 2.5 NS.
  • the expression of the timing chart is based on the assumption that the internal delay amount between the double amplifier 23 and the subtraction circuit 24 is zero.
  • the output voltage Vu of Ov output from the DUT 60 becomes a pulse having an amplitude of l / 2Vu as shown in FIG.5B due to the resistor Ru connected in series. After 5 NS, reach Vb. On the other hand, the output voltage Va of 1. Ov output from the output terminal of the driver 21 becomes a pulse having an amplitude of 1/2 Va due to the transmitting end resistance R and reaches the point Vb.
  • the restored waveform in Fig. 5F received by the comparator 22 is the same as the output waveform of the DUT because the waveform on the driver side is canceled out.
  • logic judgment is performed at a desired threshold level, or evening is performed at a desired timing. It is possible to make a judgment.
  • FIG. 6 is a first applied configuration example of the configuration of FIG. In this configuration, the double amplifier 23 is deleted, and the voltage dividing resistors R11 and R12 are provided instead.
  • the voltage dividing resistors R 11 and R 12 divide the output voltage Va of the driver by half, and then supply the divided voltage to the negative input terminal of the subtraction circuit 24.
  • the voltage at the point Vb is a waveform in which the 1/2 Vu amplitude pulse and the l / 2Va amplitude pulse are superimposed, and this is directly input to the subtraction circuit 24 as the positive input. Feed to the end.
  • the comparator 22 has the same amplitude as the half amplitude of the output waveform of the DUT. It is possible to make a logical decision at the threshold 'repel' or to make a timing decision at the desired timing.
  • FIG. 7 is a second applied configuration example of the configuration of FIG. This configuration has a configuration in which the double amplifier 23 and the subtraction circuit 24 are eliminated, and the voltage dividing resistors R 11 and R 12 and the offset applying means 25 are provided instead.
  • the offset applying means 25 receives a signal obtained by dividing the output voltage Va of the driver by 1/2, and shifts the voltage to a voltage level corresponding to a threshold voltage 20 s that defines a threshold level. After the evening 22 Supply to the negative input of 2. The voltage at the other Vb point is supplied to the positive input terminal of the comparator 22 as it is.
  • the present invention is embodied in the form described above, and has the following effects.
  • the transmission is a single transmission connection
  • the dead node does not occur in the comparator, so that the speed can be increased
  • the driver output voltage applied to the DUT is also a dual transmission connection. There is no need to be as high.
  • the semiconductor test apparatus of the present invention has an effect that a high-speed test similar to the dual transmission connection can be performed by the single transmission connection method.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

La présente invention concerne un instrument d'essai de semi-conducteurs destiné à effectuer des essais à vitesse élevée par une connexion de transmission simple, de manière analogue aux essais à vitesse élevée réalisés par une connexion de transmission double. L'instrument d'essai comprend: une unité pilote destinée à produire un signal d'essai; une résistance d'extrémité d'émission connectée à la sortie de l'unité pilote; une ligne de transmission destinée à transmettre un signal à une broche d'essai d'un dispositif faisant l'objet d'un essai à travers la résistance d'extrémité d'émission; un système d'amplification destiné à amplifier la tension du signal à l'extrémité côté ligne de transmission de la résistance d'extrémité d'émission afin de produire un signal; un système de soustraction destiné à soustraire la tension du signal à l'extrémité côté unité pilote de la résistance d'extrémité d'émission, de la tension du signal de la sortie du système d'amplification; et un comparateur destiné à comparer la tension du signal de sortie du système de soustraction.
PCT/JP2002/008702 2001-08-31 2002-08-29 Instrument d'essai de semi-conducteurs WO2003019213A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-263121 2001-08-31
JP2001263121 2001-08-31

Publications (1)

Publication Number Publication Date
WO2003019213A1 true WO2003019213A1 (fr) 2003-03-06

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PCT/JP2002/008702 WO2003019213A1 (fr) 2001-08-31 2002-08-29 Instrument d'essai de semi-conducteurs

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997024622A1 (fr) * 1994-07-15 1997-07-10 Advantest Corporation Circuit electronique a broche d'entree/sortie
WO1999049330A1 (fr) * 1998-03-26 1999-09-30 Teradyne, Inc. Compensation des effets du temps de propagation aller-retour dans les appareils de controle automatique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997024622A1 (fr) * 1994-07-15 1997-07-10 Advantest Corporation Circuit electronique a broche d'entree/sortie
WO1999049330A1 (fr) * 1998-03-26 1999-09-30 Teradyne, Inc. Compensation des effets du temps de propagation aller-retour dans les appareils de controle automatique

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