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WO2003015289A1 - Alignement et quantification non lineaire d'information extrinseque dans un decodeur iteratif - Google Patents

Alignement et quantification non lineaire d'information extrinseque dans un decodeur iteratif Download PDF

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Publication number
WO2003015289A1
WO2003015289A1 PCT/US2002/024538 US0224538W WO03015289A1 WO 2003015289 A1 WO2003015289 A1 WO 2003015289A1 US 0224538 W US0224538 W US 0224538W WO 03015289 A1 WO03015289 A1 WO 03015289A1
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Prior art keywords
extrinsic
data
time slice
value
values
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PCT/US2002/024538
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English (en)
Inventor
David Garrett
Bing Xu
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Lucent Technologies Inc.
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Application filed by Lucent Technologies Inc. filed Critical Lucent Technologies Inc.
Priority to US10/480,135 priority Critical patent/US20040181406A1/en
Priority to JP2003520091A priority patent/JP4195378B2/ja
Priority to KR1020047001641A priority patent/KR100890348B1/ko
Priority to EP02753430A priority patent/EP1413061A1/fr
Publication of WO2003015289A1 publication Critical patent/WO2003015289A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
    • H03M13/6591—Truncation, saturation and clamping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
    • H03M13/6594—Non-linear quantization

Definitions

  • the present invention relates generally to coding systems used in telecommunications and, more particularly to the reduction consumption in iterative decoding.
  • Iterative decoding utilizes a feedback path to present recursive information derived from previous iterations to a current decoding iteration.
  • the current decoding iteration utilizes the recursive information to refine a decoded symbol. Consequentially, the greater the number of iterations employed in the decoding process, the better the bit error rate performance
  • Turbo decoding utilizes iterative decoding and random interleaving to achieve an error performance close to the Shannon limit. Consequently, iterative decoding is often employed in channel equalization and decoding for third generation (3G) mobile communications.
  • Fig. 1 shows a traditional configuration of a turbo decoder 100.
  • Channel values 101 received by the turbo decoder 100 include systematic data, which represent the actual data being transmitted, and parity data, which represent a coded form of the data being transmitted.
  • a demultiplexer 103 receives the channel values 101 and demultiplexes the channel values 101 into systematic data 102, first parity data 104 corresponding to parity data of a first encoder module of a turbo encoder, and second parity data 105 corresponding to parity data of a second encoder module of the same turbo encoder.
  • the demultiplexer 103 presents the first parity data 104 and the systematic data 102 to a first decoder module 106.
  • the first decoder module 106 also receives first priori data 117 from a deinterleaver 114.
  • the first decoder module 106 performs decoding of the systematic data 102 and the first parity data 104 using the first a priori data 117 to produce first extrinsic data 107.
  • the first extrinsic data 107 represents the additional confidence information found in the first decoder module 106 based on systematic data 102, first parity data 104 and first a priori data 117 (the second decoder extrinsic information).
  • the first decoder module 106 is a soft-output decoder, such that the extrinsic data 107 indicates a degree of confidence associated with each bit. For example, if the extrinsic data 107 is comprised of m bits, one bit is devoted to the sign of the decision, indicating whether the additional confidence was 0 (+) or 1 (-), and m-1 bits are devoted to the magnitude of the additional confidence value.
  • the sign bit 0 is associated with a positive value and the sign bit 1 is associated with a negative value.
  • a large positive number indicates that there is a high degree of additional confidence that the uncoded bit was a 0.
  • a small negative number would indicate that the decoder's additional information is for bit 1, but there is not much additional confidence associated with the value.
  • An interleaver 108 receives the first extrinsic data 107.
  • the interleaver 108 permutes the first extrinsic data 107 with a known bit sequence and produces second a priori data 109, which is presented to a second decoder module 111.
  • the second decoder module 111 also receives the second parity data 105 from the demultiplexer 103.
  • the second decoder module 111 operates in a manner corresponding to the first decoder module 106, but in a second time period, to decode the second a priori data 109 * and the second parity data 105 to produce second extrinsic data 112 and decoded soft-outputs 113.
  • a deinterleaver 114 receives the second extrinsic data 112 and performs deinterleaving, which is the inverse of the interleaving performed by the interleaver 108, using the same known bit sequence.
  • the deinterleaver 114 produces the first a priori data 117, which is presented to the first decoder module 106, as described above.
  • the first and second extrinsic data 107, 112 (interleaved and deinterleaved, respectively, to form first and second a priori data 117, 109) passed between the first and second decoder modules 106, 111, provide a measure of a priori additional probability that bit decisions made by the first and second decoder modules 106, 111 are correct.
  • the decoder module 106 or 111 active in the next time period uses the corresponding input a priori data, being the (de)interleaved extrinsic data, to produce a better estimate of the uncoded data.
  • each of the first and second decoder modules 106, 111 utilizes soft-decision decoding algorithms.
  • a control unit 110 presents respective control signals 160, 161, 162, 163, 164 to the demultiplexer 103, first decoder module 106, second decoder module 111, interleaver 108 and deinterleaver 114 so as to afford a recursive mode of operation.
  • the recursive nature of the turbo decoder 100 ensures that subsequent iterations will improve the probability that the decoded soft- outputs 113 accurately represent an originally transmitted information signal.
  • Fig. 2 shows a graph 200 of a typical distribution of extrinsic values after a number of iterations of a turbo decoding process.
  • the extrinsic values associated with such bits being decoded typically oscillate about the vertical axis 210 until the degree of confidence in one or other of the decoded values, 0 or 1, grows in conjunction with the number of iterations of the decoding process.
  • Large positive extrinsic values 220 show an extremely high degree of confidence in additional information of the decoded bit being a 0.
  • large negative values 230 show a high degree of confidence in the additional information of the decoded bit being a 1.
  • the majority of bits being decoded have associated extrinsic values that indicate a fair probability that the bit being decoded is either a 0, shown by the bell-like shape of the distribution on the right-hand side of the vertical axis, or a 1, shown by the bell-like shape of the distribution on the left-hand side of the vertical axis.
  • the memory requirements to store large extrinsic values are costly, as the interleaver 108 and deinterleaver 114 between the first and second decoder modules 106, 111 must store the entire block of the extrinsic information.
  • the extrinsic value starts at zero, but may grow to a value of over 30,000 by the sixth iteration. Storing such numbers requires at least sixteen bits of precision to represent the full range of the extrinsic information. It is desirable to limit the amount of memory required for storing extrinsic values.
  • a method of iterative soft input-soft output decoding in which loglikelihood ratio and output extrinsic determination is performed upon a time slice of a trellis.
  • a priori data input to the determination that are greater than or equal to a predetermined value are identified, and where such data is identified for any one time slice, that one time slice is removed from the determination.
  • a quantizing function is applied to the output extrinsic for each time slice. If the absolute value of the output extrinsic value is less than 1, a quantized value is set to 0. Otherwise, the quantized value retains the sign of the output extrinsic value and the magnitude of the quantized value is equal to 2 X , where x is the largest integer from a range [0,y], such that 2* is the largest integer less than or equal to the absolute value of the output extrinsic value. The quantized value is then substituted for the output extrinsic value for that time slice.
  • a method of iterative soft input-soft output decoding includes the step of identifying instances of input extrinsic data that exceed or are equal to a predetermined threshold. The predetermined threshold is then substituted for each identified instance of input extrinsic data.
  • a method of iterative soft input-soft output decoding involves applying a companding and flooring process to each instance of extrinsic data.
  • the companding and flooring process includes the step of determining the absolute value of the instance of the extrinsic data. If the absolute value of the instance of extrinsic data is less than 1, the method assigns a corresponding quantized value of 0 to the instance of extrinsic data. If the absolute value of the instance of extrinsic data is greater than or equal to 1, the method assigns a corresponding quantized value to the instance of the extrinsic data, wherein the corresponding quantized value retains the sign of the instance of extrinsic data.
  • the magnitude of the corresponding quantized value is equal to 2 X , where x is the largest integer from a range [0,y] such that 2* is the largest integer less than or equal to the absolute value of the instance of extrinsic data.
  • the corresponding quantized value is then substituted for each instance of the extrinsic data for that one time slice.
  • a decoder for use in an iterative soft input-soft output decoder arrangement.
  • the decoder includes a comparator for comparing a priori data input to the decoder with a predetermined extrinsic value for each time slice of a trellis decoding operation.
  • the comparator determines when the data input equals or exceeds the extrinsic value and, in response thereto, sets a flag corresponding to each said time slice.
  • the decoder includes logic that is responsive to enablement of said flag for a corresponding time slice. The logic disables storage of metric values associated with that time slice and also disables a computation of a loglikelihood ratio corresponding to that time slice.
  • a decoder for use in an iterative soft input-soft output decoder arrangement.
  • the decoder includes an arrangement of butterfly processors for calculating a trellis using systematic data, parity data and a priori data.
  • the butterfly processor arrangement includes an alpha memory in which alpha values determined during a forward recursion of the trellis are stored for subsequent loglikelihood determination.
  • the decoder also includes a loglikelihood calculator for producing extrinsic values from the stored alpha values, beta values determined during a backward recursion of the trellis, branch metric values and the a priori data.
  • a comparator receives the a priori data and a predetermined value, wherein the comparator compares each instance of the a priori data for a time slice against the predetermined threshold and if the instance of the a priori data is greater than or equal to the predetermined value, the comparator produces a flag enable signal corresponding to an entry in the alpha memory for the instance of the a priori data.
  • the flag indicates that the corresponding alpha value does not need to be stored for the time slice and the predetermined threshold is presented to the loglikelihood calculator to be substituted for the corresponding alpha value for the production of the extrinsic values.
  • FIG. 1 is a schematic block diagram representation of a prior art arrangement of a turbo decoder
  • FIG. 2 is a graph of a typical distribution of extrinsic values associated with a number of iterations of a turbo decoding process
  • FIG. 3(a) shows the typical distribution of extrinsic values of FIG. 2 with the addition of clamped values
  • FIG. 3(b) shows a companding and flooring function
  • FIG.4 graphically illustrates a prior art companding function
  • FIG. 5 is a schematic block diagram representation of the elementary decoders of FIG. 1 in accordance with an arrangement of the present disclosure
  • FIG. 6 illustrates an evaluation of a multi-state trellis
  • FIG. 7 is a schematic block diagram representation of the loglikelihood calculator of FIG.5. It should be emphasized that the drawings of the instant application are not to scale but are merely schematic representations, and thus are not intended to portray the specific dimensions of the invention, which may be determined by skilled artisans through examination of the disclosure herein. DETAILED DESCRIPTION
  • extrinsic values close to zero have a tendency to oscillate about the vertical axis 210
  • the present inventor has observed that once an extrinsic value attains a sufficiently large positive or negative value the extrinsic value increases monotonically in subsequent iterations, such that if the extrinsic value is positive, the extrinsic value will grow in a positive manner towards the point 220 with each further iteration of the decoding process. Similarly, if the extrinsic value is negative, the extrinsic value will grow towards the point 230 with each subsequent decoding iteration.
  • Fig. 3(a) shows extrinsic values 300 to which a positive clamp 340 and a negative clamp 350 have been applied.
  • positive extrinsic values once the extrinsic value has attained the magnitude of the positive clamp 340 or is in excess of the positive clamp 340, further iterations of the decoding process utilize the clamp value, rather than a further computed extrinsic value.
  • the dotted curve 345 shows a distribution of extrinsic values that would be in excess of the positive clamp 340. Applying the positive clamp 340 creates a large frequency value 360 at the positive clamp 340. A corresponding situation applies for the negative clamp 350, which creates a large frequency value 370. Consequently, it is possible to reduce the required memory size to store extrinsic values, as it is known that all extrinsic values will fall within the range defined by the positive clamp 340 and the negative clamp 350.
  • the present inventor has found that clamping the extrinsic information to a value only slightly larger than the input symbol values results in significant reductions in the memory requirement for the extrinsic memory, with no measurable loss in decoding performance. Further, once the extrinsic value information has reached the value of either one of the clamped values 340 and 350, the decoder 100 is no longer required to calculate new output extrinsic values for subsequent iterations, because having reached the degree of certainty measured by the clamped value, further iterations will only result in further degrees of certainty that the information being decoded is either a 1 or a 0.
  • the decoder 100 can disable any computation related to computing the output extrinsic information for a bit being decoded that has an associated input extrinsic value that is already clamped.
  • extrinsic information It is possible to round down the absolute value of the extrinsic information to a value equal to the closest power of two. For example, for a maximum value of 512, requantized extrinsic information will be an element of the set ⁇ 0, 2* ⁇ , where x has a range of [0,9]. By utilizing such an encoding set, an extrinsic value may be requantized into a 5-bit signed magnitude number, with the lower four bits representing eleven possible values of the
  • Fig. 3(b) shows the companding and flooring function that may be applied to the clamped extrinsic values of Fig. 3(a). If the absolute value of the input extrinsic value is less than 1, the companded extrinsic value is set to 0. Otherwise, the companding and flooring function corresponds to finding o the largest integer x from a range [0,9] such that 2* is the largest integer less than or equal to the absolute value of the input extrinsic value. The companded extrinsic value retains the sign of the input extrinsic value.
  • Utilizing such an encoding scheme provides an extremely simple and yet fast encoding and decoding arrangement, further reducing the requirements of the extrinsic memory.
  • a floor function is applied to the o absolute values of the extrinsic values, the extrinsic values are typically underestimated, but never overestimated, in contrast to the process of Fig. 4.
  • the non-uniform scaling provided by the flooring function reduces the memory requirements for the extrinsic information.
  • the application of such a companding function provides a dampening effect that 5 results in faster and more controlled convergence of the decoding.
  • the encoding scheme provides a high degree of precision for extrinsic data values close to zero and less precision for larger extrinsic values closer to the clamping values.
  • the extrinsic data output from either one of the decoder blocks 106 or 111 is computed by subtracting the priori data received by the decoder block 106 or 111 from an output loglikelihood ratio (LLR) for each bit in the block. Unless the loglikelihood ratio information is needed outside of the turbo decoding block, the loglikelihood ratio and output extrinsic data do not need to be computed for the corresponding input extrinsic data that have been clamped.
  • LLR loglikelihood ratio
  • a trellis diagram represents the possible state changes of a convolutional encoder over time. Each state in the trellis is connected, via two associated branch metrics, to two separate states in the trellis in the next time period.
  • decoding algorithms typically traverse the trellis in a forward direction to determine the probabilities of the individual states and the associated branch metrics.
  • the logMAP algorithm differs from other decoding algorithms, such as the Viterbi algorithm, by performing both a forward and a backward recursion over a trellis.
  • the LogMAP algorithm can be partitioned to provide a Windowed LogMAP arrangement where the blocks are divided into smaller alpha and beta recursions.
  • Alpha values representing the probabilities of each state in the trellis, are determined in the forward recursion.
  • Beta values representing the probabilities of each state in the reverse direction, are determined during the backwards recursion.
  • a LogMAP turbo decoder can apply the clamping process described above to further reduce power through two mechanisms:
  • the local path metric memory only has a depth equal to the window size, it has a wide input word in order to store alpha values for all states of the trellis simultaneously.
  • clamping is effective in reducing the power associated with write accesses to alpha memory, because the alpha values are not stored when the associated input extrinsic is clamped.
  • the LLR calculation uses two sets of logsum trees to compute the log of probability of a zero and the log of probability of a 1. Disabling the logsum trees results in further savings in the logic power.
  • Table 1 shows the percentage of extrinsic values that were clamped in the turbo system (rate 1/3, block size 1700, UMTS interleaver, with extrinsic companding) on a per iteration basis. In the later iterations, most of the path metric memory writes and the LLR computations can be disabled.
  • Fig. 5 shows an expanded arrangement of the elementary decoders 106 and 111, which receive parity, inputs 104 and 105 together with a priori information 117 and 109.
  • the information 102, parity 104, 105 and a priori 117, 109 inputs are provided to an arrangement of butterfly processors 502 which operate to calculate a trellis for turbo decoding. As illustrated by a section 506 in Fig.
  • the butterfly processors include an ⁇ memory 508 in which ⁇ values obtained from a forward calculation of the trellis are stored for subsequent loglikelihood determination.
  • the butterfly processors 502 when performing a reverse calculation of the trellis, determine ⁇ values.
  • the ⁇ values and stored ⁇ values from ⁇ memory 508, together with branch metric values BM0, BM1 and the a priori data 117, 109, collectively indicated at 510 in Fig. 5, are passed to a loglikelihood calculator 504 for calculation and output of the extrinsic value (Le) 107, 112.
  • the decoder 106, 111 also includes a comparator 512, which is presented with the a priori data 117, 109 together with a clamp value 520.
  • the clamp value 520 is set in memory 514 at the maximum value the extrinsic can reach (clamped values 340 and 350).
  • the clamp value is advantageously determined according to the following equation:
  • y is the data and p is parity.
  • max (y+p) is 128, then a clamp value of 512 may be used. This is chosen so that the clamp value clearly dominates the range of possible values calculable from the input data.
  • the clamp values may be loaded to the memory 514 by an input 199 derived from the control input 161.
  • the purpose of the comparator 512 is to provide flag values 516 which are retained in a memory 518 associated with the ⁇ memory 508. For each entry in the ⁇ memory 508 there is a corresponding flag in the memory 518.
  • this flag is that when the a priori data 117,109 is greater than or equal to the clamp 520 the corresponding flag in the memory 518 is set to indicate that the corresponding entry in the ⁇ memory 508 need not be stored and is void.
  • the state of each flag in the memory 518 for a time instance is presented to each of the ⁇ memory 508 and the loglikelihood calculator 504 by an enable signal 740.
  • the ⁇ values at a particular instance in time (t+1, t+2, etc) for all states in the trellis 600 (e.g., a column 604 as illustrated) need not be stored in the ⁇ memory 508.
  • a reverse traversal is then performed to calculate the corresponding ⁇ values.
  • the output 510 of the butterfly processors 502 is enabled. This enablement requires access to the ⁇ memory 506 to retrieve the corresponding ⁇ values from the memory for the corresponding time instance.
  • a specific advantage of the present arrangement is that where the corresponding flag in the memory 518 is set, the butterfly processor 502 has knowledge that there are no retained ⁇ values for that time instance and thus the normally required access to the memory 506 need not be performed. Thus, a power saving in memory access is obtained, together with no increase in processing time.
  • Fig. 7 which represents the loglikelihood calculator 504 of Fig. 5, the ⁇ , ⁇ and branch metric values 510 are provided to the loglikelihood calculator 504 such that the branch metric values are input via respective transparent latches 701 and 709 to corresponding loglikelihood ratio processors 710 and 712 for determining the likelihood of the decoded bit being a 0 or a 1.
  • the corresponding ⁇ and ⁇ values are each provided to an array of transparent latches 702, 704, 706 and 708, the outputs of which are provided to the loglikelihood ratio processors 710 and 712.
  • Each of the latches 701, 702, 704, 706, 708 and 709 is supplied by a common enable signal which is the state of the corresponding flag in the memory 518 for that time instance, this being one of the values previously determined by the comparator 516. In Fig. 7, this state is identified by the reference numeral 740.
  • the respective outputs 714 and 716 of each of the loglikelihood processors 710 and 712 are then provided to a subtracter 718 to determine the loglikelihood ratio 720.
  • the a priori data 117,109 is presented to each of a latch-
  • the latch 732 receives the enable signal 740 to present the a priori data 117,109 to a second subtracter 722.
  • the subtracter 722 receives the loglikelihood ratio 720 and the a priori data 117,109 to produce an extrinsic output value 724.
  • the output value 724 is typically an 11-bit number, corresponding to the aforementioned clamp value of 512, which is provided to a clamping and quantizing unit 726.
  • the unit 726 performs a clamping function as described in Fig. 3(a) and companding function such as that described with reference to Fig. 3(b) or Fig. 4 to produce a quantized output 728.
  • the quantized output 728 in the practical implementation is advantageously a 5-bit value, which is input to a multiplexer 730 that selects either the new quantized 728 value or the priori input 117,109.
  • the multiplexer 730 is enabled by the signal 740 described above.
  • the output of the multiplexer 730 is the current extrinsic value 107,112 output from the decoder 106,111.
  • the (de)interleavers 114 and 108 are implemented by a single reconfigurable memory, there is no requirement to write the new extrinsic value 107, 112 to memory, as such will correspond to that (e.g., 117, 109) which was previously obtained from memory.
  • the transparent latches 701, 702, 704, 706, 708, 709 and 732 hold the ⁇ , ⁇ and branch metric values 510 and a priori input 117, 109 until the enable signal 740 is activated, at which time the values are presented to the loglikelihood processors 710, 712 and the subtracter 722, as described above.
  • the functionality of the latches may alternatively be implemented using AND gates.
  • AND gates toggle to a zero state, which may be advantageous during long periods of inactivity.
  • AND gates also provide a more simple structure.
  • a disadvantage of using AND gates is that AND gates have to toggle to the zero state and back up to an enabled state, which may be less efficient than latches during periods of high activity.
  • the method, system and portions thereof and of the described method and system may be implemented in different locations, such as a wireless unit, a base station, a base station controller, a mobile switching center and/ or a radar system.
  • processing circuitry required to implement and use the described system may be implemented in application specific integrated circuits, software-driven processing circuitry, firmware, programmable logic devices, hardware, discrete components or arrangements of the above components as would be understood by one of ordinary skill in the art with the benefit of this disclosure.

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  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
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  • Nonlinear Science (AREA)
  • Error Detection And Correction (AREA)
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Abstract

L'invention concerne un procédé de décodage SISO (sortie « pondérée »/ entrée « pondérée ») itératif, dans lequel la détermination extrinsèque d'une sortie et d'un taux de probabilité logarithmique est réalisée en fonction d'un intervalle de temps d'un treillis. Une entrée de données a priori à la détermination - entrée supérieure ou égale à une valeur prédéterminée - est identifiée, et de telles données sont identifiées pour tout intervalle de temps, ledit intervalle de temps étant retiré de la détermination. On peut appliquer une fonction de quantification à la sortie extrinsèque pour chaque intervalle de temps. Ladite fonction de quantification comprend, de manière avantageuse, une fonction de compression-expansion et de seuil. La valeur quantifiée est substituée à la valeur extrinsèque de sortie pour cet intervalle de temps.
PCT/US2002/024538 2001-08-03 2002-08-02 Alignement et quantification non lineaire d'information extrinseque dans un decodeur iteratif WO2003015289A1 (fr)

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US10/480,135 US20040181406A1 (en) 2001-08-03 2002-08-02 Clamping and non linear quantization of extrinsic information in an iterative decoder
JP2003520091A JP4195378B2 (ja) 2001-08-03 2002-08-02 反復復号器での外部情報のクランピングおよび非線形量子化
KR1020047001641A KR100890348B1 (ko) 2001-08-03 2002-08-02 반복 디코딩 방법, 및 디코더
EP02753430A EP1413061A1 (fr) 2001-08-03 2002-08-02 Alignement et quantification non lineaire d'information extrinseque dans un decodeur iteratif

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AUPR6802A AUPR680201A0 (en) 2001-08-03 2001-08-03 Reduced computation for logmap iterative decoding

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JEONG G ET AL: "OPTIMAL QUANTIZATION FOR SOFT-DECISION TURBO DECODER", VTC 1999-FALL. IEEE VTS 50TH. VEHICULAR TECHNOLOGY CONFERENCE. GATEWAY TO THE 21ST. CENTURY COMMUNICATIONS VILLAGE. AMSTERDAM, SEPT. 19 - 22, 1999, IEEE VEHICULAR TECHNOLGY CONFERENCE, NEW YORK, NY: IEEE, US, vol. 3 CONF. 50, 19 September 1999 (1999-09-19), pages 1620 - 1624, XP000922381, ISBN: 0-7803-5436-2 *
See also references of EP1413061A1
SUN RONG ET AL: "Nonuniform quantisation of mid-variables for decoding of turbo codes", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 16, 3 August 2000 (2000-08-03), pages 1396 - 1397, XP006015550, ISSN: 0013-5194 *
VOGT J ET AL: "Reducing bit width of extrinsic memory in turbo decoder realisations", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 20, 28 September 2000 (2000-09-28), pages 1714 - 1716, XP006015740, ISSN: 0013-5194 *

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* Cited by examiner, † Cited by third party
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WO2007051072A3 (fr) * 2005-10-27 2007-06-21 Qualcomm Inc Procede et dispositif de demultiplexage binaire dans un systeme de communication sans fil
US7864819B2 (en) 2005-10-27 2011-01-04 Qualcomm Incorporated Method and apparatus for bit demultiplexing in a wireless communication systems
CN101351983B (zh) * 2005-10-27 2012-02-08 高通股份有限公司 一种在无线通信系统中用于比特去复用的方法和装置
US8300751B2 (en) 2005-10-27 2012-10-30 Qualcomm Incorporated Method and apparatus for transmitting and receiving a timing correction message in a wireless communication system

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AUPR680201A0 (en) 2001-08-30
KR20040023710A (ko) 2004-03-18
JP4195378B2 (ja) 2008-12-10
EP1413061A1 (fr) 2004-04-28
KR100890348B1 (ko) 2009-03-25

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