+

WO2003010813A3 - Grid interposer - Google Patents

Grid interposer Download PDF

Info

Publication number
WO2003010813A3
WO2003010813A3 PCT/US2001/042515 US0142515W WO03010813A3 WO 2003010813 A3 WO2003010813 A3 WO 2003010813A3 US 0142515 W US0142515 W US 0142515W WO 03010813 A3 WO03010813 A3 WO 03010813A3
Authority
WO
WIPO (PCT)
Prior art keywords
grid
interposer
grid interposer
conductive surfaces
flat topped
Prior art date
Application number
PCT/US2001/042515
Other languages
French (fr)
Other versions
WO2003010813A2 (en
Inventor
Gary A Clayton
Original Assignee
Gary A Clayton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/912,111 external-priority patent/US6527563B2/en
Application filed by Gary A Clayton filed Critical Gary A Clayton
Priority to AU2002211864A priority Critical patent/AU2002211864A1/en
Publication of WO2003010813A2 publication Critical patent/WO2003010813A2/en
Publication of WO2003010813A3 publication Critical patent/WO2003010813A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/02Contact members
    • H01R13/22Contacts for co-operating by abutting
    • H01R13/24Contacts for co-operating by abutting resilient; resiliently-mounted
    • H01R13/2407Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means
    • H01R13/2414Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means conductive elastomers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0441Details
    • G01R1/0466Details concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0347Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0373Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09481Via in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0369Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0548Masks
    • H05K2203/0554Metal used as mask for etching vias, e.g. by laser ablation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

A grid interposer for testing electrical circuits and a method of making a grid interposer. The grid interposer includes upper and lower conductive surfaces sandwiched on either side of an insulating later, connected to each other by a plurality of vias filled with conductive material. The conductive surfaces are flat topped, and incised with a grid of flat topped peaks which are small enough to cut through oxidation of electrical contacts, and ensure good electrical contact with a variety of electrode shapes.
PCT/US2001/042515 2001-07-23 2001-10-03 Grid interposer WO2003010813A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002211864A AU2002211864A1 (en) 2001-07-23 2001-10-03 Grid interposer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/912,111 US6527563B2 (en) 2000-10-04 2001-07-23 Grid interposer
US09/912,111 2001-07-23

Publications (2)

Publication Number Publication Date
WO2003010813A2 WO2003010813A2 (en) 2003-02-06
WO2003010813A3 true WO2003010813A3 (en) 2003-09-18

Family

ID=25431400

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/042515 WO2003010813A2 (en) 2001-07-23 2001-10-03 Grid interposer

Country Status (2)

Country Link
AU (1) AU2002211864A1 (en)
WO (1) WO2003010813A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765691B2 (en) * 2005-12-28 2010-08-03 Intel Corporation Method and apparatus for a printed circuit board using laser assisted metallization and patterning of a substrate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703753A (en) * 1995-02-16 1997-12-30 Micromodule Systems Inc. Mounting assembly for multiple chip module with more than one substrate and computer using same
US5731636A (en) * 1995-10-19 1998-03-24 Lg Semicon Co., Ltd. Semiconductor bonding package
US5984691A (en) * 1996-05-24 1999-11-16 International Business Machines Corporation Flexible circuitized interposer with apertured member and method for making same
US6094060A (en) * 1997-01-28 2000-07-25 International Business Machines Corporation Test head for applying signals in a burn-in test of an integrated circuit
JP2001004700A (en) * 1999-06-24 2001-01-12 Yamaichi Electronics Co Ltd Interposer board
US6174175B1 (en) * 1999-04-29 2001-01-16 International Business Machines Corporation High density Z-axis connector
US6247228B1 (en) * 1996-08-12 2001-06-19 Tessera, Inc. Electrical connection with inwardly deformable contacts

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703753A (en) * 1995-02-16 1997-12-30 Micromodule Systems Inc. Mounting assembly for multiple chip module with more than one substrate and computer using same
US5731636A (en) * 1995-10-19 1998-03-24 Lg Semicon Co., Ltd. Semiconductor bonding package
US5984691A (en) * 1996-05-24 1999-11-16 International Business Machines Corporation Flexible circuitized interposer with apertured member and method for making same
US6247228B1 (en) * 1996-08-12 2001-06-19 Tessera, Inc. Electrical connection with inwardly deformable contacts
US6094060A (en) * 1997-01-28 2000-07-25 International Business Machines Corporation Test head for applying signals in a burn-in test of an integrated circuit
US6174175B1 (en) * 1999-04-29 2001-01-16 International Business Machines Corporation High density Z-axis connector
JP2001004700A (en) * 1999-06-24 2001-01-12 Yamaichi Electronics Co Ltd Interposer board

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 16 8 May 2001 (2001-05-08) *

Also Published As

Publication number Publication date
AU2002211864A1 (en) 2003-02-17
WO2003010813A2 (en) 2003-02-06

Similar Documents

Publication Publication Date Title
WO2003019653A3 (en) Method for producing contacts and printed circuit packages
EP0844657A4 (en) Method for mounting semiconductor chip
CA2464055A1 (en) Interposer assembly for soldered electrical connections
WO2005091998A3 (en) Electrical connector in a flexible host
WO2005060401A3 (en) Direct contact power transfer pad and method of making same
WO2007109608A3 (en) Composite contact for fine pitch electrical interconnect assembly
TW200731512A (en) Phase changeable memory cell array region and method of forming the same
WO2010027597A3 (en) Electronic device socket
TW200718299A (en) Wiring board, wiring material, copper-clad laminate, and wiring board fabrication method
TW200610116A (en) Micro-electronic package structure and method for fabricating the same
US7572131B2 (en) Electrical interconnect system utilizing non-conductive elastomeric elements
WO2005039266A3 (en) Land grid array socket with diverse contacts
KR200312740Y1 (en) Integrated silicone contactor with an electric spring
WO2007001391A3 (en) Metalized elastomeric electrical contacts
TW200610470A (en) Method for fabricating electrical connecting member of circuit board
TW200601917A (en) Method for fabricating electrical connection structure of circuit board
KR101566173B1 (en) Semiconductor test socket and manufacturing method thereof
TW200637449A (en) Conducting bump structure of circuit board and fabricating method thereof
TW200610466A (en) Method for fabricating conductive bumps of a circuit board
WO2003073814A3 (en) Laminated socket contacts
WO2003010813A3 (en) Grid interposer
WO2004010749A3 (en) Interconnection system
WO2006019567A3 (en) Intermittent connection device
TW200507363A (en) Land grid array connector
CN107567206A (en) Double-side conduction construction processing method, linear circuit plate processing method and line source

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ PL PT RO RU SE SG SI SK SL TJ TM TR TT TZ UA US UZ VN YU ZA

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZW AM AZ BY KG KZ MD TJ TM AT BE CH CY DE DK ES FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW MR NE SN TD TG

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载