+

WO2003001600A3 - Speicherzelle, speicherzellenanordnung und herstellungsverfahren - Google Patents

Speicherzelle, speicherzellenanordnung und herstellungsverfahren Download PDF

Info

Publication number
WO2003001600A3
WO2003001600A3 PCT/DE2002/002141 DE0202141W WO03001600A3 WO 2003001600 A3 WO2003001600 A3 WO 2003001600A3 DE 0202141 W DE0202141 W DE 0202141W WO 03001600 A3 WO03001600 A3 WO 03001600A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
memory cell
producing
same
silicide
Prior art date
Application number
PCT/DE2002/002141
Other languages
English (en)
French (fr)
Other versions
WO2003001600A2 (de
Inventor
Herbert Palm
Josef Willer
Original Assignee
Infineon Technologies Ag
Herbert Palm
Josef Willer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Herbert Palm, Josef Willer filed Critical Infineon Technologies Ag
Priority to JP2003507893A priority Critical patent/JP3976729B2/ja
Priority to KR1020037016748A priority patent/KR100629383B1/ko
Priority to EP02742805A priority patent/EP1399972A2/de
Publication of WO2003001600A2 publication Critical patent/WO2003001600A2/de
Publication of WO2003001600A3 publication Critical patent/WO2003001600A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Auf den Source-/Drain-Bereichen (3, 4) von Speichertransistoren mit in Gräben angeordneten Gate-Elektroden (2) und ONO-Speicherschichtfolge (5, 6, 7) ist eine entsprechend den Bitleitungen streifenförmig strukturierte elektrisch leitende Schicht (8) oder Schichtfolge angeordnet, insbesondere ein Metallsilicid oder eine Polysiliziumschicht (14) mit darauf aufgebrachter metallhaltiger Schicht (15), die den ohmschen Widerstand der vergrabenen Bitleitungen reduziert. Das Metallsilicid ist bevorzugt Kobaltsilicid; die metallhaltige Schicht bevorzugt Wolframsilicid oder WN/W.
PCT/DE2002/002141 2001-06-21 2002-06-12 Speicherzelle, speicherzellenanordnung und herstellungsverfahren WO2003001600A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003507893A JP3976729B2 (ja) 2001-06-21 2002-06-12 メモリセル、メモリセル構成、および製造方法
KR1020037016748A KR100629383B1 (ko) 2001-06-21 2002-06-12 메모리 셀, 메모리 셀을 포함하는 장치 및 메모리 셀 제조 방법
EP02742805A EP1399972A2 (de) 2001-06-21 2002-06-12 Speicherzelle, speicherzellenanordnung und herstellungsverfahren

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10129958A DE10129958B4 (de) 2001-06-21 2001-06-21 Speicherzellenanordnung und Herstellungsverfahren
DE10129958.3 2001-06-21

Publications (2)

Publication Number Publication Date
WO2003001600A2 WO2003001600A2 (de) 2003-01-03
WO2003001600A3 true WO2003001600A3 (de) 2003-08-21

Family

ID=7688966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002141 WO2003001600A2 (de) 2001-06-21 2002-06-12 Speicherzelle, speicherzellenanordnung und herstellungsverfahren

Country Status (8)

Country Link
US (2) US6548861B2 (de)
EP (1) EP1399972A2 (de)
JP (1) JP3976729B2 (de)
KR (1) KR100629383B1 (de)
CN (1) CN100524774C (de)
DE (1) DE10129958B4 (de)
TW (1) TW567612B (de)
WO (1) WO2003001600A2 (de)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6897522B2 (en) * 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007B2 (en) 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
DE10225410A1 (de) * 2002-06-07 2004-01-08 Infineon Technologies Ag Verfahren zur Herstellung von NROM-Speicherzellen mit Grabentransistoren
US6777725B2 (en) * 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
DE10226964A1 (de) 2002-06-17 2004-01-08 Infineon Technologies Ag Verfahren zur Herstellung einer NROM-Speicherzellenanordnung
DE10229065A1 (de) * 2002-06-28 2004-01-29 Infineon Technologies Ag Verfahren zur Herstellung eines NROM-Speicherzellenfeldes
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
DE10232938B4 (de) * 2002-07-19 2005-05-04 Infineon Technologies Ag Verfahren zur Herstellung einer vergrabenen Bitleitung für einen Halbleiterspeicher
KR100468771B1 (ko) * 2002-10-10 2005-01-29 삼성전자주식회사 모스 트랜지스터의 제조방법
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
EP1641045A3 (de) 2002-11-12 2006-06-07 Micron Technology, Inc. Geerdete Gateelektrode und Isolationstechniken für reduzierte Dunkelströme im CMOS-Bildsensoren
US6888214B2 (en) * 2002-11-12 2005-05-03 Micron Technology, Inc. Isolation techniques for reducing dark current in CMOS image sensors
TW575945B (en) * 2002-12-17 2004-02-11 Nanya Technology Corp Method for fabricating a vertical NROM cell
KR100463184B1 (ko) * 2003-01-30 2004-12-23 아남반도체 주식회사 비휘발성 메모리 장치 제조 방법
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6794764B1 (en) * 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
DE10324550B4 (de) * 2003-05-30 2006-10-19 Infineon Technologies Ag Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
JP4334315B2 (ja) * 2003-10-10 2009-09-30 株式会社ルネサステクノロジ 半導体記憶装置の製造方法
US6965143B2 (en) * 2003-10-10 2005-11-15 Advanced Micro Devices, Inc. Recess channel flash architecture for reduced short channel effect
US7067362B2 (en) * 2003-10-17 2006-06-27 Chartered Semiconductor Manufacturing Ltd. Integrated circuit with protected implantation profiles and method for the formation thereof
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
KR100593599B1 (ko) * 2003-12-30 2006-06-28 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US20050251617A1 (en) * 2004-05-07 2005-11-10 Sinclair Alan W Hybrid non-volatile memory system
US7041545B2 (en) * 2004-03-08 2006-05-09 Infineon Technologies Ag Method for producing semiconductor memory devices and integrated memory device
JP2005277171A (ja) * 2004-03-25 2005-10-06 Toshiba Corp 半導体装置およびその製造方法
JP4377751B2 (ja) * 2004-06-10 2009-12-02 シャープ株式会社 クロスポイント構造の半導体記憶装置及びその製造方法
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7279770B2 (en) * 2004-08-26 2007-10-09 Micron Technology, Inc. Isolation techniques for reducing dark current in CMOS image sensors
KR100709823B1 (ko) * 2004-08-26 2007-04-23 주식회사 케이이씨 트렌치형 전계효과트랜지스터 및 그 제조 방법
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
KR100630725B1 (ko) * 2004-12-17 2006-10-02 삼성전자주식회사 매립된 비트라인을 가진 반도체 소자 및 그 제조방법
CN1838323A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 可预防固定模式编程的方法
US7186607B2 (en) * 2005-02-18 2007-03-06 Infineon Technologies Ag Charge-trapping memory device and method for production
US7365382B2 (en) 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20060223267A1 (en) * 2005-03-31 2006-10-05 Stefan Machill Method of production of charge-trapping memory devices
KR100715228B1 (ko) * 2005-06-18 2007-05-04 삼성전자주식회사 곡면 구조를 갖는 소노스 메모리 소자 및 그 제조방법
US8338887B2 (en) * 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US7399673B2 (en) 2005-07-08 2008-07-15 Infineon Technologies Ag Method of forming a charge-trapping memory device
US7804126B2 (en) 2005-07-18 2010-09-28 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7468299B2 (en) * 2005-08-04 2008-12-23 Macronix International Co., Ltd. Non-volatile memory cells and methods of manufacturing the same
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US8116142B2 (en) * 2005-09-06 2012-02-14 Infineon Technologies Ag Method and circuit for erasing a non-volatile memory cell
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US9159568B2 (en) * 2006-02-04 2015-10-13 Cypress Semiconductor Corporation Method for fabricating memory cells having split charge storage nodes
KR100762636B1 (ko) 2006-02-14 2007-10-01 삼성전자주식회사 네트워크 단말의 음성 검출 제어 시스템 및 방법
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
KR100732304B1 (ko) * 2006-03-23 2007-06-25 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US20070257293A1 (en) * 2006-05-08 2007-11-08 Josef Willer Semiconductor memory device and method for production of the semiconductor memory device
KR100739532B1 (ko) 2006-06-09 2007-07-13 삼성전자주식회사 매몰 비트라인 형성 방법
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US8344446B2 (en) * 2006-12-15 2013-01-01 Nec Corporation Nonvolatile storage device and method for manufacturing the same in which insulating film is located between first and second impurity diffusion regions but absent on first impurity diffusion region
US7859050B2 (en) * 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device
JP2008192803A (ja) * 2007-02-05 2008-08-21 Spansion Llc 半導体装置およびその製造方法
DE102007038925A1 (de) * 2007-08-17 2009-02-19 Qimonda Ag Verfahren zum Herstellen einer aktiven Vorrichtung einer Halbleiterspeichervorrichtung, und eine Halbleiterspeichervorrichtung
US7778073B2 (en) * 2007-10-15 2010-08-17 Qimonda Ag Integrated circuit having NAND memory cell strings
KR20100106017A (ko) * 2009-03-23 2010-10-01 삼성전자주식회사 리세스 채널 트랜지스터 및 이의 제조 방법
WO2011142850A2 (en) 2010-01-22 2011-11-17 The Regents Of The University Of California Etchant-free methods of producing a gap between two layers, and devices produced thereby
US9054133B2 (en) 2011-09-21 2015-06-09 Globalfoundries Singapore Pte. Ltd. High voltage trench transistor
US8999769B2 (en) * 2012-07-18 2015-04-07 Globalfoundries Singapore Pte. Ltd. Integration of high voltage trench transistor with low voltage CMOS transistor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731163A (en) * 1972-03-22 1973-05-01 United Aircraft Corp Low voltage charge storage memory element
JPH0412573A (ja) * 1990-05-02 1992-01-17 Matsushita Electron Corp 不揮発性半導体記憶装置およびその製造方法
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5392237A (en) * 1992-09-25 1995-02-21 Rohm Co., Ltd. Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array
EP0967654A1 (de) * 1998-06-26 1999-12-29 EM Microelectronic-Marin SA Nichtflüchtiges Halbleiterspeicherbauelement
US6127226A (en) * 1997-12-22 2000-10-03 Taiwan Semiconductor Manufacturing Company Method for forming vertical channel flash memory cell using P/N junction isolation

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3167457B2 (ja) * 1992-10-22 2001-05-21 株式会社東芝 半導体装置
DE19545903C2 (de) * 1995-12-08 1997-09-18 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
DE19600423C2 (de) * 1996-01-08 2001-07-05 Siemens Ag Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
DE19651108C2 (de) * 1996-04-11 2000-11-23 Mitsubishi Electric Corp Halbleitereinrichtung des Gategrabentyps mit hoher Durchbruchsspannung und ihr Herstellungsverfahren
US5768192A (en) 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
DE19638439C2 (de) * 1996-09-19 2000-06-15 Siemens Ag Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement und Herstellungsverfahren
JP3641103B2 (ja) 1997-06-27 2005-04-20 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6124608A (en) * 1997-12-18 2000-09-26 Advanced Micro Devices, Inc. Non-volatile trench semiconductor device having a shallow drain region
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
JP3223885B2 (ja) * 1998-08-17 2001-10-29 日本電気株式会社 電界効果型半導体メモリ装置およびその製造方法
US6194741B1 (en) * 1998-11-03 2001-02-27 International Rectifier Corp. MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6376315B1 (en) * 2000-03-31 2002-04-23 General Semiconductor, Inc. Method of forming a trench DMOS having reduced threshold voltage
DE10039441A1 (de) 2000-08-11 2002-02-28 Infineon Technologies Ag Speicherzelle, Speicherzellenanordnung und Herstellungsverfahren
US6445037B1 (en) * 2000-09-28 2002-09-03 General Semiconductor, Inc. Trench DMOS transistor having lightly doped source structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731163A (en) * 1972-03-22 1973-05-01 United Aircraft Corp Low voltage charge storage memory element
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
JPH0412573A (ja) * 1990-05-02 1992-01-17 Matsushita Electron Corp 不揮発性半導体記憶装置およびその製造方法
US5392237A (en) * 1992-09-25 1995-02-21 Rohm Co., Ltd. Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array
US6127226A (en) * 1997-12-22 2000-10-03 Taiwan Semiconductor Manufacturing Company Method for forming vertical channel flash memory cell using P/N junction isolation
EP0967654A1 (de) * 1998-06-26 1999-12-29 EM Microelectronic-Marin SA Nichtflüchtiges Halbleiterspeicherbauelement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 016, no. 162 (E - 1192) 20 April 1992 (1992-04-20) *

Also Published As

Publication number Publication date
US6548861B2 (en) 2003-04-15
DE10129958A1 (de) 2003-01-09
KR20040007749A (ko) 2004-01-24
CN100524774C (zh) 2009-08-05
CN1526170A (zh) 2004-09-01
US20030006428A1 (en) 2003-01-09
DE10129958B4 (de) 2006-07-13
JP3976729B2 (ja) 2007-09-19
US6794249B2 (en) 2004-09-21
US20030151091A1 (en) 2003-08-14
WO2003001600A2 (de) 2003-01-03
JP2004531084A (ja) 2004-10-07
KR100629383B1 (ko) 2006-09-29
TW567612B (en) 2003-12-21
EP1399972A2 (de) 2004-03-24

Similar Documents

Publication Publication Date Title
WO2003001600A3 (de) Speicherzelle, speicherzellenanordnung und herstellungsverfahren
WO2001065608A3 (en) Trench gate dmos field-effect transistor and method of making the same
TW200419788A (en) Flash memory having local SONOS structure using notched gate and manufacturing method thereof
EP1211729A3 (de) Komplementäre Transistoren mit jeweiligen Gattern aus Metall und entsprechendem Metallsilizid
EP1006589A3 (de) MOS-Dünnfilmtransistor und Herstellungsverfahren
WO2004038808A3 (en) Double and triple gate mosfet devices and methods for making same
MY111990A (en) Mos transistor and method for making the same
TW334639B (en) Semiconductor device and fabrication process therefor
TW200609997A (en) Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
WO2002080227A3 (en) Memory address and decode circuits with ultra thin body transistors
EP2264770A3 (de) Dünnschichttransistor und Herstellungsverfahren dafür
WO2002097889B1 (en) Semiconductor device and a method therefor
TW428231B (en) Manufacturing method of self-aligned silicide
TW200633074A (en) A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
WO2003054964A3 (en) Monos device having buried metal silicide bit line
GB2433839A (en) A method for making a semiconductor device with a high-k gate dielectric layer and silicide gate electrode
TW200500702A (en) Thin film transistor array panel and manufacturing method thereof
SG143938A1 (en) Accumulation mode multiple gate transistor
WO2004053982A3 (en) Semiconductor memory and fabrication method
EP1505658A3 (de) Nichtflüchtige Halbleiterspeicheranordnung mit zweifacher Schwebender Gatestruktur und Verfahren zur Herstellung
EP1369926A3 (de) Ferroelektrischer Speichertransistor und dessen Herstellungsverfahren
EP1191604A3 (de) Halbleiterspeicheranordnung
WO2000075967A3 (en) Method for fabrication of a low resistivity mosfet gate with thick metal silicide on polysilicon
TWI266360B (en) An integrated circuit device, microelectronic device and method of fabricating the same
EP1152470A3 (de) Halbleiterbauelement mit LDD-Struktur und dessen Herstellungsverfahren

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CA CN IL IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 028125134

Country of ref document: CN

Ref document number: 2003507893

Country of ref document: JP

Ref document number: 1020037016748

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2002742805

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2004107576

Country of ref document: RU

Kind code of ref document: A

WWP Wipo information: published in national office

Ref document number: 2002742805

Country of ref document: EP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载