WO2003092079A1

WO2003092079A1 - Enhanced cutoff frequency silicon germanium transistor

Info

Publication number: WO2003092079A1
Application number: PCT/US2002/013315
Authority: WO
Inventors: Robb Allen Johnson; Louis D. Lanzerotti
Original assignee: International Business Machines Corporation
Priority date: 2002-04-26
Filing date: 2002-04-26
Publication date: 2003-11-06
Also published as: EP1502308A1; EP1502308A4; CN1625811A; JP2005524233A; KR100754561B1; JP4223002B2; AU2002305254A1; KR20040103974A

Abstract

A bipolar transistor for a small signal amplifier that has improved Early voltages, and hence enhanced cutoff frequency. The SiGe layer (14) has a thickness (t) and a Ge content that is greater than the stability limit. The misfit dislocations do not create appreciable charge trapping sites, and do not extend into the overlying base/collector junction, such that performance is improved without yield degradation.

Description

ENHANCED CUTOFF FREQUENCY SILICON GERMANIUM

TRANSISTOR

Technical Field

The invention relates to silicon germanium (SiGe) heterojunction bipolar transistors

(HBTs).

Background Art It is generally known to form HBTs by using wafers that include one or more layers of silicon germanium (SiGe) on a silicon substrate. On such substrates, the germanium atoms create mechanical strain in the composite film due to the difference in lattice constant between the SiGe film and the silicon substrate. In the plane of the silicon substrate the larger lattice constant of the SiGe lattice is compressed onto the smaller lattice constant of the silicon substrate. In the plane perpendicular to the silicon substrate, the SiGe layer lattice constant is greater than that of the silicon substrate and thus is under tensile stress. This strain together with the Ge atom itself, creates a bandgap offset between the SiGe film and the underlaying native Si substrate. This bandgap offset provides the unique advantages of the SiGe HBT by creating a grading field in the base to enhance carrier diffusion across the base and thus improve transistor speed. SiGe HBTs have been used as transistors for small signal amplifiers (i.e. switching approximately 5 volts or less) to provide the switching speeds (above 1GHz) necessary for current wireless communications devices. One of the difficulties encountered by the inventors in utilizing SiGe HBTs for small signal amplifiers is that the common emitter output characteristics (i.e. the collector current versus the collector-emitter voltage) for such amplifiers generally exhibit poor Early voltage. "Early voltage" (N_A) is a characterization of the slope of these output characteristics, as indicated by the voltage at which the curves extrapolate to IC = 0 A. The more horizontal the curve, the greater the voltage at the IC = 0 extrapolation, and hence the "higher" the Early voltage. Fig. la (Prior Art) illustrates the Early voltage for SiGe HBTs without use of the invention. The individual curves indicate the output characteristics for different applied base voltages; the higher the curve, the higher the applied base voltage. Note that as applied base current increases, the slope of the curves become more vertical.

The inventors have noted that N_A is a key indicator of the current gain cutoff frequency (f_τ) for a SiGe HBT. ΝPΝ devices with a low N_A have been found to have low f_τ Devices that have reduced current gain cutoff frequencies provide suboptimal switching speeds.

Hence, a need has developed in the art for SiGe HBTs with enhanced Early voltage, which in turn enhances current gain cutoff frequency. Disclosure of the Invention It is thus an object of the invention to increase current gain cutoff frequencies for SiGe

HBTs.

In a first aspect, the invention is a SiGe HBT comprising a SiGe layer having a thickness and Ge concentration greater than the SiGe stability limit, and a plurality of misfit dislocations therein that do not create appreciable charge trapping sites. In another aspect, the invention is a SiGe HBT with an SiGe layer that has a thickness of at least approximately 70nm and a Ge concentration of at least 10% on a plurality of isolation structures, a base/collector junction above the isolation structures, and a plurality of misfit dislocations that do not appreciably extend above the base/collector junction. In yet another aspect, the invention is a bipolar transistor for a small signal amplifier that has a cutoff frequency of at least approximately 19 GHz, a SiGe layer having a thickness and a Ge content that is greater than the SiGe stability limit, a plurality of isolation regions abutting said collector region, and a base region formed on said collector region, said SiGe layer having a plurality of misfit dislocations therein adjacent said plurality of isolation regions and extending into said collector region without substantially extending into said base region.

In yet another aspect, the invention is a method of forming a bipolar transistor, comprising the steps of forming a plurality of isolation regions in a silicon substrate; forming a SiGe layer on said substrate and said isolation regions, said SiGe layer having a thickness and a Ge content that is greater than the SiGe stability limit; and doping said SiGe layer and the substrate with a first dopant to form a collector region, wherein said collector region comprises a plurality of misfit dislocations that do not substantially extend beyond said collector region into other portions of the bipolar transistor. Brief Description Of Drawings The foregoing and other structures and features of the present invention will become more apparent upon review of the detailed description of the invention as rendered below. In the description to follow, reference will be made to the accompanying drawings, in which Fig. la is plot of IC versus NCE for an experimental SiGe HBT; Fig. lb is plot of IC versus VCE for an SiGe HBT of the present invention;

Figure 2 shows a plot of collector current density versus cutoff frequency for ΝPΝs shown with the Early voltages shown in Figs, la and lb, respectively; Fig. 3 is a plot of SiGe concentration versus thickness, showing various experimental data points that include those of the invention, superimposed on the SiGe stability curves reported by prior art articles; Fig. 4 is a cross-sectional view of a SiGe HBT constructed in accordance with the teachings of a first embodiment of the invention;

Fig. 5 shows the Gummel plots (IC, IB vs NCE) of the ΝPΝs shown with the Early voltages shown in Figs, la and lb, respectively; Fig. 6 is a plot of normalized yield data for SiGe HBTs of the thicknesses shown by the data points in Fig. 3; and

Fig. 7 is a graph illustrating three embodiments of Ge concentration versus layer thickness for the SiGe layer of the invention. Best Mode For Carrying Out The Invention The present inventors found that Early voltage (and hence cutoff frequency) can be substantially enhanced by increasing the thickness of the SiGe layer. While in the prior art it is known to increase SiGe thickness for other purposes, thicker SiGe layers are generally avoided for fear of creating misfit dislocations. As will be explained in more detail below, the present inventors have found that when managed properly, misfit dislocations do not adversely affect the performance or yield of the resulting SiGe HBTs.

SiGe enhances charge mobility by introducing mechanical strain due to the lattice mismatches inherent in the Si-Ge compound. However, if there is too much Ge, or if the SiGe layer is too thick, the accepted wisdom in the art is that the resulting crystal dislocations will reduce both performance and yield. The performance penalty would be due to dislocations relieving the mechanical stresses that create the bandgap offsets that SiGe provides. The yield penalty would be due to the defects disturbing the crystallography of the substrate. In fact, this general understanding has become so widespread that it is generally acknowledged as the "Matthews-Blakesley stability limit" or the "Stiffler limit," in recognition of the researchers who first reported these interrelationships (Stiffler et al., Journal of Applied Physics, Vol. 71, No. 10, pp.

4820-4825; Matthews and Blakeslee, "Defects in Epitaxial Multilayers," Journal of Crystal Growth 27 pp. 118-125 (1974)). For ease of future reference, these results will be referred to as the "SiGe stability limits." The different SiGe stability limits reported by Matthews-Blakesley and Stiffler are plotted in Fig. 3, which shows the reported optimal relationships between SiGe thickness and Ge concentration.

Much research has focused on various methodologies of exceeding the SiGe stability limits by eliminating such misfit dislocations. See U.S. Patent 5,256,550 to Laderman et al., discussing the formation of thicker SiGe layers without misfit dislocations by the deposition of a first SiGe layer using low temperature epitaxial techniques, then a capping Si layer, followed by appropriate thermal cycling. In this structure the overlying Si layer is necessary to preserve the strain of the SiGe layer without creating misfit dislocations. A paper by K. Schonenberg et al entitled "The Stability of SiGe Strained Layers on Small Area Trench Isolated Silicon Islands," Electrochemical Society Proceedings, Vol. 96-4, Proceedings of the 4^th International Symposium on Process Physics and Modeling in Semiconductor Technology, Los Angeles, CA May 5-10 1996, pp. 296-308, reports that observed defect densities decrease as the size of the SiGe area bounded by isolation decreases, and as the processing of the shallow trench isolation is modified to reduce stress. This area dependency is also reported in Nescan, "Selective Epitaxial Growth of Strained SiGe/Si for Optoelectronic Devices," Materials Science and Engineering B, Solid-State Materials for Advanced Technology, Vol. 51, No. 1- 3, pp. 166-69 (1998).

Another reason that misfit dislocations in the active region of a bipolar transistor are avoided is to prevent creation of charge trapping sites. These charge trapping sites, if present in sufficient quantities, will reduce minority carrier lifetime. In a typical bipolar transistor, this results in reduced current gain, which is not desired in small signal applications. However, in power amplifier applications reduced current gain can be tolerated. Thus, U.S. Patent 5,097,308 teaches the intentional introduction of dislocations between 9-20 um from the SiGe-Si interface to provide traps that induce greater recombination of minority carriers, so as to reduce minority carrier lifetime in a bipolar power rectifier. Low minority carrier lifetime is desirable in bipolar rectifiers to increase switching speed. The switching speed of a bipolar transistor is determined by how fast charge in the base is removed. One charge removal process is recombination, whereby electrons and holes recombine at charge trapping sites to turn the transistor off. However, for standard SiGe bipolar transistor small signal amplification applications, the reduced current gain which accompanies this reduced minority carrier lifetime is not desirable (and in fact would normally be avoided; as stated above, the resulting reduction in switching speed would be incompatible with the goal of increased cutoff current gain frequency).

The inventors have found that by forming a SiGe layer at a thickness/concentration combination greater than the SiGe stability curves, Early voltages are substantially improved, increasing cutoff frequencies, without creating misfit dislocations that significantly relieve the mechanical stresses that create the bandgap offsets that SiGe provides, and without significantly disturbing the crystallography of the substrate. Fig. 3 illustrates the SiGe thicknesses and concentrations that were used to provide the data reported herein. For the sake of comparison Ge concentration was fixed at 10%, and thickness was increased. Note that the first two data points are at or below the SiGe stability curves; these devices provided the Early voltage results shown in Fig. la . The SiGe thicknesses of the invention start at approximately 70nm. As shown in Fig. 4, the SiGe HBT of the invention is formed on a monocrystalline silicon substrate 10 having shallow trench isolation regions (STI) 12 therein. An SiGe layer 14 is epitaxially grown using conventional techniques on the substrate 10, to a thickness t of at least 40nm and a Ge concentration of at least approximately 10%.

After suitable doping to form a collector region 14C, the SiGe layer is insitu doped during growth with boron to form a base region 14B (not shown to scale laterally). Note that as a practical matter boron from the base region can diffuse deeper into the SiGe layer during various processing thermal cycles, from a depth X to a depth Y into the SiGe layer 14. As such, the resulting base/collector junction can be at JA or JB.

The emitter electrode (not shown) is subsequently formed using well-known techniques to complete formation of the HBT. The HBT of the invention is then connected to other HBTs formed on the substrate to form integrated circuits. Fig. lb illustrates the collector current versus the collector-emitter voltage for the SiGe HBT of the invention. Note the substantial improvement in Early voltage (the plots are far more horizontal for all applied base voltages, meaning collector current is constant for increased collector- emitter voltages).

Figure 2 shows a plot of collector current density versus cutoff frequency for (a) an NPN with Early voltages as shown in Fig. la (indicated by the dashed line); and (b) the NPN with the Early voltages shown in Fig. lb (indicated by the solid line). Note the increase in cutoff frequency for transistors having the improved Early voltages of the invention. The peak Ft is approximately 19 GHz. Note also the increase in cutoff frequency occurs over a wider range of collector current. An aspect of the invention is that these gains in Early voltage and cutoff frequency do not come at the expense of dislocations that decrease performance (by charge trapping) or yield (by crystal dislocations).

Turning first to charge trapping, note first the observed increase in cutoff frequency shown in Fig. 4; if appreciable charge trapping was induced by the misfit dislocations, the resulting carrier recombination would decrease cutoff frequency, not increase it. Moreover, Fig. 5 shows the Gummel plots (IC, IB vs VCE) of the NPNs shown with the Early ^voltages shown in Figs, la and lb, respectively. Note that the IB and IC curves in the Gummel plots have ideal slopes (n~l (n is a measure of ideality) or 60 mV/decade at room temperature) which indicates that there was no substantial charge trapping induced by the misfit dislocations formed as part of the thicker SiGe layer. One of the consequences of avoiding increased charge trapping is that as shown in Figs, la and lb, these higher cutoff frequencies are achieved without a corresponding reduction in the breakdown voltage (B V_CE0) of the device; or, to put it another way, the cutoff frequency Ft for a device with a given breakdown voltage B Vceo increases with increasing SiGe thickness. This becomes particularly important for device designs in which high breakdown voltage devices are required (such as in power amplifiers or read heads) .

Now considering yields, Fig. 6 shows a plot of normalized yields for SiGe HBTs of the invention, for different SiGe thicknesses. The first region shown (thickness of 300 angstroms, Ge concentration of 10%) is approximately at the upper limit of the SiGe stability curves (see Fig. 2). Note that as the thickness increases above the SiGe stability curves at Ge concentration of 10%, yield does not substantially change. This illustrates that the misfit dislocations in the SiGe layers of the invention do not significantly disturb the crystallography of the substrate, because if they did yield would be declining with thicker SiGe layer thicknesses. Fig. 7 is a plot of Ge concentration percentage versus depth of a 70nm thick SiGe layer, for three embodiments of the present invention. In a first embodiment as illustrated by curve A, the Ge concentration in the SiGe layer of the invention is approximately 10% throughout the thickness of the 40nm-thick SiGe film. This embodiment produced the collector current versus the collector-emitter voltage plot of the invention as shown by the solid lines of Fig. 3. In a second embodiment as illustrated by curve B, the Ge concentration in the SiGe layer of the invention is approximately 10% throughout the thickness of the 70nm-thick film. The first and second embodiments produced the yield data shown in Fig. 6. In a third embodiment, as illustrated by curve C, the Ge concentration in the SiGe layer of the invention is approximately 25% at the upper surface of the SiGe layer and for the first third of its thickness (approximately 23nm for a 70nm-thick SiGe film), then the Ge percentage is dropped in a substantially linear manner from 25% to 10% over the second third of the thickness of the SiGe film, then the concentration is at 10% for the remaining thickness of the film. By reducing the content at the lower surface to 10% the results in terms of misfit dislocations, yield and performance should be the same as what was observed for the first two embodiments of the invention.

In a fourth embodiment of the invention (not shown in Fig. 7), the SiGe layer is 150nm thick, and has a Ge concentration of approximately 10% throughout this thickness. The inventors found that even at this thickness and Ge content the misfit dislocations had the general properties reported herein. Based on these results, the inventors believe the SiGe layer could be even thicker than 150nm and still provide the reported properties.

The results reported herein indicate there is no fundamental reason why SiGe concentration and thickness needs to be limited by concerns regarding the creation of dislocations.

As such, it would appear that the only natural limit to the percentage of Ge concentration is the point at which too little or too much stress would be induced in the underlaying Si layer; the inventors believe that a concentration below approximately 5% would not provide sufficient stress to induce a reasonable amount of charge mobility improvement, and a concentration above approximately 35% may either provide prohibitive stress in the thickness regimes (approximately 70nm and above) that appear to optimize Early voltage or reduce yeilds due to hillock formation on the upper surface of the SiGe layer.

The inventors found that the misfit dislocations in the SiGe layer of the invention were located for the most part in the area of the STI edges 12 A, 12B shown in Fig. 3. The dislocations tended to run horizontally, along the SiGe/Si interface shown by dashed line 10 A. Significantly, practically none were observed extending into the base/collector junction JA or JB, as the case may be, and none we observed extending into the emitter region. Moreover, as previously discussed, the ideal Gummel plots indicate that the resulting dislocations did not establish appreciable charge trapping sites. Thus, as opposed to the teachings in the art, the inventors have found that SiGe layers that have misfit dislocations can improve performance without degrading yield. As opposed to the teachings in the art, the inventors have found that the large numbers of misfit dislocations, in and of themselves, are not determinative of performance or yield. Rather, the key is that the dislocations do not create appreciable charge trapping, and do not extend in large numbers past the base/collector junction.

While the invention has been described above with reference to a particular set of embodiments, the invention is not to be interpreted as limited thereto. Modifications may be made to the described embodiments without departing from the spirit and scope of the invention as claimed. For example, while particular Ge concentrations, concentration gradients, and SiGe thicknesses have been taught, other concentrations, gradients, and/or thicknesses could be used so long as they provide at least the same general results as those reported herein.

Industrial Applicability

The invention has applicability to electrical circuits and devices, especially those used in communication systems.

Claims

CLAIMSWhat we claim is:

1. A silicon germanium (SiGe) heterojunction bipolar transistor (HBT) comprising a SiGe layer (14) having a thickness (t) and Ge concentration greater than the SiGe stability limit, and a plurality of misfit dislocations therein that do not create appreciable charge trapping sites.

2. The HBT of claim 1, wherein said SiGe layer (14) has a base/collector junction, and wherein said plurality of misfit dislocations do not appreciably extend above the base/collector junction.

3. The HBT of claim 1 , having a SiGe layer (14) that has a thickness (t) of at least approximately 70nm and a Ge concentration of at least 10% on a plurality of isolation structures (12), a base/collector junction above the isolation structures (12), and a plurality of misfit dislocations that do not appreciably extend above the base/collector junction.

4. The HBT of claim 3, wherein said plurality of misfit dislocations do not create appreciable charge trapping sites.

5. The HBT of claim 1 wherein said HBT has a cutoff frequency of at least approximately 19 GHz, a plurality of isolation regions (12) abutting said collector region, and a base region formed on said collector region, wherein said misfit dislocations of said SiGe layer therein are located adjacent to said plurality of isolation regions (12) and extending into said collector region without substantially extending into said base region.

6. The transistor of claim 5, wherein said SiGe layer (14) has a Ge concentration of at least 10%.

7. The transistor of claim 6, wherein said SiGe layer (14) has a thickness (t) of at least approximately 70nm.

8. The transistor of claim 6, wherein said SiGe layer (14) has a thickness (t) of at least approximately 150nm.

9. The transistor of claim 6, wherein said SiGe layer (14) has a Ge concentration that varies within said SiGe layer (14).

10. The transistor of claim 9, wherein said SiGe layer (14) has a Ge concentration of a higher value at an upper surface thereof and a lower value at a lower surface thereof.

11. The transistor of claim 10, wherein said Ge concentration is at a first value in an upper portion of said SiGe layer (14), a second value less than said first value in a lower portion of said SiGe film, and a value that varies from said first value to said second value in a middle portion of said SiGe layer ( 14).

12. The transistor of claim 11, wherein said higher value is approximately 25%, and said lower value is approximately 10%.

13. The transistor of claim 11, wherein said Ge concentration is approximately 25% in an upper third of a thickness (t) of said SiGe layer (14).

14. The transistor of claim 13, wherein said Ge concentration decreases in a general linear fashion from 25% to 10% in an intermediate third of said thickness (t) of said SiGe layer (14).

15. The transistor of claim 14, wherein said Ge concentration is approximately 10% in an lower third of said thickness (t) of said SiGe layer (14).

16. A method fabricating a bipolar transistor according to any of Claims 1-15 to have increased Ft and having a given BVceo, comprising the steps of: forming a plurality of isolation regions (12) in a silicon substrate (10); forming a SiGe layer (14) on said substrate (10) and said isolation regions (12), said SiGe layer (14) having a thickness (t) and a Ge content that is greater than the SiGe stability limit; and doping said SiGe layer (14) and the substrate (10) with a first dopant to form a collector region; wherein said collector region comprises a plurality of misfit dislocations that do not substantially extend beyond said collector region into other portions of the bipolar transistor.

17. The method of claim 16, wherein said SiGe layer (14) has a Ge concentration of between 5 % and 35 % .

18. The method of claim 16, wherein said SiGe layer (14) has a Ge concentration of at least approximately 10%.

19. The method of claim 16, wherein said SiGe layer (14) has a thickness (t) of at least approximately 70nm.

20. The method of claim 19, wherein said SiGe layer ( 14) has a thickness (t) of at least approximately 150nm.

21. The method of claim 17, wherein said SiGe layer (14) has a Ge concentration that varies within said SiGe layer (14).

22. The method of claim 21, wherein said SiGe layer (14) has a Ge concentration of a higher value at an upper surface thereof and a lower value at a lower surface thereof.

23. The method of claim 21, wherein said Ge concentration is at a first value in an upper portion of said SiGe layer (14), a second value less than said first value in a lower portion of said SiGe layer (14), and a value that varies from said first value to said second value in a middle portion of said SiGe layer (14).