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WO2003083955A1 - Photovoltaic element and method of manufacturing the same - Google Patents

Photovoltaic element and method of manufacturing the same Download PDF

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Publication number
WO2003083955A1
WO2003083955A1 PCT/JP2003/003507 JP0303507W WO03083955A1 WO 2003083955 A1 WO2003083955 A1 WO 2003083955A1 JP 0303507 W JP0303507 W JP 0303507W WO 03083955 A1 WO03083955 A1 WO 03083955A1
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WO
WIPO (PCT)
Prior art keywords
film
photovoltaic element
portions
conductive semiconductor
type
Prior art date
Application number
PCT/JP2003/003507
Other languages
French (fr)
Inventor
Takahiro Mishima
Naoki Ishikawa
Original Assignee
Ebara Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corporation filed Critical Ebara Corporation
Priority to AU2003217486A priority Critical patent/AU2003217486A1/en
Publication of WO2003083955A1 publication Critical patent/WO2003083955A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photovoltaic element such as a solar cell, and more particularly to a photovoltaic element such as a solar cell having a p-n junction and positive and negative electrodes disposed on a rear surface opposite to a light incident surface.
  • the present invention also relates to a method of manufacturing such a photovoltaic element.
  • Solar cells manufactured in mass production are mostly made of amorphous silicon materials . While such solar cells can be manufactured at low cost, they have a low efficiency of generating electric power.
  • a solar cell having a p-n junction formed by a monocrystalline or polycrystalline silicon substrate and an amorphous silicon film of a conductivity type opposite to the silicon substrate onto which the amorphous silicon film is adhered.
  • a solar cell having a junction formed by a combination of a crystalline silicon substrate and an amorphous silicon film photo carriers are recombined with each other due to interface state levels being produced at an interface between semiconductor layers having different conductivity types. Therefore, it has been difficult to achieve reliable performance.
  • a solar cell has a transparent electrode on a light incident surface of a substrate and a rear electrode on a rear surface opposite to the light incident surface and produces photovoltaic power between the transparent electrode and the rear electrode.
  • shielding loss of light is caused by the transparent electrode on the light incident surface, so that the solar cell has a limited efficiency of generating electric power.
  • a rear-junction type solar cell in which a transparent electrode is not disposed on a light incident surface of a substrate.
  • a p-n junction is formed near a rear surface opposite to the light incident surface, and electrodes are connected to p-type and n-type layers, respectively.
  • the present invention has been made in view of the above drawbacks. It is, therefore, an object of the present invention to provide a photovoltaic element such as a solar cell which includes a silicon substrate with high quality to such an extent that carriers have long lifetime and has a high efficiency of generating electric power, and a method of manufacturing such a photovoltaic element through a low-temperature process.
  • a rear-junction type photovoltaic element in which a p-n junction and electrodes are formed on a rear surface opposite to a light incident surface (front surface) of a (silicon) semiconductor silicon substrate.
  • the photovoltaic element has an intrinsic semiconductor film having a thickness ranging from 0.1 nm to 50 nm.
  • the intrinsic semiconductor film is disposed on the rear surface of the semiconductor substrate.
  • P-type conductive semiconductor portions and n-type conductive semiconductor portions are disposed on the intrinsic semiconductor film, respectively.
  • a first electrode and a second electrode are connected to the p-type portions and the n-type portions, respectively.
  • the first electrode and the second electrode should preferably have comb-like shapes, respectively, and these comb-like shapes should preferably be alternately disposed.
  • the first electrode has a first set of teeth and said second electrode has a second set of teeth.
  • the teeth of the first set of teeth are alternately disposed between the teeth of the second set of teeth.
  • the semiconductor substrate may comprise a onocrystalline or polycrystalline semiconductor substrate.
  • the intrinsic semiconductor film may comprise an amorphous silicon film, a film having a hetero-structure in which amorphous silicon and microcrystalline silicon are mixed with each other, an amorphous silicon carbide film, or a film having a hetero-structure in which amorphous silicon carbide and microcrystalline silicon are mixed with each other. It is desirable that the intrinsic semiconductor film is formed by plasma CVD or, particularly, catalytic CVD.
  • An antireflection film may be disposed on the light incident surface of the semiconductor substrate .
  • a layer having a conductivity type opposite to the semiconductor substrate may be disposed on the light incident surface of the semiconductor substrate.
  • Another intrinsic semiconductor film may be disposed between the light incident surface of the semiconductor substrate and the antireflection film.
  • an intrinsic semiconductor film is formed by plasma CVD or catalytic CVD.
  • P-type and n-type portions and electrodes are formed on the intrinsic semiconductor film by a low-temperature process.
  • the photovoltaic element can maintain a silicon substrate with high quality to such an extent that carriers have long lifetime .
  • a rear-junction type photovoltaic element according to the present invention has a good efficiency of photovoltaic conversion, e.g., a high efficiency of generating electric power .
  • the substrate can be maintained with high quality, and productivity of forming films can relatively be enhanced.
  • FIG. 1 is a schematic view showing a photovoltaic element according to a first embodiment of the present invention
  • FIG. 2A is a schematic view showing a catalytic CVD apparatus according to an embodiment of the present invention
  • FIG. 2B is a schematic view showing a plasma CVD apparatus according to an embodiment of the present invention
  • FIG. 3 is a bottom view of the photovoltaic element shown in FIG. 1;
  • FIG. 4 is a schematic view showing a photovoltaic element according to a second embodiment of the present invention.
  • FIG. 5 is a schematic view showing a photovoltaic element according to a third embodiment of the present invention.
  • FIGS. 6A through 6F illustrate a process of manufacturing a photovoltaic element shown in FIG. 4.
  • FIG. 1 shows a photovoltaic element according to a first embodiment of the present invention .
  • the photovoltaic element may be used as a solar cell .
  • the photovoltaic element comprises a rear-junction type solar cell in which a p-n junction and electrodes are disposed on an n-type crystalline semiconductor substrate 11.
  • the crystalline semiconductor substrate 11 may comprise a monocrystalline or polycrystalline semiconductor substrate.
  • the crystalline semiconductor substrate 11 may comprise a monocrystalline silicon substrate formed of a dendritic web having a thickness of 100 ⁇ m and doped into an n-type semiconductor with impurities.
  • the crystalline semiconductor substrate 11 may comprise a ribbon-like polycrystalline silicon substrate.
  • the photovoltaic element has an intrinsic semiconductor film 12 disposed on a rear surface of the crystalline semiconductor substrate 11.
  • the monocrystalline or polycrystalline silicon substrate 11 can be produced as follows. A silicon material is melted in a crucible maintained at a predetermined temperature. A seed crystal is pulled up along a crystal axis of a predetermined orientation from the crucible to grow a thin ribbon-like (sheet-like) crystal. The thin crystal is clamped on an endless belt and continuously pulled up to form a long crystal. The produced long crystal is cut off into proper dimensions to produce a rectangular sheet-like monocrystalline or polycrystalline silicon substrate having a thickness of 150 ⁇ m or less. Such a method of producing monocrystalline or polycrystalline silicon substrate is disclosed in Japanese patent publication No. 2002-087899 assigned to the assignee of this patent application, the disclosure of which is hereby incorporated by reference.
  • the intrinsic semiconductor film 12 is formed as an extremely thin amorphous layer having a thickness ranging from 0.1 nm to 50 nm.
  • the intrinsic semiconductor film may comprise an amorphous silicon film, a film having a hetero-structure in which amorphous silicon and microcrystalline silicon are mixed with each other, an amorphous silicon carbide film, or a film having a hetero-structure in which amorphous silicon carbide and microcrystalline silicon are mixed with each other.
  • the intrinsic semiconductor film is an electrically neutral film. With the intrinsic semiconductor film being interposed between p-type and n-type layers, hydrogen passivation can effectively be performed, and electrical characteristics can be improved. For example, an open-circuit voltage can be increased.
  • the intrinsic semiconductor film 12 should preferably be formed by catalytic CVD or plasma CVD.
  • FIG. 2A shows a catalytic CVD apparatus.
  • the catalytic CVD apparatus has a gas supply device 21 for supplying gases, a high- temperature catalyst 22, and a substrate holder 24 for holding a substrate 23 to be processed. These components are housed in a vacuum chamber capable of being depressurized.
  • the high- temperature catalyst 22 is used to form a CVD film on a surface of the substrate 23 by heating and activating the gases supplied from the gas supply device 21.
  • a wire made of tungsten, molybdenum, or the like which is heated to a temperature ranging from 1500 to 2400 °C may be used as a high-temperature catalyst 22.
  • FIG. 2B shows a plasma CVD apparatus.
  • the plasma CVD apparatus has electrodes 25 and 26 and a high frequency power supply 27 for applying a high frequency voltage between the electrodes 25 and 26.
  • gas molecules 28 to be deposited are formed into a plasma and vibrated in directions shown by arrows in FIG. 2B. In this manner, a CVD film is deposited on a surface of a substrate 23 to be processed.
  • the catalytic CVD apparatus shown in FIG. 2A causes almost no damage to a substrate by a plasma, has a simpler and less expensive structure, and can easily be made larger in size as compared to the plasma CVD apparatus shown in FIG. 2B.
  • the catalytic CVD apparatus can achieve a relatively high deposition rate of 5 to 10 nm/sec, for example, and produce a high-quality film of an amorphous silicon film or a microcrystalline silicon film in a relatively short time.
  • the photovoltaic element has p-type portions 13 and n-type portions 14, each formed by doping with impurities. These p-type portions 13 and n-type portions 14 are alternately disposed on a surface of the intrinsic semiconductor film 12.
  • the p-type portions 13 and n-type portions 14 comprise amorphous conductive silicon layers formed, for example, by catalytic CVD or plasma CVD, for example, with a metallic mask. Electrodes 15 and 16 are disposed on the p-type portions 13 and n-type portions 14, respectively. For example, conductive paste of silver or the like is screen-printed into a pattern on the p-type portions 13 and n-type portions 14 and is then hardened by heating to form electrodes 15 and 16. An insulating film 17 made of polyimide resin or the like is disposed between the p-type portions 13 and n-type portions 14. An antireflection film 18 made of SiN may be formed on the light incident surface of the silicon substrate 11.
  • FIG. 3 schematically shows a rear surface of the photovoltaic element of FIG.1.
  • the electrode 15 connected to the p-type portions 13 has a comb-like shape
  • the electrode 16 connected to the n-type portions 14 has a comb-like shape.
  • the comb-like shape of the electrode 15 and the comb-like shape of the electrode 16 are alternately disposed adjacent to and in parallel with each other.
  • the electrode 15 has a number of teeth connected to a bus bar 15a, and the electrode
  • bus bar 16a has a number of teeth connected to a bus bar 16a. In this photovoltaic element, electric power is generated between the bus bars 15a and 16a.
  • the photovoltaic element has a thin intrinsic amorphous silicon layer (semiconductor film) 12 formed on the rear surface of the substrate 11 by catalytic CVD or plasma CVD.
  • the solar cell has p-type portions 13 and n-type portions 14 formed on a surface of the intrinsic semiconductor film 12.
  • the p-type portions 13 and n-type portions 14 are also formed by catalytic CVD or plasma CVD and doped with p-type and n-type impurities, respectively.
  • the intrinsic semiconductor film 12, the p-type portions 13 and n-type portions 14 may be formed by a low-temperature process such as catalytic CVD or plasma CVD. Further, with respect to forming an insulating film
  • each pattern is formed by screen-printing or the like and hardened by heating at a relatively low temperature of 400°C or less.
  • the photovoltaic element is manufactured in low-temperature processes at temperatures of 400°C or less. Therefore, the silicon substrate 11 can be maintained with high quality to such an extent that carriers have long lifetime. Since the photovoltaic element has no transparent electrodes on the front surface, it has a good efficiency of photovoltaic conversion, e.g. , a high efficiency of generating electric power, and does not have shielding loss.
  • the temperature of the substrate becomes in a range of from about 100°C to about 400°C, and thus the catalytic CVD is a low-temperature process. Therefore, the silicon substrate 11 is not damaged by catalytic CVD. Further, defects within the crystal can be corrected by a high- concentration hydrogen radical to reduce defective interface state levels.
  • the catalytic CVD causes no damage to a substrate by a plasma, unlikely plasma CVD. Thus, the silicon substrate
  • FIG. 4 shows a photovoltaic element according to a second embodiment of the present invention.
  • the photovoltaic element in the second embodiment has the same structure as the photovoltaic element shown in FIG. 1 except that an intrinsic semiconductor film 20 is interposed between the light incident surface of the semiconductor substrate 11 and the antireflection film 18.
  • the intrinsic semiconductor film 20 should preferably be formed simultaneously with the intrinsic semiconductor film
  • the side surfaces of the semiconductor substrate 11 should preferably be covered with an intrinsic semiconductor film.
  • an intrinsic semiconductor film By covering the light incident surface and the side surfaces of the crystalline silicon substrate 11 with intrinsic semiconductor films, interface state levels can be reduced, and electrical characteristics can be improved.
  • FIG. 5 shows a photovoltaic element according to a third embodiment of the present invention.
  • the photovoltaic element in the third embodiment has the same structure as the photovoltaic element shown in FIG.4 except that a layer 19 having a conductivity type opposite to the substrate 11 is interposed between the light incident surface of the substrate 11 and the intrinsic semiconductor film 20.
  • the layer 19 is p-type. Since the layer 19 has a conductivity type opposite to the substrate 11, an internal electric field in the substrate 11 can prevent carriers from being recombined with each other. Therefore, it is possible to improve electrical characteristics such as an efficiency of photovoltaic conversion.
  • an n-type monocrystalline or polycrystalline silicon substrate 11 is prepared.
  • the silicon substrate 11 may be formed of dendritic web crystal or ribbon-like polycrystal .
  • the surfaces of the silicon substrate 11 are cleaned to remove oxide films or the like. Thus, the surfaces of the silicon substrate 11 are cleansed.
  • catalytic CVD is performed to form intrinsic amorphous silicon films 12 and 20 on front and rear faces, respectively, of the silicon substrate 11.
  • the intrinsic amorphous silicon films 12 and 20 should preferably have thicknesses ranging from 0.1 nm to 50 nm, for example, about 10 nm.
  • the intrinsic amorphous silicon films are formed under the following conditions.
  • catalytic CVD is performed to form amorphous conductive silicon portions 33 on the intrinsic amorphous silicon film 12.
  • the conductive silicon portions 33 have thicknesses of about 30 nm.
  • the conductive silicon portions 33 are then doped to form p-type portions 13.
  • the p-type portions 13 are formed under the following conditions.
  • amorphous conductive silicon portions 34 are formed on the intrinsic amorphous silicon film
  • a metallic mask is used for forming a number of parallel comb-like patterns of the amorphous conductive silicon portions
  • the conductive silicon portions 34 have thicknesses of about 30 nm.
  • the conductive silicon portions 34 are then doped to form n-type portions 14.
  • the n-type portions 14 are formed under the following conditions.
  • insulating portions (protective portions) 17 are formed on the intrinsic amorphous silicon film 12.
  • paste of polyimide resin is embedded into between the conductive silicon portions 13 and 14 by screen-printing and hardened by heating at a temperature of 250 °C or less.
  • the insulating portions (protective portions) 17 can improve resistance to weather and to soft soldering.
  • silver paste is applied on the conductive silicon portions 13 and 14 by screen-printing and hardened by heating at a relatively low temperature of 250°C or less to form comb-like electrodes 15 and 15a, 16 and 16a (see FIG. 3) disposed alternately on the conductive silicon portions 13 and 14, respectively.
  • the antireflection film should preferably be formed on the intrinsic semiconductor film 20.
  • the antireflection film may be formed as an Si 3 N 4 film by high frequency sputtering, For example.
  • the antireflection film may have a thickness of about 60 nm.
  • a diffusion layer 19 having a conductivity type opposite to that of the substrate 11 may be formed between the light incident surface of the substrate 11 and the intrinsic semiconductor film 20.
  • the diffusion layer 19 may be formed on the silicon substrate 11 by thermomigration, ion implantation, or the like.
  • the present invention is suitable for use in a photovoltaic element such as a solar cell having a p-n junction and positive and negative electrodes disposed on a rear surface opposite to a light incident surface.

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  • Photovoltaic Devices (AREA)

Abstract

In a rear-junction type photovoltaic element, a p-n junction and electrodes (15, 16) are formed on a rear surface opposite to a light incident surface of a (semiconductor) silicon substrate (11). The photovoltaic element has an intrinsic semiconductor film (12) having a thickness ranging from 0.1 nm to 50 nm. The intrinsic semiconductor film (12) is disposed on the rear surface of the semiconductor substrate (11). P-type conductive semiconductor portions (13) and n-type conductive semiconductor portions (14) are disposed on the intrinsic semiconductor film (12), respectively. A first electrode (15) and a second electrode (16) are connected to the p-type conductive semiconductor portions (13) and the n-type conductive semiconductor portions (14), respectively.

Description

DESCRIPTION
PHOTOVOLTAIC ELEMENT AND METHOD OF MANUFACTURING THE SAME
Technical Field The present invention relates to a photovoltaic element such as a solar cell, and more particularly to a photovoltaic element such as a solar cell having a p-n junction and positive and negative electrodes disposed on a rear surface opposite to a light incident surface. The present invention also relates to a method of manufacturing such a photovoltaic element.
Background Art
Solar cells manufactured in mass production are mostly made of amorphous silicon materials . While such solar cells can be manufactured at low cost, they have a low efficiency of generating electric power.
For improving an efficiency of photovoltaic conversion, there has been developed a solar cell having a p-n junction formed by a monocrystalline or polycrystalline silicon substrate and an amorphous silicon film of a conductivity type opposite to the silicon substrate onto which the amorphous silicon film is adhered. In a solar cell having a junction formed by a combination of a crystalline silicon substrate and an amorphous silicon film, photo carriers are recombined with each other due to interface state levels being produced at an interface between semiconductor layers having different conductivity types. Therefore, it has been difficult to achieve reliable performance.
In view of such a drawback, it has been attempted to form an intrinsic amorphous semiconductor film at an interface between a crystalline silicon substrate and an amorphous silicon film to reduce interface state levels.
Generally, a solar cell has a transparent electrode on a light incident surface of a substrate and a rear electrode on a rear surface opposite to the light incident surface and produces photovoltaic power between the transparent electrode and the rear electrode. In this case, shielding loss of light is caused by the transparent electrode on the light incident surface, so that the solar cell has a limited efficiency of generating electric power. In view of such a drawback, there has been developed a rear-junction type solar cell in which a transparent electrode is not disposed on a light incident surface of a substrate. Specifically, in a rear-junction type solar cell, a p-n junction is formed near a rear surface opposite to the light incident surface, and electrodes are connected to p-type and n-type layers, respectively.
In such a rear-junction type solar cell, carriers produced near a front surface of the semiconductor substrate are required to reach a p-n junction disposed near the rear surface of the substrate. Therefore, a high-quality crystalline semiconductor substrate is required for a rear-junction type solar cell so that carriers have long lifetime. However, in a manufacturing process of a rear-junction type solar cell, high-temperature processes such as thermal oxidation and thermomigration are performed, so that lifetime of carriers is shortened. Therefore, it has been difficult to achieve reliable performance, e.g. , a reliable efficiency of generating electric power.
Disclosure of Invention
The present invention has been made in view of the above drawbacks. It is, therefore, an object of the present invention to provide a photovoltaic element such as a solar cell which includes a silicon substrate with high quality to such an extent that carriers have long lifetime and has a high efficiency of generating electric power, and a method of manufacturing such a photovoltaic element through a low-temperature process.
According to a first aspect of the present invention, there is provided a rear-junction type photovoltaic element in which a p-n junction and electrodes are formed on a rear surface opposite to a light incident surface (front surface) of a (silicon) semiconductor silicon substrate. The photovoltaic element has an intrinsic semiconductor film having a thickness ranging from 0.1 nm to 50 nm. The intrinsic semiconductor film is disposed on the rear surface of the semiconductor substrate. P-type conductive semiconductor portions and n-type conductive semiconductor portions are disposed on the intrinsic semiconductor film, respectively. A first electrode and a second electrode are connected to the p-type portions and the n-type portions, respectively. The first electrode and the second electrode should preferably have comb-like shapes, respectively, and these comb-like shapes should preferably be alternately disposed. Specifically, the first electrode has a first set of teeth and said second electrode has a second set of teeth. The teeth of the first set of teeth are alternately disposed between the teeth of the second set of teeth. The semiconductor substrate may comprise a onocrystalline or polycrystalline semiconductor substrate. The intrinsic semiconductor film may comprise an amorphous silicon film, a film having a hetero-structure in which amorphous silicon and microcrystalline silicon are mixed with each other, an amorphous silicon carbide film, or a film having a hetero-structure in which amorphous silicon carbide and microcrystalline silicon are mixed with each other. It is desirable that the intrinsic semiconductor film is formed by plasma CVD or, particularly, catalytic CVD.
An antireflection film may be disposed on the light incident surface of the semiconductor substrate . A layer having a conductivity type opposite to the semiconductor substrate may be disposed on the light incident surface of the semiconductor substrate. Another intrinsic semiconductor film may be disposed between the light incident surface of the semiconductor substrate and the antireflection film. According to a second aspect of the present invention, there is provided a method of manufacturing a photovoltaic element. A crystalline semiconductor substrate having a conductivity type is prepared, and an intrinsic semiconductor film is adhered to a surface of the crystalline semiconductor substrate. A p-type portions and an n-type portion are formed on the intrinsic semiconductor film by doping with impurities so that the p-type portion is separated from the n-type portion.
According to the present invention, an intrinsic semiconductor film is formed by plasma CVD or catalytic CVD. P-type and n-type portions and electrodes are formed on the intrinsic semiconductor film by a low-temperature process. The photovoltaic element can maintain a silicon substrate with high quality to such an extent that carriers have long lifetime . Thus , a rear-junction type photovoltaic element according to the present invention has a good efficiency of photovoltaic conversion, e.g., a high efficiency of generating electric power . Particularly, with the catalytic CVD, the substrate can be maintained with high quality, and productivity of forming films can relatively be enhanced. The above and other objects, features, and advantages of the present invention will be apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
Brief Description of Drawings
FIG. 1 is a schematic view showing a photovoltaic element according to a first embodiment of the present invention; FIG. 2A is a schematic view showing a catalytic CVD apparatus according to an embodiment of the present invention;
FIG. 2B is a schematic view showing a plasma CVD apparatus according to an embodiment of the present invention; FIG. 3 is a bottom view of the photovoltaic element shown in FIG. 1;
FIG. 4 is a schematic view showing a photovoltaic element according to a second embodiment of the present invention;
FIG. 5 is a schematic view showing a photovoltaic element according to a third embodiment of the present invention; and
FIGS. 6A through 6F illustrate a process of manufacturing a photovoltaic element shown in FIG. 4.
Best Mode for Carrying Out the Invention A photovoltaic element according to embodiments of the present invention will be described below with reference to the accompanying drawings .
FIG. 1 shows a photovoltaic element according to a first embodiment of the present invention . In the present embodiment , the photovoltaic element may be used as a solar cell . For example, the photovoltaic element comprises a rear-junction type solar cell in which a p-n junction and electrodes are disposed on an n-type crystalline semiconductor substrate 11. The crystalline semiconductor substrate 11 may comprise a monocrystalline or polycrystalline semiconductor substrate. For example, the crystalline semiconductor substrate 11 may comprise a monocrystalline silicon substrate formed of a dendritic web having a thickness of 100 μm and doped into an n-type semiconductor with impurities. The crystalline semiconductor substrate 11 may comprise a ribbon-like polycrystalline silicon substrate. The photovoltaic element has an intrinsic semiconductor film 12 disposed on a rear surface of the crystalline semiconductor substrate 11. The monocrystalline or polycrystalline silicon substrate 11 can be produced as follows. A silicon material is melted in a crucible maintained at a predetermined temperature. A seed crystal is pulled up along a crystal axis of a predetermined orientation from the crucible to grow a thin ribbon-like (sheet-like) crystal. The thin crystal is clamped on an endless belt and continuously pulled up to form a long crystal. The produced long crystal is cut off into proper dimensions to produce a rectangular sheet-like monocrystalline or polycrystalline silicon substrate having a thickness of 150 μm or less. Such a method of producing monocrystalline or polycrystalline silicon substrate is disclosed in Japanese patent publication No. 2002-087899 assigned to the assignee of this patent application, the disclosure of which is hereby incorporated by reference.
The intrinsic semiconductor film 12 is formed as an extremely thin amorphous layer having a thickness ranging from 0.1 nm to 50 nm. The intrinsic semiconductor film may comprise an amorphous silicon film, a film having a hetero-structure in which amorphous silicon and microcrystalline silicon are mixed with each other, an amorphous silicon carbide film, or a film having a hetero-structure in which amorphous silicon carbide and microcrystalline silicon are mixed with each other. The intrinsic semiconductor film is an electrically neutral film. With the intrinsic semiconductor film being interposed between p-type and n-type layers, hydrogen passivation can effectively be performed, and electrical characteristics can be improved. For example, an open-circuit voltage can be increased.
The intrinsic semiconductor film 12 should preferably be formed by catalytic CVD or plasma CVD. FIG. 2A shows a catalytic CVD apparatus. As shown in FIG. 2A, the catalytic CVD apparatus has a gas supply device 21 for supplying gases, a high- temperature catalyst 22, and a substrate holder 24 for holding a substrate 23 to be processed. These components are housed in a vacuum chamber capable of being depressurized. The high- temperature catalyst 22 is used to form a CVD film on a surface of the substrate 23 by heating and activating the gases supplied from the gas supply device 21. For example, a wire made of tungsten, molybdenum, or the like which is heated to a temperature ranging from 1500 to 2400 °C may be used as a high-temperature catalyst 22.
FIG. 2B shows a plasma CVD apparatus. As shown in FIG. 2B, the plasma CVD apparatus has electrodes 25 and 26 and a high frequency power supply 27 for applying a high frequency voltage between the electrodes 25 and 26. When a high frequency voltage is applied between the electrodes 25 and 26, gas molecules 28 to be deposited are formed into a plasma and vibrated in directions shown by arrows in FIG. 2B. In this manner, a CVD film is deposited on a surface of a substrate 23 to be processed.
The catalytic CVD apparatus shown in FIG. 2A causes almost no damage to a substrate by a plasma, has a simpler and less expensive structure, and can easily be made larger in size as compared to the plasma CVD apparatus shown in FIG. 2B. Particularly, the catalytic CVD apparatus can achieve a relatively high deposition rate of 5 to 10 nm/sec, for example, and produce a high-quality film of an amorphous silicon film or a microcrystalline silicon film in a relatively short time. The photovoltaic element has p-type portions 13 and n-type portions 14, each formed by doping with impurities. These p-type portions 13 and n-type portions 14 are alternately disposed on a surface of the intrinsic semiconductor film 12. The p-type portions 13 and n-type portions 14 comprise amorphous conductive silicon layers formed, for example, by catalytic CVD or plasma CVD, for example, with a metallic mask. Electrodes 15 and 16 are disposed on the p-type portions 13 and n-type portions 14, respectively. For example, conductive paste of silver or the like is screen-printed into a pattern on the p-type portions 13 and n-type portions 14 and is then hardened by heating to form electrodes 15 and 16. An insulating film 17 made of polyimide resin or the like is disposed between the p-type portions 13 and n-type portions 14. An antireflection film 18 made of SiN may be formed on the light incident surface of the silicon substrate 11.
FIG. 3 schematically shows a rear surface of the photovoltaic element of FIG.1. As shown in FIG .3, the electrode 15 connected to the p-type portions 13 has a comb-like shape, and the electrode 16 connected to the n-type portions 14 has a comb-like shape. The comb-like shape of the electrode 15 and the comb-like shape of the electrode 16 are alternately disposed adjacent to and in parallel with each other. The electrode 15 has a number of teeth connected to a bus bar 15a, and the electrode
16 has a number of teeth connected to a bus bar 16a. In this photovoltaic element, electric power is generated between the bus bars 15a and 16a.
Structural features of the photovoltaic element will be described below. The photovoltaic element has a thin intrinsic amorphous silicon layer (semiconductor film) 12 formed on the rear surface of the substrate 11 by catalytic CVD or plasma CVD.
The solar cell has p-type portions 13 and n-type portions 14 formed on a surface of the intrinsic semiconductor film 12. The p-type portions 13 and n-type portions 14 are also formed by catalytic CVD or plasma CVD and doped with p-type and n-type impurities, respectively. Thus, the intrinsic semiconductor film 12, the p-type portions 13 and n-type portions 14 may be formed by a low-temperature process such as catalytic CVD or plasma CVD. Further, with respect to forming an insulating film
17 and electrodes 15 and 16, each pattern is formed by screen-printing or the like and hardened by heating at a relatively low temperature of 400°C or less. Thus, the photovoltaic element is manufactured in low-temperature processes at temperatures of 400°C or less. Therefore, the silicon substrate 11 can be maintained with high quality to such an extent that carriers have long lifetime. Since the photovoltaic element has no transparent electrodes on the front surface, it has a good efficiency of photovoltaic conversion, e.g. , a high efficiency of generating electric power, and does not have shielding loss.
It is desirable to form the intrinsic semiconductor film 12, the p-type portions 13 and n-type portions 14 by catalytic CVD. In the catalytic CVD, the temperature of the substrate becomes in a range of from about 100°C to about 400°C, and thus the catalytic CVD is a low-temperature process. Therefore, the silicon substrate 11 is not damaged by catalytic CVD. Further, defects within the crystal can be corrected by a high- concentration hydrogen radical to reduce defective interface state levels. The catalytic CVD causes no damage to a substrate by a plasma, unlikely plasma CVD. Thus, the silicon substrate
11 can effectively be maintained with high quality to such an extent that carriers have long lifetime.
FIG. 4 shows a photovoltaic element according to a second embodiment of the present invention. The photovoltaic element in the second embodiment has the same structure as the photovoltaic element shown in FIG. 1 except that an intrinsic semiconductor film 20 is interposed between the light incident surface of the semiconductor substrate 11 and the antireflection film 18. The intrinsic semiconductor film 20 should preferably be formed simultaneously with the intrinsic semiconductor film
12 on the rear surface of the semiconductor substrate 11. The side surfaces of the semiconductor substrate 11 should preferably be covered with an intrinsic semiconductor film. By covering the light incident surface and the side surfaces of the crystalline silicon substrate 11 with intrinsic semiconductor films, interface state levels can be reduced, and electrical characteristics can be improved.
FIG. 5 shows a photovoltaic element according to a third embodiment of the present invention. The photovoltaic element in the third embodiment has the same structure as the photovoltaic element shown in FIG.4 except that a layer 19 having a conductivity type opposite to the substrate 11 is interposed between the light incident surface of the substrate 11 and the intrinsic semiconductor film 20. For example, when the silicon substrate 11 is n-type, the layer 19 is p-type. Since the layer 19 has a conductivity type opposite to the substrate 11, an internal electric field in the substrate 11 can prevent carriers from being recombined with each other. Therefore, it is possible to improve electrical characteristics such as an efficiency of photovoltaic conversion.
Next, a method of manufacturing a photovoltaic element in the second embodiment will be described below with reference to FIGS. 6A through 6F.
As shown in FIG. 6A, an n-type monocrystalline or polycrystalline silicon substrate 11 is prepared. The silicon substrate 11 may be formed of dendritic web crystal or ribbon-like polycrystal . The surfaces of the silicon substrate 11 are cleaned to remove oxide films or the like. Thus, the surfaces of the silicon substrate 11 are cleansed. Next, as shown in FIG. 6B, catalytic CVD is performed to form intrinsic amorphous silicon films 12 and 20 on front and rear faces, respectively, of the silicon substrate 11. The intrinsic amorphous silicon films 12 and 20 should preferably have thicknesses ranging from 0.1 nm to 50 nm, for example, about 10 nm. For example, the intrinsic amorphous silicon films are formed under the following conditions.
Gas flow rate: SiH4 = 20 seem Gas ratio: SiH./H, = 1 : 10 Deposition pressure: 1 Pa Temperature of substrate: 250 °C Temperature of filament: 1800°C In an exemplary embodiment, as shown in FIG. 6C, catalytic CVD is performed to form amorphous conductive silicon portions 33 on the intrinsic amorphous silicon film 12. The conductive silicon portions 33 have thicknesses of about 30 nm. The conductive silicon portions 33 are then doped to form p-type portions 13. For example, the p-type portions 13 are formed under the following conditions.
Gas flow rate: SiH4 = 20 seem, B2H6 = 1 seem (1%, diluted with H2)
Gas ratio: SiH4/H2= 1 : 10 Deposition pressure: 1 Pa Temperature of substrate: 250°C
Temperature of filament: 1800°C
Next, as shown in FIG. 6D, amorphous conductive silicon portions 34 are formed on the intrinsic amorphous silicon film
12. A metallic mask is used for forming a number of parallel comb-like patterns of the amorphous conductive silicon portions
44 disposed between the p-type portions 13. The conductive silicon portions 34 have thicknesses of about 30 nm. The conductive silicon portions 34 are then doped to form n-type portions 14. For example, the n-type portions 14 are formed under the following conditions.
Gas flow rate: SiH4 = 20 seem, PH3 = 1 seem (1%, diluted with H2)
Gas ratio: SiH4/H2= 1 : 10 Deposition pressure: 1 Pa Temperature of substrate: 250°C
Temperature of filament: 1800°C Next, as shown in FIG. 6E , insulating portions (protective portions) 17 are formed on the intrinsic amorphous silicon film 12. For example, paste of polyimide resin is embedded into between the conductive silicon portions 13 and 14 by screen-printing and hardened by heating at a temperature of 250 °C or less. The insulating portions (protective portions) 17 can improve resistance to weather and to soft soldering. As shown in FIG. 6F, silver paste is applied on the conductive silicon portions 13 and 14 by screen-printing and hardened by heating at a relatively low temperature of 250°C or less to form comb-like electrodes 15 and 15a, 16 and 16a (see FIG. 3) disposed alternately on the conductive silicon portions 13 and 14, respectively.
An antireflection film should preferably be formed on the intrinsic semiconductor film 20. The antireflection film may be formed as an Si3N4 film by high frequency sputtering, For example. The antireflection film may have a thickness of about 60 nm.
As shown in FIG. 5, a diffusion layer 19 having a conductivity type opposite to that of the substrate 11 may be formed between the light incident surface of the substrate 11 and the intrinsic semiconductor film 20. The diffusion layer 19 may be formed on the silicon substrate 11 by thermomigration, ion implantation, or the like.
Although certain preferred embodiments of the present invention have been shown and described in detail, it should be understood that various changes and modifications may be made therein without departing from the scope of the appended claims .
Industrial Applicability
The present invention is suitable for use in a photovoltaic element such as a solar cell having a p-n junction and positive and negative electrodes disposed on a rear surface opposite to a light incident surface.

Claims

1. A photovoltaic element comprising: a semiconductor substrate having a light incident surface and a rear surface opposite to said light incident surface; an intrinsic semiconductor film having a thickness ranging from 0.1 nm to 50 nm, said intrinsic semiconductor film being disposed on said rear surface; a p-type conductive semiconductor portion disposed on said intrinsic semiconductor film; a first electrode connected to said p-type conductive semiconductor portion; an n-type conductive semiconductor portion disposed on said intrinsic semiconductor film; and a second electrode connected to said n-type conductive semiconductor portion.
2. A photovoltaic element according to claim 1, wherein each of said first electrode and said second electrode has a comb-like shape.
3. A photovoltaic element according to claim 2 , wherein said first electrode comprises a first set of teeth and said second electrode comprises a second set of teeth, and wherein the teeth of said first set of teeth are alternately disposed between the teeth of said second set of teeth.
4. A photovoltaic element according to claim 1, wherein said semiconductor substrate comprises a monocrystalline or polycrystalline semiconductor substrate.
5. A photovoltaic element according to claim 1, wherein said intrinsic semiconductor film comprises at least one of an amorphous silicon film, a film having a hetero-structure mixture of amorphous silicon and microcrystalline silicon, an amorphous silicon carbide film, and a film having a hetero-structure mixture of amorphous silicon carbide and microcrystalline silicon.
6. A photovoltaic element according to claim 1, wherein said intrinsic semiconductor film is formed by catalytic CVD.
7. A photovoltaic element according to claim 1, further comprising an antireflection film disposed on said light incident surface.
8. A photovoltaic element according to claim 1, further comprising a layer having a conductivity type opposite to a conductivity of said semiconductor substrate and being disposed on said light incident surface.
9. A photovoltaic element according to claim 1, further comprising a second intrinsic semiconductor film disposed on said light incident surface.
10. A method of manufacturing a photovoltaic element , said method comprising: preparing a crystalline semiconductor substrate having a conductivity type; adhering an intrinsic semiconductor film to a surface of the crystalline semiconductor substrate; and forming a p-type conductive semiconductor portion and an n-type conductive semiconductor portion on the intrinsic semiconductor film so that the p-type conductive semiconductor portion is separated from the n-type conductive semiconductor portion.
11. A method according to claim 10, wherein said adhering comprises forming the intrinsic semiconductor film by catalytic CVD.
12. A method according to claim 10, wherein said forming comprises doping with impurities.
13. A method according to claim 10, wherein said forming comprises : forming a first set of conductive semiconductor portions on the intrinsic semiconductor film; doping the first set of conductive semiconductor portions to form p-type conductive semiconductor portions; forming a second set of conductive semiconductor portions on the intrinsic semiconductor film such that each p-type conductive semiconductor portion is separated from the other p-type conductive semiconductor portions and such that each of the second set of conductive semiconductor portions is separated from one another; and doping the second set of conductive semiconductor portions to form n-type conductive semiconductor portions.
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