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WO2003063218A3 - Method for forming shallow junctions by ion implantation in silicon wafers - Google Patents

Method for forming shallow junctions by ion implantation in silicon wafers Download PDF

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Publication number
WO2003063218A3
WO2003063218A3 PCT/GB2003/000136 GB0300136W WO03063218A3 WO 2003063218 A3 WO2003063218 A3 WO 2003063218A3 GB 0300136 W GB0300136 W GB 0300136W WO 03063218 A3 WO03063218 A3 WO 03063218A3
Authority
WO
WIPO (PCT)
Prior art keywords
ion implantation
substrate
silicon wafers
shallow junctions
forming shallow
Prior art date
Application number
PCT/GB2003/000136
Other languages
French (fr)
Other versions
WO2003063218A2 (en
Inventor
Ahmed Nejim
Brian Sealy
Original Assignee
Univ Surrey
Ahmed Nejim
Brian Sealy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Surrey, Ahmed Nejim, Brian Sealy filed Critical Univ Surrey
Priority to AU2003201676A priority Critical patent/AU2003201676A1/en
Publication of WO2003063218A2 publication Critical patent/WO2003063218A2/en
Publication of WO2003063218A3 publication Critical patent/WO2003063218A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for ion implantation into a silicon semiconducting wafer with a buried barrier layer includes the implantation of dopant ions at a low energy level into the substrate to a depth close to the surface. Other ions are implanted at a high energy level into the substrate to form a network of extended defects at a depth beyond the barrier layer. The implanted substrate is subjected to rapid thermal annealing to activate the dopants to form a shallow conducting layer close to the wafer surface.
PCT/GB2003/000136 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers WO2003063218A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003201676A AU2003201676A1 (en) 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0200879.5A GB0200879D0 (en) 2002-01-16 2002-01-16 Ion implanted junctions in silicon wafers
GB0200879.5 2002-01-16

Publications (2)

Publication Number Publication Date
WO2003063218A2 WO2003063218A2 (en) 2003-07-31
WO2003063218A3 true WO2003063218A3 (en) 2003-11-06

Family

ID=9929131

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2003/000136 WO2003063218A2 (en) 2002-01-16 2003-01-15 Method for forming shallow junctions by ion implantation in silicon wafers

Country Status (3)

Country Link
AU (1) AU2003201676A1 (en)
GB (1) GB0200879D0 (en)
WO (1) WO2003063218A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
US7172954B2 (en) 2005-05-05 2007-02-06 Infineon Technologies Ag Implantation process in semiconductor fabrication
WO2006125993A1 (en) * 2005-05-27 2006-11-30 University Of Surrey Semiconductor device and method of manufacture
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces
US8813580B2 (en) * 2012-03-05 2014-08-26 Honeywell International Inc. Apparatus and processes for silicon on insulator MEMS pressure sensors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129536A (en) * 1991-11-01 1993-05-25 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
EP0806794A2 (en) * 1996-04-29 1997-11-12 Texas Instruments Incorporated Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation
US5837597A (en) * 1994-12-21 1998-11-17 Nec Corporation Method of manufacturing semiconductor device with shallow impurity layers
US6037640A (en) * 1997-11-12 2000-03-14 International Business Machines Corporation Ultra-shallow semiconductor junction formation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129536A (en) * 1991-11-01 1993-05-25 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5837597A (en) * 1994-12-21 1998-11-17 Nec Corporation Method of manufacturing semiconductor device with shallow impurity layers
EP0806794A2 (en) * 1996-04-29 1997-11-12 Texas Instruments Incorporated Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation
US6037640A (en) * 1997-11-12 2000-03-14 International Business Machines Corporation Ultra-shallow semiconductor junction formation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 017, no. 504 (E - 1430) 10 September 1993 (1993-09-10) *
RAINERI V ET AL: "REDUCTION OF BORON DIFFUSION IN SILICON BY 1 MEV 29SI+ IRRADIATION", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 58, no. 9, 4 March 1991 (1991-03-04), pages 922 - 924, XP000208528, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
WO2003063218A2 (en) 2003-07-31
GB0200879D0 (en) 2002-03-06
AU2003201676A1 (en) 2003-09-02

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