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WO2003058684A3 - Transistor mosfet de puissance haute tension comprenant une zone de maintien de la tension pourvue de colonnes dopees formees par gravure des tranchees et diffusion de zones de polysilicone dopees de maniere opposee - Google Patents

Transistor mosfet de puissance haute tension comprenant une zone de maintien de la tension pourvue de colonnes dopees formees par gravure des tranchees et diffusion de zones de polysilicone dopees de maniere opposee Download PDF

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Publication number
WO2003058684A3
WO2003058684A3 PCT/US2002/041809 US0241809W WO03058684A3 WO 2003058684 A3 WO2003058684 A3 WO 2003058684A3 US 0241809 W US0241809 W US 0241809W WO 03058684 A3 WO03058684 A3 WO 03058684A3
Authority
WO
WIPO (PCT)
Prior art keywords
polysilicon
region
sustaining region
trench
diffusion
Prior art date
Application number
PCT/US2002/041809
Other languages
English (en)
Other versions
WO2003058684A2 (fr
Inventor
Richard A Blanchard
Original Assignee
Gen Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Semiconductor Inc filed Critical Gen Semiconductor Inc
Priority to EP02794456.0A priority Critical patent/EP1476894B1/fr
Priority to JP2003558903A priority patent/JP4880199B2/ja
Priority to KR1020047010415A priority patent/KR100952538B1/ko
Priority to AU2002359889A priority patent/AU2002359889A1/en
Publication of WO2003058684A2 publication Critical patent/WO2003058684A2/fr
Publication of WO2003058684A3 publication Critical patent/WO2003058684A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de formation d'un dispositif à semi-conducteurs de puissance. Le procédé consiste d'abord à produire un substrat d'un premier ou d'un second type de conductivité, puis à former une zone de maintien de la tension sur le substrat. La zone de maintien de la tension est formée par dépôt d'une couche épitaxiale d'un premier type de conductivité sur le substrat puis par formation d'au moins une tranchée dans la couche épitaxiale. Une première couche de polysilicone contenant un second dopant du second type de conductivité est déposée dans la tranchée. Le second dopant est diffusé pour former une zone épitaxiale dopée adjacente à la tranchée et dans la couche épitaxiale. Une seconde couche de polysilicone contenant un premier dopant du premier type de conductivité est ensuite déposée dans la tranchée. Le premier et le second dopant, respectivement situés dans la seconde et la première couche de polysilicone, sont interdiffusés afin d'obtenir une compensation électrique dans la première et la seconde couche de polysilicone. Enfin, au moins une zone du second type de conductivité est formée sur la zone de maintien de la tension de manière à définir une jonction entre les deux.
PCT/US2002/041809 2001-12-31 2002-12-30 Transistor mosfet de puissance haute tension comprenant une zone de maintien de la tension pourvue de colonnes dopees formees par gravure des tranchees et diffusion de zones de polysilicone dopees de maniere opposee WO2003058684A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02794456.0A EP1476894B1 (fr) 2001-12-31 2002-12-30 Procédé de réalisation d'un transistor mosfet de puissance haute tension comprenant une zone de maintien de la tension pourvue de colonnes dopées formées par gravure des tranchees et diffusion de zones de polysilicone dopées de manière opposée
JP2003558903A JP4880199B2 (ja) 2001-12-31 2002-12-30 トレンチのエッチングおよび反対にドープされたポリシリコンの領域からの拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力ｍｏｓｆｅｔ
KR1020047010415A KR100952538B1 (ko) 2001-12-31 2002-12-30 반대로 도핑된 폴리실리콘의 영역들로부터 트렌치 에칭 및확산에 의해 형성되는 도핑된 칼럼들을 포함하는 전압유지 영역을 갖는 고전압 전력 ｍｏｓｆｅｔ
AU2002359889A AU2002359889A1 (en) 2001-12-31 2002-12-30 High voltage power mosfet having a voltage sustaining region and diffusion from regions of oppositely doped polysilicon

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/039,241 2001-12-31
US10/039,241 US6576516B1 (en) 2001-12-31 2001-12-31 High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon

Publications (2)

Publication Number Publication Date
WO2003058684A2 WO2003058684A2 (fr) 2003-07-17
WO2003058684A3 true WO2003058684A3 (fr) 2003-10-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/041809 WO2003058684A2 (fr) 2001-12-31 2002-12-30 Transistor mosfet de puissance haute tension comprenant une zone de maintien de la tension pourvue de colonnes dopees formees par gravure des tranchees et diffusion de zones de polysilicone dopees de maniere opposee

Country Status (8)

Country Link
US (3) US6576516B1 (fr)
EP (1) EP1476894B1 (fr)
JP (1) JP4880199B2 (fr)
KR (1) KR100952538B1 (fr)
CN (1) CN100355086C (fr)
AU (1) AU2002359889A1 (fr)
TW (1) TWI270208B (fr)
WO (1) WO2003058684A2 (fr)

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KR100952538B1 (ko) 2010-04-12
US20050042830A1 (en) 2005-02-24
KR20040069213A (ko) 2004-08-04
AU2002359889A8 (en) 2003-07-24
EP1476894A2 (fr) 2004-11-17
JP4880199B2 (ja) 2012-02-22
US6794251B2 (en) 2004-09-21
TWI270208B (en) 2007-01-01
EP1476894A4 (fr) 2009-02-18
US6576516B1 (en) 2003-06-10
CN1610974A (zh) 2005-04-27
US20030203552A1 (en) 2003-10-30
US7224027B2 (en) 2007-05-29
TW200302575A (en) 2003-08-01
JP2005514787A (ja) 2005-05-19
EP1476894B1 (fr) 2016-06-22
AU2002359889A1 (en) 2003-07-24
WO2003058684A2 (fr) 2003-07-17
CN100355086C (zh) 2007-12-12

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