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WO2003046979A3 - Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect - Google Patents

Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect Download PDF

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Publication number
WO2003046979A3
WO2003046979A3 PCT/US2002/032605 US0232605W WO03046979A3 WO 2003046979 A3 WO2003046979 A3 WO 2003046979A3 US 0232605 W US0232605 W US 0232605W WO 03046979 A3 WO03046979 A3 WO 03046979A3
Authority
WO
WIPO (PCT)
Prior art keywords
copper alloy
ternary copper
grain size
low resistance
large grain
Prior art date
Application number
PCT/US2002/032605
Other languages
French (fr)
Other versions
WO2003046979A2 (en
Inventor
Sergey Lopatin
Paul R Besser
Pin-Chin Connie Wang
Original Assignee
Advanced Micro Devices Inc
Sergey Lopatin
Paul R Besser
Pin-Chin Connie Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Sergey Lopatin, Paul R Besser, Pin-Chin Connie Wang filed Critical Advanced Micro Devices Inc
Priority to JP2003548301A priority Critical patent/JP4463555B2/en
Priority to AU2002335805A priority patent/AU2002335805A1/en
Priority to EP02770570A priority patent/EP1449247A2/en
Priority to KR1020047007985A priority patent/KR100966359B1/en
Publication of WO2003046979A2 publication Critical patent/WO2003046979A2/en
Publication of WO2003046979A3 publication Critical patent/WO2003046979A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
PCT/US2002/032605 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect WO2003046979A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003548301A JP4463555B2 (en) 2001-11-26 2002-10-11 Using ternary copper alloy to obtain low resistance, large grain size wiring
AU2002335805A AU2002335805A1 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
EP02770570A EP1449247A2 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
KR1020047007985A KR100966359B1 (en) 2001-11-26 2002-10-11 How to use tri-copper alloy to get low resistance and large grain size wiring

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,395 2001-11-26
US09/994,395 US7696092B2 (en) 2001-11-26 2001-11-26 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Publications (2)

Publication Number Publication Date
WO2003046979A2 WO2003046979A2 (en) 2003-06-05
WO2003046979A3 true WO2003046979A3 (en) 2003-10-30

Family

ID=25540628

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/032605 WO2003046979A2 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Country Status (7)

Country Link
US (1) US7696092B2 (en)
EP (1) EP1449247A2 (en)
JP (1) JP4463555B2 (en)
KR (1) KR100966359B1 (en)
CN (1) CN1320630C (en)
AU (1) AU2002335805A1 (en)
WO (1) WO2003046979A2 (en)

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US7696092B2 (en) 2001-11-26 2010-04-13 Globalfoundries Inc. Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
US7989338B2 (en) * 2005-06-15 2011-08-02 Globalfoundries Singapore Pte. Ltd. Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
JP5234306B2 (en) * 2006-10-18 2013-07-10 三菱マテリアル株式会社 Wiring and electrode for flat panel display using TFT transistor with less surface defects and good surface condition, and sputtering target for forming them
US8575019B2 (en) * 2010-09-30 2013-11-05 Institute of Microelectronics, Chinese Academy of Sciences Metal interconnection structure and method for forming metal interlayer via and metal interconnection line
CN104137191A (en) * 2011-12-28 2014-11-05 矢崎总业株式会社 Ultrafine conductor material, ultrafine conductor, method for preparing ultrafine conductor, and ultrafine electrical wire
JP5987443B2 (en) * 2012-04-19 2016-09-07 富士通株式会社 Operation motion detection device, operation motion detection method, and program
KR102211741B1 (en) * 2014-07-21 2021-02-03 삼성전기주식회사 Printed circuit board and method of manufacturing the same
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
KR20220030455A (en) * 2020-09-01 2022-03-11 삼성전자주식회사 Semiconductor device

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US6090710A (en) * 1995-06-27 2000-07-18 International Business Machines Corporation Method of making copper alloys for chip and package interconnections
US6242808B1 (en) * 1998-04-09 2001-06-05 Fujitsu Limited Semiconductor device with copper wiring and semiconductor device manufacturing method
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Also Published As

Publication number Publication date
AU2002335805A8 (en) 2003-06-10
JP2005510875A (en) 2005-04-21
WO2003046979A2 (en) 2003-06-05
CN1592963A (en) 2005-03-09
KR20040064287A (en) 2004-07-16
CN1320630C (en) 2007-06-06
US20040005773A1 (en) 2004-01-08
KR100966359B1 (en) 2010-06-28
EP1449247A2 (en) 2004-08-25
AU2002335805A1 (en) 2003-06-10
JP4463555B2 (en) 2010-05-19
US7696092B2 (en) 2010-04-13

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