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WO2003046965A1 - Substrats specialises destines a etre utilises dans des processus de solidification laterale sequentielle - Google Patents

Substrats specialises destines a etre utilises dans des processus de solidification laterale sequentielle Download PDF

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Publication number
WO2003046965A1
WO2003046965A1 PCT/US2001/044563 US0144563W WO03046965A1 WO 2003046965 A1 WO2003046965 A1 WO 2003046965A1 US 0144563 W US0144563 W US 0144563W WO 03046965 A1 WO03046965 A1 WO 03046965A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductivity
substrate
silicon compound
melting
Prior art date
Application number
PCT/US2001/044563
Other languages
English (en)
Inventor
James S. Im
Original Assignee
The Trustees Of Columbia University In The City Of New York
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Trustees Of Columbia University In The City Of New York filed Critical The Trustees Of Columbia University In The City Of New York
Priority to PCT/US2001/044563 priority Critical patent/WO2003046965A1/fr
Priority to AU2002219913A priority patent/AU2002219913A1/en
Publication of WO2003046965A1 publication Critical patent/WO2003046965A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to techniques for processing of semiconductor films, and more particularly to techniques for processing semiconductor films on glass or other substrates.
  • the effectiveness with which sequential lateral solidification can be implemented depends on several factors, the most important of which corresponds to the length of lateral crystal growth achieved per laser pulse.
  • Such lateral crystal growth depends on several parameters, including the duration of the laser pulses, film thickness, substrate temperature at the point of laser pulse irradiation, the energy density of the laser pulse incident on the substrate, and the effective thermal conductivity of the substrate. In particular, if all other factors are kept constant, reducing the thermal conductivity of the substrate will have the effect of increasing lateral crystal growth.
  • An obj ect of the present invention is to provide substrates having modified effective thermal conductivity which can be later used in an optimized sequential lateral solidification process.
  • a further object of the present invention is to provide substrates having modified effective thermal conductivity.
  • Still a further object of the present invention is to provide substrates having a directionally optimized effective thermal conductivity.
  • Yet a further object of the present invention is to provide multi layer substrates where one or more of the subsurface layers act as a heat reservoir in order to optimize the effective thermal characteristics of the substrate.
  • the present invention provides a substrate having modified effective thermal conductivity for use in the sequential lateral solidification process.
  • the substrate includes a base layer, e.g., glass, a low conductivity layer formed adjacent to a surface of the base layer, a high conductivity layer formed adjacent to the low conductivity layer, and a silicon layer formed on the high conductivity layer.
  • the low conductivity layer is porous glass, and is in the range of 5,000 Angstroms to 2 microns thick.
  • the high conductivity layer may be a metal, and should be sufficiently thin so as to not increase the overall vertical conductivity of the substrate, preferably in the range of 50 to 5,000 Angstroms thick.
  • An intermediate silicon compound layer is preferably formed between the silicon layer and the high conductivity layer.
  • the silicon compound may be silicon dioxide, and should be sufficiently thick to prevent diffusion of impurities from the high conductivity layer. It is preferred that the silicon compound layer is in the range of 200 to 2,000 Angstroms thick.
  • the present invention provides a substrate having modified effective thermal conductivity for use in the sequential lateral solidification process, wherein the high conductivity layer is replaced by an internal subsurface melting layer.
  • the substrate includes a base layer, a low conductivity layer formed adjacent to the base layer, a subsurface melting layer having a melting point which is less than that of silicon and formed adjacent to the low conductivity layer, a silicon compound layer formed adjacent to the subsurface melting layer, and silicon layer formed on the silicon compound layer.
  • FIG. 1 is a schematic diagram of a substrate in accordance with a preferred embodiment of the present invention.
  • Fig. 2 is an illustrative diagram showing lateral solidification of silicon
  • Figs. 3 a and b are graphs showing the relationship between the temperature of solidifying silicon and the position of such silicon around a liquid to solid interface
  • Fig. 4 is a schematic diagram of a substrate in accordance with a second preferred embodiment of the present invention. DESCRIPTION OF PREFERRED EMBODIMENTS Referring to Fig. 1, a preferred embodiment of the present invention will be described.
  • the substrate 100 includes a bulk glass plate layer 110, a low conductivity layer 120, a high conductivity layer 130, a silicon dioxide layer 130 and a semiconducting film layer 150.
  • the multilayer structure of substrate 100 may be fabricated by any combination of thin film formation techniques, such as physical or chemical vapor deposition, electrochemical deposition, or spin coating.
  • the low conductivity layer 120 may be porous glass or a polymer film layer.
  • the layer 120 must have a conductivity which is less than the glass plate 110 and sufficiently thick so that the glass plate layer 110 will not participate when the substrate 100 is used in later processing.
  • Layer 120 will be in the order of 5,000
  • the high conductivity layer 130 may be a metallic layer such as copper or aluminum.
  • the high conductivity layer must have a conductivity which is greater than that of the glass plate 110, and sufficiently thin so as to not increase the overall vertical conductivity of the substrate 100, i.e., conductivity in the direction which crosses layers 110, 120, 130, 140, 150.
  • layer 130 will be in the order of 50 to 5,000 Angstroms thick.
  • the silicon dioxide layer 140 should be sufficiently thick to prevent potential diffusion of unwanted impurities from the underlying layer 130 to the silicon cap 150.
  • the Layer 140 will be in the order of 200 to 2,000 Angstroms thick.
  • the layer 140 maybe fabricated from siliconnitri.de or a mixture of silicon dioxide and silicon nitride.
  • the high conductivity layer 130 may be formed from a material which is electrically and chemically compatible with the semiconducting film layer 150, such as diamond.
  • the silicon dioxide layer 140 may be omitted, with the semiconducting film layer 150 formed directly on the high conductivity layer
  • the top semiconducting film layer may be either be amorphous, microcrystallme or polycrystalline silicon, or a mixture thereof.
  • layer 150 will be in the order of 200 to 2,000 Angstroms thick.
  • the substrate 100 When fabricated as described above, the substrate 100 will exhibit either a reduced overall effective thermal conductivity, or a reduced effective thermal conductivity in the vertical direction. Having such a modified thermal conductivity, the substrate 100 is highly useful in order to improve lateral crystal growth in the lateral solidification process, as will be now described.
  • Fig. 2 represents a cross sectional view of the silicon film 150 as it may appear during lateral solidification, with liquid silicon 210 solidifying into crystalline silicon 220 at a velocity Vg.
  • Vg a velocity
  • the liquid silicon solidifies through the motion of the interface 230
  • latent heat is released at the interface 230 due to reduction in enthalpy associated with the liquid to solid transition.
  • the lateral solidification will continue along moving boundary 230 until either impingement of the interface with another similar interface, or until nucleation.
  • T bul represents the temperature of the bulk liquid silicon as it cools
  • T int represents the temperature of the silicon as the interface 230
  • T mp represents the melting temperature of silicon.
  • the temperature profile 310 represents a poor temperature profile, as the high interface temperature will cause slow lateral solidification, and the low temperature in the region away from the interface 230 will cause the temperature of those regions of liquid silicon to drop below the nucleation temperature range, ⁇ T N .
  • the temperature profile 320 represents a optimal temperature profile, with a lower interface temperature causing more rapid lateral solidification, and a less cooling in the liquid silicon away from the interface 230 such that the temperature remains above the nucleation temperature range for a loner time.
  • the substrate 400 includes a bulk glass plate layer 410, a low conductivity layer 420, a subsurface melting layer 430, a silicon dioxide layer 430 and a semiconductor layer 450 made from a predetermined semiconductor material.
  • the low conductivity layer 420, a silicon dioxide layer 430 and semiconductor layer 450 may be fabricated as described above in connection with substrate 100 by any combination of thin film formation techniques, such as physical or chemical vapor deposition, electrochemical deposition, or spin coating.
  • the subsurface melting layer 430 must have a melting point which is less than or equal to that of the predetermined semiconductor material, and preferably should exhibit an increased conductivity after melting.
  • a material having a high latent heat for the melting layer 430 such as a Silicon Germanium alloy.
  • a 1000 Angstrom thick layer of Silicon Germanium alloy would be suitable for melting layer 430.
  • an approximately 1000 Angstrom thick layer of certain metals such as Aluminum or Copper could be used for melting layer 430.
  • the substrate 400 When fabricated as described above, the substrate 400 will exhibit either a reduced overall effective thermal conductivity, or a reduced effective thermal conductivity in the vertical direction.
  • the melting layer 430 When used in the sequential lateral solidification process, the melting layer 430 will partially or completely melt, thereby storing heat. Later, as the melting layer solidifies, heat will be released through the phase transformation from liquid to solid, thereby preventing rapid cooling of the overlying silicon layer 450, and delaying nucleation. Thus, as shown in Fig. 3b, the solidification of the melting layer 430 will have the effect of moving the temperature profile of the solidifying silicon layer up from profile 310 to profile 320 in the regions away from the boundary 230.
  • the substrate 400 is likewise highly useful in order to improve lateral crystal growth in the lateral solidification process.
  • the silicon layer 150, 450 maybe replaced by other semiconductors such Germanium, Silicon Germanium, Gallium Arsenide, or Gallium Nitride, with, in the case of the second embodiment, suitable modifications to the melting layer 430.
  • other metals may be used for the high conductivity layer 130.
  • the high and low conductivity layers may be either a single unitary layer, or consist of multiple sub-layers. It will thus be appreciated that those skilled in the art will be able to devise numerous systems and methods which, although not explicitly shown or described herein, embody the principles of the invention and are thus within the spirit and scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Substrats possédant une conductivité thermique effective modifiée, destinés à être utilisés dans le processus de solidification latérale séquentielle. Dans un mode de réalisation, un substrat comporte une couche de base en verre, une couche à faible conductivité formée adjacente à une surface de la couche de base, une couche à conductivité élevée formée adjacente à la couche à faible conductivité, une couche de composé de silicium formée adjacente à la couche à conductivité élevée et une couche de silicium formée sur la couche de composé de silicium. Dans un autre mode de réalisation, ledit substrat comporte une couche de fusion interne, située sous la surface, destinée à servir de réservoir de chaleur pendant le processus de solidification latérale séquentielle subséquent.
PCT/US2001/044563 2001-11-28 2001-11-28 Substrats specialises destines a etre utilises dans des processus de solidification laterale sequentielle WO2003046965A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2001/044563 WO2003046965A1 (fr) 2001-11-28 2001-11-28 Substrats specialises destines a etre utilises dans des processus de solidification laterale sequentielle
AU2002219913A AU2002219913A1 (en) 2001-11-28 2001-11-28 Specialized substrates for use in sequential lateral solidification processing

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Application Number Priority Date Filing Date Title
PCT/US2001/044563 WO2003046965A1 (fr) 2001-11-28 2001-11-28 Substrats specialises destines a etre utilises dans des processus de solidification laterale sequentielle

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Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961117B2 (en) 2000-11-27 2005-11-01 The Trustees Of Columbia University In The City Of New York Process and mask projection system for laser crystallization processing of semiconductor film regions on a substrate
US7029996B2 (en) 1999-09-03 2006-04-18 The Trustees Of Columbia University In The City Of New York Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidification
US7115503B2 (en) 2000-10-10 2006-10-03 The Trustees Of Columbia University In The City Of New York Method and apparatus for processing thin metal layers
US7160763B2 (en) 2001-08-27 2007-01-09 The Trustees Of Columbia University In The City Of New York Polycrystalline TFT uniformity through microstructure mis-alignment
US7164152B2 (en) 2003-09-16 2007-01-16 The Trustees Of Columbia University In The City Of New York Laser-irradiated thin films having variable thickness
CN1301535C (zh) * 2003-07-25 2007-02-21 友达光电股份有限公司 于基板上形成多晶硅层的方法
US7220660B2 (en) 2000-03-21 2007-05-22 The Trustees Of Columbia University In The City Of New York Surface planarization of thin silicon films during and after processing by the sequential lateral solidification method
US7259081B2 (en) 2002-08-19 2007-08-21 Im James S Process and system for laser crystallization processing of film regions on a substrate to provide substantial uniformity, and a structure of such film regions
US7300858B2 (en) 2002-08-19 2007-11-27 The Trustees Of Columbia University In The City Of New York Laser crystallization and selective patterning using multiple beamlets
US7311778B2 (en) 2003-09-19 2007-12-25 The Trustees Of Columbia University In The City Of New York Single scan irradiation for crystallization of thin films
US7318866B2 (en) 2003-09-16 2008-01-15 The Trustees Of Columbia University In The City Of New York Systems and methods for inducing crystallization of thin films using multiple optical paths
US7341928B2 (en) 2003-02-19 2008-03-11 The Trustees Of Columbia University In The City Of New York System and process for processing a plurality of semiconductor thin films which are crystallized using sequential lateral solidification techniques
US7364952B2 (en) 2003-09-16 2008-04-29 The Trustees Of Columbia University In The City Of New York Systems and methods for processing thin films
US7399359B2 (en) 2002-04-01 2008-07-15 The Trustees of Columbia University in theCity of New York Method and system for providing a thin film with a controlled crystal orientation using pulsed laser induced melting and nucleation-initiated crystallization
US7622370B2 (en) 2002-08-19 2009-11-24 The Trustees Of Columbia University In The City Of New York Process and system for laser crystallization processing of film regions on a substrate to minimize edge areas, and a structure of such film regions
US7638728B2 (en) 2003-09-16 2009-12-29 The Trustees Of Columbia University In The City Of New York Enhancing the width of polycrystalline grains with mask
US8871022B2 (en) 2007-11-21 2014-10-28 The Trustees Of Columbia University In The City Of New York Systems and methods for preparation of epitaxially textured thick films
US8883656B2 (en) 2002-08-19 2014-11-11 The Trustees Of Columbia University In The City Of New York Single-shot semiconductor processing system and method having various irradiation patterns
US8889569B2 (en) 2009-11-24 2014-11-18 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse sequential lateral soldification
US9012309B2 (en) 2007-09-21 2015-04-21 The Trustees Of Columbia University In The City Of New York Collections of laterally crystallized semiconductor islands for use in thin film transistors
US9087696B2 (en) 2009-11-03 2015-07-21 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse partial melt film processing
US9466402B2 (en) 2003-09-16 2016-10-11 The Trustees Of Columbia University In The City Of New York Processes and systems for laser crystallization processing of film regions on a substrate utilizing a line-type beam, and structures of such film regions
US9646831B2 (en) 2009-11-03 2017-05-09 The Trustees Of Columbia University In The City Of New York Advanced excimer laser annealing for thin films

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US6130455A (en) * 1996-03-21 2000-10-10 Sharp Kabushiki Kaisha Semiconductor device, thin film transistor having an active crystal layer formed by a line containing a catalyst element
WO2001039258A1 (fr) * 1999-11-22 2001-05-31 Sony Corporation Dispositif fonctionnel et procede de fabrication de ce dispositif
US20010039103A1 (en) * 2000-04-10 2001-11-08 Shinichi Muramatsu Process for producing crystalline silicon thin film

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JPS62181419A (ja) * 1986-02-05 1987-08-08 Nec Corp 多結晶シリコンの再結晶化法
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JPH0433327A (ja) * 1990-05-30 1992-02-04 Kyocera Corp 半導体結晶化膜の形成方法
US6130455A (en) * 1996-03-21 2000-10-10 Sharp Kabushiki Kaisha Semiconductor device, thin film transistor having an active crystal layer formed by a line containing a catalyst element
WO2001039258A1 (fr) * 1999-11-22 2001-05-31 Sony Corporation Dispositif fonctionnel et procede de fabrication de ce dispositif
US20010039103A1 (en) * 2000-04-10 2001-11-08 Shinichi Muramatsu Process for producing crystalline silicon thin film

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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8859436B2 (en) 1996-05-28 2014-10-14 The Trustees Of Columbia University In The City Of New York Uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors formed using sequential lateral solidification and devices formed thereon
US7319056B2 (en) 1996-05-28 2008-01-15 The Trustees Of Columbia University In The City Of New York Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidification
US7029996B2 (en) 1999-09-03 2006-04-18 The Trustees Of Columbia University In The City Of New York Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidification
US7220660B2 (en) 2000-03-21 2007-05-22 The Trustees Of Columbia University In The City Of New York Surface planarization of thin silicon films during and after processing by the sequential lateral solidification method
US7115503B2 (en) 2000-10-10 2006-10-03 The Trustees Of Columbia University In The City Of New York Method and apparatus for processing thin metal layers
US6961117B2 (en) 2000-11-27 2005-11-01 The Trustees Of Columbia University In The City Of New York Process and mask projection system for laser crystallization processing of semiconductor film regions on a substrate
US7160763B2 (en) 2001-08-27 2007-01-09 The Trustees Of Columbia University In The City Of New York Polycrystalline TFT uniformity through microstructure mis-alignment
US7399359B2 (en) 2002-04-01 2008-07-15 The Trustees of Columbia University in theCity of New York Method and system for providing a thin film with a controlled crystal orientation using pulsed laser induced melting and nucleation-initiated crystallization
US8883656B2 (en) 2002-08-19 2014-11-11 The Trustees Of Columbia University In The City Of New York Single-shot semiconductor processing system and method having various irradiation patterns
US7259081B2 (en) 2002-08-19 2007-08-21 Im James S Process and system for laser crystallization processing of film regions on a substrate to provide substantial uniformity, and a structure of such film regions
US7300858B2 (en) 2002-08-19 2007-11-27 The Trustees Of Columbia University In The City Of New York Laser crystallization and selective patterning using multiple beamlets
US7622370B2 (en) 2002-08-19 2009-11-24 The Trustees Of Columbia University In The City Of New York Process and system for laser crystallization processing of film regions on a substrate to minimize edge areas, and a structure of such film regions
US7341928B2 (en) 2003-02-19 2008-03-11 The Trustees Of Columbia University In The City Of New York System and process for processing a plurality of semiconductor thin films which are crystallized using sequential lateral solidification techniques
CN1301535C (zh) * 2003-07-25 2007-02-21 友达光电股份有限公司 于基板上形成多晶硅层的方法
US7364952B2 (en) 2003-09-16 2008-04-29 The Trustees Of Columbia University In The City Of New York Systems and methods for processing thin films
US7318866B2 (en) 2003-09-16 2008-01-15 The Trustees Of Columbia University In The City Of New York Systems and methods for inducing crystallization of thin films using multiple optical paths
US7638728B2 (en) 2003-09-16 2009-12-29 The Trustees Of Columbia University In The City Of New York Enhancing the width of polycrystalline grains with mask
US7164152B2 (en) 2003-09-16 2007-01-16 The Trustees Of Columbia University In The City Of New York Laser-irradiated thin films having variable thickness
US9466402B2 (en) 2003-09-16 2016-10-11 The Trustees Of Columbia University In The City Of New York Processes and systems for laser crystallization processing of film regions on a substrate utilizing a line-type beam, and structures of such film regions
US7311778B2 (en) 2003-09-19 2007-12-25 The Trustees Of Columbia University In The City Of New York Single scan irradiation for crystallization of thin films
US9012309B2 (en) 2007-09-21 2015-04-21 The Trustees Of Columbia University In The City Of New York Collections of laterally crystallized semiconductor islands for use in thin film transistors
US8871022B2 (en) 2007-11-21 2014-10-28 The Trustees Of Columbia University In The City Of New York Systems and methods for preparation of epitaxially textured thick films
US9087696B2 (en) 2009-11-03 2015-07-21 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse partial melt film processing
US9646831B2 (en) 2009-11-03 2017-05-09 The Trustees Of Columbia University In The City Of New York Advanced excimer laser annealing for thin films
US8889569B2 (en) 2009-11-24 2014-11-18 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse sequential lateral soldification

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