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WO2002103668A1 - Procede et appareil de commande d'ecran lcd nematique - Google Patents

Procede et appareil de commande d'ecran lcd nematique Download PDF

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Publication number
WO2002103668A1
WO2002103668A1 PCT/KR2002/000693 KR0200693W WO02103668A1 WO 2002103668 A1 WO2002103668 A1 WO 2002103668A1 KR 0200693 W KR0200693 W KR 0200693W WO 02103668 A1 WO02103668 A1 WO 02103668A1
Authority
WO
WIPO (PCT)
Prior art keywords
driver
display data
block
column
level
Prior art date
Application number
PCT/KR2002/000693
Other languages
English (en)
Inventor
Tae Kwang Park
Keun Myung Lee
Original Assignee
Leadis Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leadis Technology, Inc. filed Critical Leadis Technology, Inc.
Publication of WO2002103668A1 publication Critical patent/WO2002103668A1/fr

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only

Definitions

  • This invention in general relates to semiconductor circuits. More specifically, this invention relates to circuits for driving STN liquid crystal displays.
  • FIG. 1 shows a structure of conventional supertwisted nematic (“STN”) liquid crystal display (“LCD”) module, which comprises an LCD panel 101 consisting of row electrodes 102 and column electrodes 103, a row driver 104 for applying row driving voltages to the row electrodes 102, and a column driver 105 for applying column driving voltages to the column electrodes 103.
  • Pixels are formed at every cross- section of the row and column electrodes, such as at 106. Each pixel changes to black, white, or a different shade of gray or color depending on the voltages applied by the corresponding row and column electrodes across the liquid crystal to change the light transmittance.
  • each row electrode is selected sequentially (also called “scanning electrode") and the pixel data values corresponding to the selected scanning electrode are applied to the corresponding column electrode.
  • Each frame needs to be displayed repeatedly to maintain a certain RMS value of each pixel so that the frames can be recognized by human eyes without any flickering.
  • the conventional sequential driving methods suffers so- called a "frame response phenomenon.”
  • driving pulses of high-amplitude and short pulse width are required, which causes uneven brightness of the LCD panel.
  • Multi-line addressing (MLA) methods have been suggested for driving flat panel devices as alternatives to sequential driving methods.
  • MLA methods multiple row electrodes are selected simultaneously to enable multiple selection of row electrodes within a frame cycle to increase the effective duty cycle of the row voltage application.
  • orthogonal signals are applied to a set of row electrodes so that the individual electrodes can maintain the same effective RMS values within a frame.
  • FIG. 2 shows a block diagram of a conventional 4-line MLA column driver.
  • a display data RAM 121 stores data for display and outputs some of the display data for latch by a display data latch 122.
  • orthogonal row signals Fi(t) applied to a set of row electrodes are compared with the display data of the same set of row electrodes at an XOR block 123 column by column to find mismatches between the orthogonal signals Fi(t) and display data for each column.
  • a decoder block 124 calculates mismatch numbers based on the result of mismatches from the XOR block 123.
  • the data levels of the mismatch numbers are shifted at a level shifter block 126, and a voltage selector 127 selects a voltage level among 5 different voltages levels based on the level-shifted mismatch numbers.
  • the conventional MLA driver uses data and output latches, it requires a large chip area in its implementation, which adversely affect the performance of the driver. Therefore, there is a need for a new driver that requires less number of circuit components and chip area to improve the performance.
  • a preferred embodiment comprises a 3 -line output display data for storing display data, an XOR block for finding mismatches between each 3 -line output set of the stored display and orthogonal function signals, a decoder block for calculating mismatch numbers, a level shifter block for shifting the data level of the mismatch numbers to another level, and a voltage selector block for selecting a voltage level from 2 levels of voltage. Because data latches and output latches are not necessary, the driver of the present invention achieves a significant reduction in the circuit components and chip size without compromising the display quality.
  • Figure 1 is a block diagram of a conventional LCD.
  • Figure 2 is a block diagram of a conventional MLA driver.
  • Figure 3 is a block diagram of a new MLA driver of the present invention.
  • Figure 4 is an illustration of an embodiment of a display data RAM according to the present invention.
  • Figure 5 is an illustration of an alternative embodiment of a display data RAM. According to the present invention
  • Figure 6 is a schematic block diagram of the MLA driver.
  • Figure 7 is an illustration of an example of orthogonal functions used for the virtual-line MLA of the present invention.
  • FIG. 8 is a timing diagram for the MLA driver according to the present invention.
  • Figure 9 is an illustration of a structure of a display data RAM for color display in accordance with the present invention.
  • FIG. 3 shows a block diagram of a preferred embodiment of an MLA driver of the present invention.
  • the preferred embodiment includes a 3-line output display data RAM 201 that is capable of simultaneously/concurrently outputting 3 lines of data. Because 3 -line data items are outputted simultaneously, display data latches are no longer needed for calculating mismatch numbers with orthogonal functions. Moreover, since the output data items from the 3 -line output display data RAM are synchronized to the system clock, the output latches are also unnecessary.
  • the display data RAM 201 stores 168 rows and 128 columns of bits that represents pixel data for a 168x128 display.
  • the present invention employs a virtual-line MLA, where a "virtual" row signal is additionally provided after every three "real" row signals.
  • the virtual row signal is not used in accessing stored data. Instead, the virtual row signal is used only for the purpose of simplifying calculation of mismatch numbers and thereby facilitating calculation of column signals.
  • Three real row signals and one virtual row signal constitute a set of 4-line orthogonal signals that combine with display data to produce column signals that would produce the correct display when multiple row electrodes are simultaneously driven.
  • the following table compares the method of calculating mismatch numbers using the orthogonal function of the present invention with the convention method.
  • 3 real lines and a virtual line only 2 kinds of mismatch numbers may be used, namely, "1” and "3”, compared to the conventional 4-line MLA using 5 kinds of mismatch numbers of "0", "1", "2", "3", "4".
  • FIG. 4 schematically shows an embodiment of the 3 -line output display data RAM.
  • the display data RAM is also partitioned into blocks, such as block 0, 221, each block consisting of 3 rows. Scanning is performed on blocks of rows rather than individual rows.
  • the first line outputs at each scan 1(0,0), 1(3,0), 1(6,0), ... I(3x(block number), 0).
  • the second line outputs at each scan 1(1,0), 1(4,0), 1(5,0), ... I(3x(block number)+l, 0)
  • the third line outputs at each scan 1(2,0), 1(5,0), 1(6,0), ..., I(3x(block number)+2, 0).
  • the three lines output 1(0,0), 1(1,0), and 1(2,0) simultaneously, which are combined with orthogonal function signals.
  • the second line outputs at each scan: 1(1,1), 1(4,1),
  • the three lines output 1(0,1), 1(1,1), and 1(2,1) simultaneously, which are combined with orthogonal function signals.
  • FIG. 5 shows an alternative embodiment of a display data RAM of the present invention.
  • the display is partitioned into scan blocks of 3 scan lines.
  • the display data RAM is also partitioned, but the 3 display data items in adjacent rows along the same column are arranged within the display data RAM in a horizontal fashion to achieve a more efficient layout. For example, 1(0,0), 1(1,0), and 1(2,0) are arranged in horizontally rather than vertically.
  • FIG. 6 schematically illustrates the blocks of FIG. 3 in more detail except the display data RAM.
  • the XOR block 202 consists of triples of XOR gates, such as 261.
  • the three rows of display data along the same column currently output by the display RAM 201 are compared with orthogonal row signals Fi(t) at the XOR block 202 to compute mismatch numbers.
  • the decoder block 203 consists of 128 individual decoders, such as 262, each having 3 inputs for generating the number of mismatches for each column.
  • the mismatch numbers are used by the level shifter block 204 having 128 1-bit level shifters, such as 263, and the voltage selector 205 having 128 individual voltage selectors, such as 264, each selecting either +Vxl or -Vxl.
  • Each individual voltage selector 264 selects +Vxl for a mismatch number of "1" and -Vxl for a mismatch number of "3". Since a voltage level is selected from 2 voltage levels, the construction is simpler than that of the conventional method of selecting one voltage level from 5 voltage levels of-Vx2, -Vxl, Vc, +Vxl, and +Vx2.
  • FIG. 7 shows an example of orthogonal functions of signals applied to scan lines.
  • the scan lines are divided into blocks where each block is made of block of 3 lines and 1 virtual line rather than a block of 4 lines in the convention MLA.
  • FIG. 8 shows a timing diagram of the MLA method of the present invention.
  • the frame start signal 302 is first generated in sync with the system clock 301.
  • the scan block signal 303 counts the address of display data RAM blocks.
  • the display data of each block are outputted as a display data signal 304 and, at the same time, the signal for the mismatch numbers 306 are generated based on the display data signal 304 and row orthogonal signals 305.
  • FIG. 9 shows a block diagram of another display data RAM for use with a color display in accordance with the present invention.
  • the example shows a RAM 321 consisting of 56 rows by 128 x 3 columns of addressable bits for storing RGB pixel data.
  • Each primary color of RGB is represented by 3 bits making 8 different shades available for each primary color, and thus 512 different colors in combinations.
  • Each bit is stored in a memory cell such as 322.
  • a scan block such as scan block 325
  • three bits for Red in the first row such as 322, 323 and 324
  • a multiplexer such as 326
  • Three bits for Red in the second row within the activated scan block 325 are combined by a multiplexer to produce a gray-level output R(1,0).
  • three bits for Red in the third row within the activated scan block are combined by a multiplexer to produce a gray-level output R(2,0).
  • Each three gray level colors in the adjacent rows along the same column, such as R(0,0), R(1,0), and R(2,0) are then combined with the orthogonal functions to calculate the mismatch numbers.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un pilote permettant de commander un écran LCD nématique. Dans un mode de réalisation préféré, ledit pilote comprend des données d'affichage de sortie à 3 lignes permettant de stocker des données d'affichage, un bloc de disjonction exclusive permettant de trouver des défauts d'appariement entre chaque ensemble de sortie à 3 lignes de l'affichage stocké et des signaux de fonction orthogonaux, un bloc décodeur permettant de calculer des nombres de défaut d'appariement, un bloc déphaseur permettant de rétablir le niveau des données des nombres de défaut d'appariement à un autre niveau, et un bloc sélecteur de tension permettant de sélectionner un niveau de tension parmi 2 niveaux de tension. Etant donné que des verrous de données et des verrous de sortie ne sont pas nécessaires, le pilote de la présente invention permet une réduction significative au niveau des composants du circuit et de la taille de la puce sans affecter la qualité de l'affichage.
PCT/KR2002/000693 2001-06-19 2002-04-16 Procede et appareil de commande d'ecran lcd nematique WO2002103668A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2001/34741 2001-06-19
KR10-2001-0034741A KR100431532B1 (ko) 2001-06-19 2001-06-19 평면표시장치 및 그 구동방법

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WO2002103668A1 true WO2002103668A1 (fr) 2002-12-27

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100809699B1 (ko) * 2006-08-25 2008-03-07 삼성전자주식회사 디스플레이용 데이터 구동 장치, 데이터 출력 장치 및디스플레이용 데이터 구동 방법

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0135331A2 (fr) * 1983-08-19 1985-03-27 K-Tron International, Inc. Système et technique de vérification d'affichages à cristaux liquides
US4917465A (en) * 1989-03-28 1990-04-17 In Focus Systems, Inc. Color display system
US5158490A (en) * 1991-04-04 1992-10-27 Samsung Electron Devices Co., Ltd. Device for assembling STN liquid crystal module
EP0720140A2 (fr) * 1994-12-26 1996-07-03 Hitachi, Ltd. Méthode et appareil pour la sélection et l'application d'une tension de données dans un dispositif d'affichage à cristaux liquides à adressage actif
US5585950A (en) * 1993-04-12 1996-12-17 Casio Computer Co., Ltd. STN LCD device displaying multiple colors in response to different voltages which includes a retardation plate
WO1997001780A1 (fr) * 1995-06-26 1997-01-16 Minnesota Mining And Manufacturing Company Systeme de projection a affichage a cristaux liquides dans lequel des polariseurs optiques a film multicouche
JPH0943565A (ja) * 1995-07-25 1997-02-14 Samsung Electron Devices Co Ltd スーパーツイストネマチック（ｓｔｎ）型液晶表示素子およびその液晶配向膜の配向処理方法
US5638088A (en) * 1992-06-18 1997-06-10 Hitachi, Ltd. Method of driving STN liquid crystal panel and apparatus therefor
US5774103A (en) * 1995-09-05 1998-06-30 Samsung Display Devices Co., Ltd. Method for driving a liquid crystal display
DE19854875A1 (de) * 1997-12-03 1999-06-10 Hyundai Electronics Ind Flüssigkristallanzeige
US6031510A (en) * 1996-06-28 2000-02-29 Microchip Technology Incorporated Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3582919B2 (ja) * 1994-12-16 2004-10-27 旭硝子株式会社 画像表示装置の駆動方法
JP3503463B2 (ja) * 1997-02-27 2004-03-08 セイコーエプソン株式会社 セグメントドライバ
JP3927736B2 (ja) * 1998-09-30 2007-06-13 オプトレックス株式会社 駆動装置および液晶表示装置
JP3778244B2 (ja) * 1999-03-11 2006-05-24 オプトレックス株式会社 液晶表示装置の駆動方法および駆動装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0135331A2 (fr) * 1983-08-19 1985-03-27 K-Tron International, Inc. Système et technique de vérification d'affichages à cristaux liquides
US4917465A (en) * 1989-03-28 1990-04-17 In Focus Systems, Inc. Color display system
US5158490A (en) * 1991-04-04 1992-10-27 Samsung Electron Devices Co., Ltd. Device for assembling STN liquid crystal module
US5638088A (en) * 1992-06-18 1997-06-10 Hitachi, Ltd. Method of driving STN liquid crystal panel and apparatus therefor
US5585950A (en) * 1993-04-12 1996-12-17 Casio Computer Co., Ltd. STN LCD device displaying multiple colors in response to different voltages which includes a retardation plate
EP0720140A2 (fr) * 1994-12-26 1996-07-03 Hitachi, Ltd. Méthode et appareil pour la sélection et l'application d'une tension de données dans un dispositif d'affichage à cristaux liquides à adressage actif
WO1997001780A1 (fr) * 1995-06-26 1997-01-16 Minnesota Mining And Manufacturing Company Systeme de projection a affichage a cristaux liquides dans lequel des polariseurs optiques a film multicouche
JPH0943565A (ja) * 1995-07-25 1997-02-14 Samsung Electron Devices Co Ltd スーパーツイストネマチック（ｓｔｎ）型液晶表示素子およびその液晶配向膜の配向処理方法
US5774103A (en) * 1995-09-05 1998-06-30 Samsung Display Devices Co., Ltd. Method for driving a liquid crystal display
US6031510A (en) * 1996-06-28 2000-02-29 Microchip Technology Incorporated Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation
DE19854875A1 (de) * 1997-12-03 1999-06-10 Hyundai Electronics Ind Flüssigkristallanzeige

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KR100431532B1 (ko) 2004-05-14
KR20020096340A (ko) 2002-12-31

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