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WO2002011368A3 - Pre-fetching and caching data in a communication processor's register set - Google Patents

Pre-fetching and caching data in a communication processor's register set Download PDF

Info

Publication number
WO2002011368A3
WO2002011368A3 PCT/US2001/041485 US0141485W WO0211368A3 WO 2002011368 A3 WO2002011368 A3 WO 2002011368A3 US 0141485 W US0141485 W US 0141485W WO 0211368 A3 WO0211368 A3 WO 0211368A3
Authority
WO
WIPO (PCT)
Prior art keywords
event
register set
core processor
processing
data
Prior art date
Application number
PCT/US2001/041485
Other languages
French (fr)
Other versions
WO2002011368A2 (en
Inventor
Duane E Galbi
Wilson P Ii Snyder
Daniel J Lussier
Joseph B Tompkins
Bruce G Burns
Original Assignee
Conexant Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/640,258 external-priority patent/US6754223B1/en
Application filed by Conexant Systems Inc filed Critical Conexant Systems Inc
Priority to AU2001285384A priority Critical patent/AU2001285384A1/en
Publication of WO2002011368A2 publication Critical patent/WO2002011368A2/en
Publication of WO2002011368A3 publication Critical patent/WO2002011368A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Circuitry (100) to free the core processor (104) from performing the explicit read operation required to read data into the internal register set. The processor's register set (603B) is expanded and a 'shadow register' set (603C) is provided. While the core processor (104) is processing one event the 'context' and 'data' and other associated information for the next event is loaded into the shadow register set (603C). When the core processor (104) finishes processing an event, the core processor (104) switches to the shadow register set (603C) and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the 'context' and 'data' associated with the next event before the current event ends. In this case, the core processor (104) still starts processing the next event and the pre-fetch continues during the event processing.
PCT/US2001/041485 2000-07-31 2001-07-31 Pre-fetching and caching data in a communication processor's register set WO2002011368A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001285384A AU2001285384A1 (en) 2000-07-31 2001-07-31 Enhancing performance by pre-fetching and caching data directly in a communication processor's register set

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US22182100P 2000-07-31 2000-07-31
US60/221,821 2000-07-31
US09/640,258 US6754223B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor
US09/640,231 US6804239B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information
US09/639,915 US6888830B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters
US09/639,915 2000-08-16
US09/640,231 2000-08-16
US09/640,258 2000-08-16

Publications (2)

Publication Number Publication Date
WO2002011368A2 WO2002011368A2 (en) 2002-02-07
WO2002011368A3 true WO2002011368A3 (en) 2002-06-06

Family

ID=27499249

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/041485 WO2002011368A2 (en) 2000-07-31 2001-07-31 Pre-fetching and caching data in a communication processor's register set

Country Status (2)

Country Link
AU (1) AU2001285384A1 (en)
WO (1) WO2002011368A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023843B2 (en) * 2002-06-26 2006-04-04 Nokia Corporation Programmable scheduling for IP routers
GB0823702D0 (en) 2008-12-31 2009-02-04 St Microelectronics Res & Dev Processing packet streams
GB2466651A (en) * 2008-12-31 2010-07-07 St Microelectronics Security co-processor architecture for decrypting packet streams
US12282838B2 (en) 2018-05-04 2025-04-22 Apple Inc. Systems and methods for assigning tasks in a neural network processor
CN109300217B (en) * 2018-09-03 2021-03-12 深圳怡化电脑股份有限公司 Queuing and calling method, computer storage medium, queuing and calling server and system
CN114185513B (en) * 2022-02-17 2022-05-20 沐曦集成电路(上海)有限公司 Data caching device and chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805927A (en) * 1994-01-28 1998-09-08 Apple Computer, Inc. Direct memory access channel architecture and method for reception of network information
US5920561A (en) * 1996-03-07 1999-07-06 Lsi Logic Corporation ATM communication system interconnect/termination unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805927A (en) * 1994-01-28 1998-09-08 Apple Computer, Inc. Direct memory access channel architecture and method for reception of network information
US5920561A (en) * 1996-03-07 1999-07-06 Lsi Logic Corporation ATM communication system interconnect/termination unit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEE T A ET AL: "Low power data management architecture for wireless communications signal processing", VEHICULAR TECHNOLOGY CONFERENCE, 1998. VTC 98. 48TH IEEE OTTAWA, ONT., CANADA 18-21 MAY 1998, NEW YORK, NY, USA,IEEE, US, 18 May 1998 (1998-05-18), pages 625 - 629, XP010287765, ISBN: 0-7803-4320-4 *

Also Published As

Publication number Publication date
WO2002011368A2 (en) 2002-02-07
AU2001285384A1 (en) 2002-02-13

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