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WO2002009165A1 - Procede de polissage d'une plaquette - Google Patents

Procede de polissage d'une plaquette Download PDF

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Publication number
WO2002009165A1
WO2002009165A1 PCT/JP2001/005971 JP0105971W WO0209165A1 WO 2002009165 A1 WO2002009165 A1 WO 2002009165A1 JP 0105971 W JP0105971 W JP 0105971W WO 0209165 A1 WO0209165 A1 WO 0209165A1
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WO
WIPO (PCT)
Prior art keywords
polishing
wafer
work
film
polished
Prior art date
Application number
PCT/JP2001/005971
Other languages
English (en)
Japanese (ja)
Inventor
Shigeyoshi Netsu
Hisashi Masumura
Michito Sato
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Publication of WO2002009165A1 publication Critical patent/WO2002009165A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces

Definitions

  • the present invention relates to a polishing technique for a circular work requiring a high flatness, and for example, to a polishing method for producing a mirror-polished wafer, which is highly flat to a peripheral portion of the wafer.
  • semiconductor wafers used for device fabrication require extremely high flatness.
  • a silicon wafer manufacturing method is obtained by a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer, and the slicing process.
  • a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer, and the slicing process.
  • ⁇ Chamfering process for chamfering the outer periphery to prevent cracking and chipping of the wafer
  • ⁇ Rubbing process for flattening the wafer surface
  • chamfering and rubbing From the etching process to remove the processing strain remaining on the wafer, the polishing process to make the surface of the wafer mirror, and the cleaning process to clean the polished wafer to remove the abrasive and foreign matter adhering to it. It is configured.
  • the above steps show the main steps, and other steps such as a heat treatment step may be added or the order of the steps may be changed.
  • the polishing process of mirroring the surface of the wafer is very important because it is the process of determining the final shape of the wafer, that is, the quality of the wafer.
  • Some polishing machines are generally designed to combine rotation and orbit so that the momentum around the center of the work (the wafer) is equal to the momentum around the periphery.
  • a workpiece W is held on a holding plate 16 attached to a rotating holder 11 by vacuum suction or the like.
  • Abrasive cloth 15 is supplied onto polishing cloth 13 attached to surface plate 12 which is rotating from above, and polishing cloth 13 which rotates the surface of workpiece W (surface to be polished) 13 The surface is polished by applying a load to the surface while making sliding contact.
  • a method of holding a work a method of providing a backing pad on the holding surface of a holding plate made of metal or the like to fix the work, or a method such as ceramics or glass
  • a method of attaching a work to the holding plate via an adhesive or the like is also a method of attaching a work to the holding plate via an adhesive or the like.
  • a silicon wafer is polished like this to make it a mirror surface wafer, but when a semiconductor device is manufactured by forming a circuit on the surface of the mirror surface wafer, one piece is used. It is desirable to obtain as many devices as possible from the wafer, and in order to achieve this, the wafer must be as flat as possible over the entire surface, especially near the outer edge. Is required. Specifically, in the current standard, it is sufficient that high flattening is performed in a region excluding a certain area (for example, 3 mm in outer circumference) from the outer edge of the wafer. There is a growing demand for wafers with high flatness in the area of 2 mm or even 1 mm from the part.
  • FIG. 5 shows the change in the shape of the periphery of the wafer measured by the inventors after the primary polishing from the outer peripheral edge.
  • a jig called a retainer ring that protrudes from the holding surface by the thickness of the eave from the holding surface is provided on the outer periphery of the holding plate.
  • a method has been proposed in which a polishing cloth is submerged from the surface, or a method in which excessive polishing is suppressed by floating the peripheral portion of the anode using a small-diameter holding plate. I have. Further, a method in which a retainer ring and a small-diameter holding plate are combined as disclosed in Japanese Patent Application Laid-Open No. 8-257893 has been proposed.
  • the peripheral sag can be slightly improved, but for example, the peripheral sag at a position 2 mm from the outer edge can be reduced to 0.2 / It is very difficult to keep it below m.
  • the SFQR max of the surface reference is 0 ⁇ 15 / xm or less. ⁇ It was difficult to manufacture wafers stably.
  • SFQR Site Frontrons-sQuares Range
  • SFQR max represents the maximum value among SFQRs of all sites on the antenna. Disclosure of the invention
  • the present invention has been made in view of the above-mentioned problems, and suppresses generation of peripheral sag when polishing a circular work requiring extremely precise flatness such as a semiconductor wafer.
  • the surface-based SFQR max is extremely high, less than 0.15 / zm ⁇
  • the aim is to produce a stable amount of ewa.
  • the work in a method of holding a circular work with a holding plate and bringing the surface of the work into sliding contact with a polishing cloth for polishing, the work is polished by the work.
  • a coat film made of a material having a low speed is formed at least on the peripheral portion of the workpiece surface, and the central portion of the workpiece surface is exposed or the workpiece surface is exposed more than the peripheral portion.
  • the polishing of the peripheral portion of the work can be substantially delayed, and the peripheral portion can be polished. Can be prevented from being excessively polished and causing peripheral sagging.
  • the coating film is formed on the workpiece, the workpiece surface can be stably highly planarized regardless of the structure of the holding plate or the like.
  • the polishing method according to the present invention can be suitably applied when the work is a silicon wafer.
  • a high flatness including a region within 2 mm from the outer peripheral end can be achieved.
  • a wafer having a surface-based SFQR max force of 0.15 im or less can be stably manufactured.
  • the coat film is formed on a peripheral portion within 10 mm from the outer peripheral edge of the surface of the wafer.
  • the peripheral sag can be reliably suppressed. S can.
  • a silicon oxide film, a silicon nitride film, or a resin film is formed as the coating film.
  • Such a coating film has a polishing rate more moderate than that of a silicon wafer. Slowly, its speed can be controlled precisely, and it can be formed relatively easily around the wafer surface.
  • the formation of the silicon oxide film or the silicon nitride film is performed at least by the CVD (Chemical Vapor Deposition) or thermal treatment. After an oxide film or a nitride film is formed on the surface of the wafer, the peripheral portion of the wafer surface is masked and subjected to an etching process, thereby forming a central portion of the wafer. The oxide film or nitride film can be removed to expose the work surface or make it thinner than the peripheral part.
  • CVD Chemical Vapor Deposition
  • a desired oxide film or nitride film can be easily formed on the peripheral portion of the wafer surface. .
  • the resin film can be formed by applying the resin to a peripheral portion of the wafer surface by spin coating and then performing a heat treatment. .
  • a drying heat treatment for evaporating the organic solvent is performed. Apply heat treatment such as curing heat treatment to cure the resin.
  • a coat film according to the present invention is formed to form a work surface. By performing the polishing, it is possible to substantially suppress overpolishing of the peripheral portion of the work.
  • the present invention is applied to polishing requiring very high flatness, such as a semiconductor wafer, there is no need to improve the structure of the holding plate, and the conventional holding plate can be used.
  • ⁇ ⁇ Grinding while holding the wafer causes This achieves extremely high flatness over the entire surface up to the vicinity of the outer peripheral edge of the wafer, and also makes it possible to provide a mirror surface wafer with excellent surface characteristics.
  • Such a mirror surface wafer can form a circuit on the entire surface, and can improve the productivity and yield of semiconductor devices.
  • FIG. 1 is a schematic sectional view showing an example of a wafer before polishing on which a coating film according to the present invention has been formed.
  • FIG. 2 is a schematic view showing a part of a step of forming a thermosetting resin film according to the present invention.
  • Figure 3 is a graph showing the polishing rates for silicon wafers and various coating films.
  • FIG. 4 is a graph showing the amount of displacement of the thickness of the peripheral portion of the wafer measured in the example and the comparative example.
  • FIG. 5 is a schematic view showing an example of a wafer polishing apparatus.
  • FIG. 6 is a graph showing the displacement of the thickness of the peripheral portion of the wafer after polishing by the conventional method.
  • the polishing method according to the present invention can be applied to any polishing of thin circular workpieces requiring high flatness, but a silicon wafer is a preferred specific example. Will be described.
  • silicon wafers are grown from a silicon raw material melt by the Chizoralski method (CZ method), floating zone melting method (FZ method), etc.
  • CZ method Chizoralski method
  • FZ method floating zone melting method
  • the ingot is sliced, and the rough surface of the obtained wafer is removed.
  • etching is performed to remove the processing distortion and the like on the wafer surface.
  • surface grinding is performed instead of wrapping.
  • the wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished.
  • the wafer is made of a material having a lower polishing rate than the wafer.
  • the coating film is formed at least on the peripheral portion of the wafer surface, and is formed so that the wafer surface is exposed or thinner at the central portion of the wafer surface.
  • the back surface of the wafer is held and the surface of the wafer is polished.
  • a coat film made of a material having a low polishing rate is formed on at least a peripheral portion of the wafer surface, and then the surface is polished.
  • the silicon around the wafer can be delayed from being polished.
  • the silicon in the central portion is removed to some extent by polishing until the coat film in the peripheral portion of the wafer is removed, the silicon in the peripheral portion is removed. Substantial polishing is started. Therefore, even if the peripheral part of the wafer is removed at a higher polishing rate than the central part after the coat film is polished and removed, overpolishing of the peripheral part is prevented and generation of peripheral sag is suppressed. be able to.
  • peripheral sagging can be suitably prevented.
  • the coating film gradually thins from the outer edge to the center. It is even more preferable to form it so that it becomes more dense.
  • the coating film formed by the present invention is not particularly limited as long as it is made of a work, that is, a silicon wafer or a material having a low polishing rate, but is not particularly limited.
  • a silicon nitride film or a resin film is preferred.
  • the polishing rate of these coat films is a fraction to several tenths of that of silicon, and polishing of the silicon around the wafer begins. This is advantageous in that it can be effectively delayed and can be formed relatively easily.
  • the method of forming the silicon oxide film or the silicon nitride film is not particularly limited, but at least the oxide film or the nitride film is formed on the surface of the wafer by CVD or heat treatment. After the film is formed, the periphery of the wafer surface is masked and etched to form a silicon oxide film or a silicon nitride film on the wafer surface. It can be easily formed on the periphery.
  • the raw material is subjected to a heat treatment in an oxidizing atmosphere to form a thermal oxide film on the entire surface of the wafer, and then a tape or a resist is formed around the periphery.
  • a tape or a resist is formed around the periphery.
  • the oxide film is formed only on the peripheral portion according to the same procedure as above.
  • the CVD oxide film may be formed only on the peripheral portion by masking the central portion first and then performing CVD.
  • the method for forming the resin film is not particularly limited, either.A resin solution diluted with an organic solvent is applied to the peripheral portion of the wafer surface by spin coating, followed by heat treatment. It can be easily formed.
  • the resin is not particularly limited, but may be, for example, a thermosetting resin such as an epoxy resin.
  • the wafer W is fixed on the turntable 2 so that the center thereof is located on the rotation axis 3.
  • a thermosetting resin such as an epoxy resin dissolved in an appropriate solvent is applied to the periphery of the wafer through the supply nozzle 4 and then applied.
  • the epoxy resin coat film 1 can be easily formed only on the periphery of the wafer.
  • the resin is not limited to epoxy resin, and any resin can be used as long as it has a lower polishing rate than the work after curing.
  • the coating film is formed so that the central portion of the wafer surface is exposed or thinner than the peripheral portion.
  • the coating film 1 can be made thinner and the subsequent polishing time can be shortened. It is preferable because you can do it.
  • a coating film on the portion other than the peripheral portion of the wafer surface, for example, on the back surface of the wafer, but also on the back surface 6 as shown in FIG. If the wafer W is polished by forming the coat film 1, excessive etching and dirt on the rear surface of the wafer due to an abrasive or the like can be prevented, and the rear surface of the wafer can be prevented. The occurrence of scratches due to holding can also be prevented. Such prevention of dirt and scratches is particularly effective when a resinous coating film is formed.
  • the viscosity of the coating solution and the spin conditions are controlled.
  • the resin may flow into the surface of the wafer, and this phenomenon can be used to form a coat film only on the peripheral part of the surface of the wafer. is there.
  • PVB polyvinyl butyral
  • the wafer shown in FIG. 1 is an example in which the coating film according to the present invention is formed, and is formed only on the peripheral portion of the wafer front surface or only on the peripheral portion of the wafer front and back surfaces.
  • the coating film may be formed, and the work efficiency can be improved by reducing the portion where the coating film is formed as described above.
  • the coat film remaining on the back surface or the chamfered portion is washed and removed using a solution capable of dissolving and removing the coat film. Alternatively, it may be removed by polishing to remove the coating film, etching, mirror polishing, or the like.
  • a desired coat film can be easily formed by the above-described method, but the thickness of the coat film formed on the peripheral portion is as follows, for example. It can be determined by a simple method.
  • tl TH / Rc
  • the amount of the silicon removed in the central part during the time t1 The thickness TH of the coat film can be determined so that the thickness of the coat film coincides with the peripheral sag amount Y.
  • the peripheral sag (Y;), the silicon polishing rate (Rsi), and the coating film polishing rate (Rc) are measured in advance, the peripheral part The thickness (TH) of the coating film can be easily determined.
  • the polishing rate varies depending on the polishing conditions. However, according to the experiments performed by the present inventors, the polishing rate of the silicon itself was 0.6 to 0.6. When polishing is performed under normal polishing conditions of 7 / xmZ, the respective polishing rates are approximately as follows.
  • Epoxy resin film 0.02 to 0.04 / im / min
  • polishing conditions such as polishing pressure, or the conditions for forming the coating film.However, experiments should be performed in advance under the same conditions. Can be easily obtained with
  • FIG. 3 shows the results of an experiment on the polishing rate performed by the present inventors.
  • each coating film has a polishing rate of 1/10 or less as compared to silicon nano-electrode, which is higher than that of silicon. It is hard to be polished. Therefore, it is possible to delay polishing of the silicon in the peripheral portion only by coating thinly on the portion _ around the wafer, thereby effectively preventing peripheral dripping. Is out.
  • the above formula for deriving the thickness of the coating film is merely an example, and the thickness of the coating film may be determined after rubbing or as described above.
  • the shape of the wafer after polishing (raw material wafer), the overall polishing allowance, the material and manufacturing conditions of the coating film, the polishing conditions such as the abrasive used and the polishing pressure, or the surface of the abrasive to be polished In consideration of the change in hardness due to the doping amount of a dopant element such as boron or an impurity element such as nitrogen, the polishing rate may be determined in advance as appropriate, for example, by confirming the polishing rate by experiments.
  • the coat film After the coat film is formed on the peripheral portion, it can be polished using a conventional holding plate as shown in FIG. That is, the wafer W is vacuum-sucked and held through the through-holes in the holding plate 16 provided with a large number of through-holes, and the abrasive 15 is supplied to the polishing cloth 13. Polish the wafer surface by sliding it against the polishing cloth 13 while applying a predetermined pressing force. By performing such polishing, in the initial stage of polishing, the center of the The silicon is directly polished in the part, while the coat film with a low polishing rate is polished in the peripheral part, so that the central part of the wafer becomes thin once.
  • the silicon in the peripheral portion is polished at a higher polishing rate than the central portion, so that the thickness of the central portion and the peripheral portion eventually becomes almost equal. It is only necessary to finish polishing when it becomes the same.
  • the polishing method of the present invention can be applied at any stage in the polishing process, the peripheral sag is almost always generated by the primary polishing, which has the largest polishing allowance. It can be suitably applied to primary polishing. Therefore, after the primary polishing is performed by the method of the present invention, the secondary polishing is performed as necessary, and the final polishing is further performed, so that a very high flatness is obtained over the entire surface. It is possible to obtain a mirror surface having the following characteristics.
  • the present invention is not particularly limited with respect to the type of holding plate, the method of holding the wafer, and the like, and is also applicable to the case of polishing in a patch type. be able to. That is, the back surfaces of a plurality of wafers on which a desired coat film has been formed are adhered to a glass or ceramic plate via an adhesive or a wax. These wafers can be polished simultaneously.
  • the silicon wafer polished by the polishing method of the present invention suppresses the generation of peripheral sag, becomes a mirror-finished wafer having excellent flatness over the entire surface of the wafer, and shows a good yield of the wafer. Can be improved. In particular, it has a very high flatness with a SFQR max of 0.15 ⁇ ⁇ or less, including the area within 2 mm from the outer edge. ⁇
  • the wafer is stable regardless of the structure of the holding plate etc. It can be manufactured.
  • a circuit can be formed over the entire surface, and the productivity and yield of semiconductor devices can be significantly improved. I can do it.
  • the silicon wafer after etching (diameter: 8 inches (200 mm)) is formed by CVD to form a CVD oxide film on the surface of the wafer.
  • CVD chemical vapor deposition
  • the peripheral portion up to 5 mm from the outer peripheral edge of the anode was subjected to masking and etching treatment, and the central portion of the oxide film was removed to leave the CVD oxide film only in the peripheral portion.
  • the thickness of the CVD oxide film was calculated by the HU notation formula, and the CVD oxide film was formed based on the calculated value.
  • the polishing rate of silicon Rsi 0.6 ⁇ m
  • the polishing rate of the coating film (CVD oxide film) Rc 0.1 ⁇ m
  • the peripheral sagging Y Approximately 0.3 ⁇ (value obtained by polishing by the conventional method)
  • Polishing equipment Vacuum adsorption type single wafer polishing equipment
  • a silicon wafer of the same size as the wafer used in the embodiment was used.
  • polishing was performed under the same polishing conditions as in Example 1 without forming a coat film.
  • the thickness distribution of the peripheral portion was determined using a capacitance-type thickness measuring device with reference to a position 10 mm from the outer peripheral end. Excluded area: 2 mm around) was measured, and the results are shown in Fig. 4.
  • the wafer polished in the embodiment achieves extremely high flatness up to the peripheral part, and the displacement amount is less than 0.1 ⁇ even at a position 2 mm from the outer peripheral edge.
  • the SFQR max was 0.09 ⁇ , while the wafer polished in the comparative example (without coat film) improved more than the sag around the raw material anode.
  • the sagging started around 6 mm from the outer edge of the target, and there was a displacement of about 0.3 m at 2 mm from the outer edge.
  • SFQRmax was about 0.20 ⁇ .
  • peripheral sagging had already occurred in the periphery of the raw material wafer measured in advance after the etching.
  • the peripheral part of the wafer is thinner than the central part, although the polishing pressure is low and the polishing rate is low, if the polishing is further continued, the entire surface of the wafer is substantially polished under the same conditions (polishing rate), or the peripheral portion of the wafer is excessively polished. Therefore, when polishing is performed with a polishing allowance of about 10 ⁇ in the polishing process, a new peripheral sag as shown in FIG. 6 is generated.
  • the present invention is not limited to the above embodiment.
  • the above embodiment is merely an example, and has substantially the same configuration as the technical idea described in the claims of the present invention, and achieves the same operation and effect. Anything is included in the technical scope of the present invention.
  • the object to be polished to which the present invention can be applied is not limited to the silicon wafer, and high flatness of the entire surface is required. It can be applied to the required polishing of circular workpieces.
  • the present invention is not particularly limited with respect to the size of the work.
  • the method of controlling the thickness of the coat film is controlled so as to attain a high flatness after one step of polishing.
  • the final step is performed. It is necessary to have high flatness after perfect finish polishing.
  • the present invention is optimally used in primary polishing where peripheral sagging is most likely to occur.
  • subsequent polishing such as secondary polishing or finish polishing, may cause some sagging around the periphery. Therefore, the thickness of the coating film must be adjusted so that the first polishing completely achieves high flatness.
  • polishing may be performed by controlling the thickness of the film. That is, the present invention may be used so that a wafer with high flatness is obtained in a final product.
  • a coat film as in the present invention may be formed and polished at each polishing step.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

L'invention concerne un procédé de polissage circulaire d'une plaquette consistant à amener la surface avant de la plaquette en contact coulissant avec une toile abrasive fixée sur une plaque de fixation. Ce procédé consiste à former une pellicule de revêtement, fabriquée à partir d'une matière présentant un taux de polissage inférieur à celui de la matière de la plaquette, dans la périphérie de la surface avant de la plaquette et à former la pellicule dans la partie centrale de la surface avant de la plaquette de façon que la surface avant de la plaquette soit exposée ou que la pellicule de revêtement soit plus mince en son centre que sur sa périphérie, à soutenir la surface arrière de la plaquette, et à polir la surface avant de la plaquette. De préférence, la pellicule de revêtement est une pellicule d'oxyde de silicium, de nitrure de silicium, ou une pellicule de résine. Les affaissements périphériques peuvent être évités lors du polissage circulaire d'une plaquette, telle qu'une plaquette semi-conductrice nécessitant une planéité très précise, les plaquettes présentant une planéité si précise que le SFQR max. d'une surface de référence inférieure ou égale à 0,15νm peuvent être fabriquées de façon stable dans des zones situées à 2 mm de l'extrémité périphérique de la plaquette.
PCT/JP2001/005971 2000-07-21 2001-07-10 Procede de polissage d'une plaquette WO2002009165A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-220821 2000-07-21
JP2000220821A JP2002043257A (ja) 2000-07-21 2000-07-21 ワークの研磨方法

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WO2002009165A1 true WO2002009165A1 (fr) 2002-01-31

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237055A (ja) * 2005-02-22 2006-09-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法および半導体ウェーハの鏡面面取り方法
US8952496B2 (en) 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
JP5423384B2 (ja) * 2009-12-24 2014-02-19 株式会社Ｓｕｍｃｏ 半導体ウェーハおよびその製造方法
JP2013110322A (ja) * 2011-11-22 2013-06-06 Shin Etsu Handotai Co Ltd シリコン酸化膜の形成方法及び形成装置、並びにシリコンウェーハの研磨方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292922A (ja) * 1985-06-21 1986-12-23 Hitachi Hokkai Semiconductor Ltd 半導体装置の製造方法
JPH07335845A (ja) * 1994-06-15 1995-12-22 Toshiba Corp Ｓｏｉ基板の製造方法及び研磨装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292922A (ja) * 1985-06-21 1986-12-23 Hitachi Hokkai Semiconductor Ltd 半導体装置の製造方法
JPH07335845A (ja) * 1994-06-15 1995-12-22 Toshiba Corp Ｓｏｉ基板の製造方法及び研磨装置

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JP2002043257A (ja) 2002-02-08

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