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WO2002009148A2 - Systeme d'emission de rayonnements integre et son procede de fabrication - Google Patents

Systeme d'emission de rayonnements integre et son procede de fabrication Download PDF

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Publication number
WO2002009148A2
WO2002009148A2 PCT/US2001/022543 US0122543W WO0209148A2 WO 2002009148 A2 WO2002009148 A2 WO 2002009148A2 US 0122543 W US0122543 W US 0122543W WO 0209148 A2 WO0209148 A2 WO 0209148A2
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WIPO (PCT)
Prior art keywords
layer
earth metal
alkali earth
monocrystalline
oxide
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PCT/US2001/022543
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English (en)
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WO2002009148A3 (fr
Inventor
Barbara M. Foley
William Jay Ooms
James E. Prendergast
Kurt Eisenbeiser
Jamal Ramdani
Ravindranath Droopad
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Motorola, Inc.
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Priority to AU2001276964A priority Critical patent/AU2001276964A1/en
Publication of WO2002009148A2 publication Critical patent/WO2002009148A2/fr
Publication of WO2002009148A3 publication Critical patent/WO2002009148A3/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0262—Photo-diodes, e.g. transceiver devices, bidirectional devices
    • H01S5/0264—Photo-diodes, e.g. transceiver devices, bidirectional devices for monitoring the laser-output
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021—Silicon based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3201—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures incorporating bulkstrain effects, e.g. strain compensation, strain related to polarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials

Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to integrated, monolithic radiation systems including an electromagnetic radiation source and a wave guide.
  • GaAs Gallium arsenide
  • silicon wafers are available up to about 300 mm and are widely available at 200 mm.
  • the 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than GaAs.
  • a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of compound semiconductor material or in an epitaxial film of such material on a bulk wafer of compound semiconductor material.
  • a thin film of high quality monocrystalline compound semiconductor material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the compound semiconductor material.
  • FIGS. 1 - 3 and 11 - 12 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer ;
  • FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer
  • FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer
  • FIGS. 9 - 10 and 13 - 21 include illustrations of cross-sectional views of a portion of various radiation systems in accordance with the present embodiment.
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and compound semiconductor layer 26.
  • the template layer helps to initiate the growth of the compound semiconductor layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22 in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry ' .
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer
  • the amorphous ' intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate .and with the overlying compound semiconductor material.
  • the material could be an oxide or nitride having a lattice structure substantially matched to the substrate and to the subsequently applied semiconductor material.
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • the compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • Group IIIA and VA elements III-V semiconductor compounds
  • mixed III-V compounds Group II (A or B) and VIA elements
  • II-VI semiconductor compounds II-VI semiconductor compounds
  • Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide
  • Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention.
  • Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g. , compound semiconductor layer 26 formation.
  • Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
  • semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
  • semiconductor layer 38 comprises compound semiconductor material (e . g. , a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38.
  • compound semiconductor material e . g. , a material discussed above in connection with compound semiconductor layer 26
  • a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • Example 1 illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of S ⁇ B ⁇ JTiO. where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer is formed by capping the oxide layer.
  • the template layer is preferably 1-10 monolayers of Ti-As, Sr- O-As, Sr-Ga-0, or Sr-Al-O. By way of a preferred example, 1-2 monolayers of Ti-As or Sr-Ga-0 have been shown to successfully grow GaAs layers.
  • monocrystalline substrate 22 is a silicon substrate as described above.
  • the accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer.
  • the accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr0 3 , BaZr0 3 , SrHf0 3 , BaSn0 3 or BaHf0 3 .
  • a monocrystalline oxide layer of BaZr0 3 can grow at a temperature of about 700 degrees C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.
  • An accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials in the indium phosphide (InP) system.
  • the compound semiconductor material can be, for example, indium phosphide (InP) , indium gallium arsenide (InGaAs) , aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP), having a thickness of about 1.0 nm to 10 ⁇ m.
  • a suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium- phosphorus (Zr-P) , hafnium-arsenic (Hf-As) , hafnium- phosphorus (Hf-P) , strontium-oxygen-arsenic (Sr-O-As) , strontium-oxygen-phosphorus (Sr-O-P) , barium-oxygen- arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen-phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials.
  • the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template.
  • a monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer.
  • the resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
  • a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate.
  • the substrate is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer material is Sr ⁇ B ⁇ JTiO j , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the II-VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) .
  • a suitable template for this material system includes 1-10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface.
  • a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the'ZnSeS.
  • This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP) , an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • AlGaAs aluminum gallium arsenide
  • InGaP aluminum gallium phosphide
  • AlGaP aluminum indium phosphide
  • AllnP a gallium arsenide phosphide
  • InGaP indium gallium phosphide
  • buffer layer 32 includes a GaAs x P x _ x superlattice, wherein the value of x ranges from 0 to 1.
  • buffer layer 32 includes an In Ga x P superlattice, wherein the value of y ranges from 0 to 1.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • the template for this structure can be the same of that described in example 1.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer.
  • the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2.
  • Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2.
  • a buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline compound semiconductor material layer.
  • the buffer layer can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) .
  • buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%.
  • the buffer layer preferably has a thickness of about 10-30 nm. Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
  • Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) .
  • amorphous layer 36 may include a combination of SiO x and Sr z Ba 1 _. Ti0 3 (where z ranges from 0 to 1) , which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5- 6 nm.
  • Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
  • layer 38 includes the same materials as those comprising layer 26.
  • layer 26 includes GaAs
  • layer 38 also includes GaAs.
  • layer 38 may include materials different from those used to form layer 26.
  • layer 38 is about 1 monolayer to about 100 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired.
  • this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal.
  • the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr x Ba 1 _ x Ti0 3 , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide.
  • the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal.
  • a crystalline semiconductor buffer layer between the host oxide and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline compound semiconductor layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline compound semiconductor layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered
  • the 2x1 structure includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer .
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750 ⁇ C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material .
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti- As bond, a Ti-O-As bond or a Sr-O-As .
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention.
  • Single crystal SrTi0 3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the buffer layer is formed overlying the template layer before the deposition of the monocrystalline compound semiconductor layer. If the buffer layer is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes in the proper environment
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • TEM Transmission Electron Micrograph
  • a single crystal SrTi0 3 accommodating buffer layer was grown epitaxially on silicon substrate 22.
  • an amorphous interfacial layer forms as described above.
  • GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other III-V and II-VI monocrystalline compound semiconductor layers can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • Each of the variations of compound semiconductor materials and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the compound semiconductor layer.
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
  • hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively.
  • strontium titanate can be capped with a layer of strontium or • strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen.
  • FIG. 9 illustrates a top view
  • FIG. 10 illustrates a side view of a monolithic, integrated system 90 for transmitting electromagnetic radiation in accordance with an exemplary embodiment of the present invention.
  • System 90 includes a radiation emitting device 92, a wave guide 94, and a radiation detection device 96.
  • emitting device 92 and detection device 96 may be configured to transmit and receive electromagnetic radiation of various wavelengths.
  • emitting device 92 is a laser or a light emitting diode
  • detection device 96 is a photo detector, and both are formed within a compound semiconductor region of system 90.
  • Laser 92, wave guide 94, and photo detector 96 are formed over a Group IV substrate 1002 and an amorphous oxide layer 1004 formed thereon, wherein amorphous oxide layer 1004 is formed according the method described above, for example, in connection with layer 36.
  • laser 92, guide 94, and detector 96 may be formed over a monocrystalline oxide such as layer 24 discussed above in connection with FIGS. 1,2, and 5.
  • laser 92 includes an edge emitting laser, having a first cladding layer 1006, an active layer 1008; and a second cladding layer 1010.
  • Layers 1006-1010 may be formed of any suitable semiconductor material such as the compound semiconductor materials discussed above in connection with layer 26.
  • first cladding layer 1006 may include n-type doped AlGaAs
  • active layer 1008 may include GaAs
  • second cladding layer 1010 may include p-type doped AlGaAs, where each of layers 1006-1010 is epitaxially formed over substrate 1002.
  • portions 1012-1016 may include a monocrystalline oxide such as that described above in connection with any of FIGS. 1-3.
  • portion 1012 may include strontium titanate doped with a material ( e . g. , an impurity), and portions 1014 and 1016 may include undoped strontium titanate such that the refractive index of portions 1014,1016 is lower than the refractive index of portion 1012.
  • Detector 96 is generally configured to convert light received from laser 92 into an electrical signal.
  • detector 96 includes an active region 1022 and contacts 1024 and 1026.
  • Active region 1022 may be formed of a variety of crystalline, polycrystalline, or amorphous materials such as silicon, GaAs, and InGaAs; however, in accordance with one embodiment of the present invention, region 1022 is formed of the same material used to form region 1008 of laser 92, such as monocrystalline GaAs.
  • Monolithic system 90 may be formed on Group IV substrate 1002, which may include various devices such as CMOS circuits formed therein, by forming amorphous layer 1004, using a suitable cap layer that is not shown in
  • FIGS. 9 or 10 as discussed above in connection with FIGS. 3 and 7.
  • Suitable layers for cladding and active regions of a laser are then formed on the monocrystalline substrate.
  • an AlGaAs layer 1102, a GaAs layer 1104, and an AlGaAs layer 1106 can be formed over now amorphous layer 1004.
  • layers 1102, 1106 and active region 1104 can be formed over a monocrystalline oxide layer as discussed above in connection with FIGS. 1-2.
  • a portion of layers 1102, 1104, and 1106 may be removed to form structure 1200, illustrated in FIG. 12, using suitable photolithographic and etching techniques.
  • a portion of all of layers 1102-1106 is removed from a region 1202, and a portion of layer 1106 is removed from a region 1204 to define a portion of detector 96.
  • Contacts 1024 and 1026 may then be formed on a surface of layer 1022, for example, using conductive material (e . g. , metal) deposition and etch techniques.
  • Wave guide 94 may then be formed on structure 1200 by depositing radiation transmissive material suitable for second portion 1014, forming a patterned portion 1012 over portion 1014 using, for example, photolithography techniques, and depositing material to form third portion 1016 of wave guide 94, such that one end of guide 94 is aligned to and preferably contacts an output section of source 92 and another end of guide 94 is in alignment with and preferably contacts an input of ' detector 96.
  • system 90 may suitably include electronic circuits coupled to emitter 92 and/or detector 96.
  • system 90 may include drive circuitry, for emitter 92 or detector 96, formed within either substrate 1002 and/or within compound semiconductor material epitaxially grown thereon.
  • FIGS. 13 and 14 illustrate a top view and a side view, respectively, of a planar system 1300, including a microelectronic circuit 1302, an emitter 1304 (e . g. , laser) coupled to circuit 1302, a wave guide 1306, and a detector 1308 in accordance with an alternate embodiment of the present invention.
  • Emitter 1304, wave guide 1306, and detector 1308 of system 1300 may be formed using the process and materials described above in connection with system 90, except that the emitter, wave guide, and detector are formed within a trench 1310 created within a monocrystalline Group IV semiconductor substrate 1312, such that light can be transmitted from emitter 1304 toward detector 1308 along a path that is substantially parallel to a bottom surface of the groove formed in the substrate.
  • Planar structure 1300 also includes a planarizing or filler compound 1404, which may include spin on glass or the like.
  • Trench 1310 may be formed by etching substrate 1312 along crystalline planes.
  • substrate 1312 includes (100) silicon
  • trench 1310 may be formed by exposing substrate 1312 to a wet etch environment such that trench 1310 includes a substantially planar surface 1402 that is substantially parallel to the substrate surface, over which layer 1314 and laser 1304 may be formed, and sidewalls 1408 that are substantially parallel to other crystalline planes of substrate 1312.
  • circuit 1302 may be formed within substrate 1312 and coupled to source 1304 by, for example, using a conductive plug 1410 and a conductive line 1412 formed over planarizing material 1404.
  • circuit 1302 could be formed within a monocrystalline compound semiconductor layer grown above an amorphous oxide layer using a suitable template layer to facilitate monocrystalline growth of the additional semiconductor layer.
  • Circuit 1302 may include any device suitable for driving laser 1304 and may be formed within any suitable semiconductor material.
  • the semiconductor material may include Group rv compounds such as silicon, germanium, silicon germanium, silicon germanium carbide, or compound semiconductor material such as GaAs and other materials discussed above in connection with examples 1-6 provided above .
  • both systems 90 and 1300 may include other electronic circuits in addition to circuit 1302.
  • systems 90 and 1300 may include tuning circuits, feedback control circuits, and the like, which are discussed in greater detail hereinbelow.
  • FIG. 15 illustrates a top view of a system 1500 in accordance with another exemplary embodiment of the present invention.
  • System 1500 is configured to transmit electromagnetic radiation such as light from a source to a location "off chip.”
  • system 1500 includes an emitter 1502 as a radiation source, a wave guide 1504
  • Emitter 1502 and wave guide 1504 are formed using the materials and processes described above in connection with emitters 92, 1304 and wave guides 94, 1306. In particular, emitter 1502 and guide 1504 are formed over a monocrystalline Group IV substrate, as described above.
  • a first end 1508 of cable 1506 is generally aligned with either an output end of a wave guide 1504 or an output of source 1502 (in which case wave guide 1504 is not required) , such that substantially all radiation generated by source 1502 enters cable 1506.
  • a V-shaped groove 1602, illustrated in FIG. 16 is formed in a substrate 1604. Cable 1506, which generally has a circular cross section having a diameter, can then be fixedly attached to substrate 1604 within groove 1602, such that at least a portion of cable 1506 resides within a portion groove 1602.
  • groove 1602 is formed by etching substrate 1604, and a depth of groove 1602 is selected such that cable 1506 and output from guide 1504 or laser 1502 are substantially aligned, e . g. , a center of cable 1506 and a center of guide 1504 are aligned.
  • FIG. 17 illustrates another embodiment of the invention in which both a radiation emitting source and a fiber optic cable are located within a trench formed within a substrate.
  • a system 1700 includes an edge emitting radiation source 1702, such as an edge emitting laser, formed within a first portion of a groove 1704, a fiber optic cable 1706 formed within a second portion 1708 of the groove, and a source control circuit 1710 formed within a substrate 1712 and coupled to source 1702 via conductive path 1714.
  • source 1702 includes an edge emitting laser formed according to the process described above in connection with source 1304 and trench portions 1704 and 1708 are formed according to the process described above in connection with trench 1310.
  • FIG. 18 illustrates a system 1800, including a feedback control loop, in accordance with yet another embodiment of the present invention.
  • System 1800 includes a radiation emitter 1802, a radiation detector 1804, a feedback control circuit 1806, a driver 1808, an optical device 1810 ( e . g. , a fiber optic cable), and a wave guide 1812 coupled to both device 1810 and radiation detector 1804.
  • each of emitter 1802, detector 1804, circuit 1806, driver 1808, and guide 1812 are monolithically integrated on a Group IV substrate.
  • system 1800 is configured to control an output from source 1802, for example, at a desired intensity level, using a feedback loop 1814, including a feedback path from detector 1804 to device 1802.
  • detector 1804 In accordance with the illustrated example, detector 1804
  • circuit 1806 (with appropriate receiver circuitry) converts radiation emission such as light received from source 1802 into an electrical signal, circuit 1806 manipulates the signal from detector 1804 with an appropriate gain, and driver circuit 1808 sends a signal to source 1802 in response to a signal received from circuit 1806.
  • Detector 1804 circuitry, feedback circuit 1806, and driver circuit 1808 may be formed in any suitable semiconductor layer.
  • circuit 1808 may be formed within the Group IV (e . g. , silicon) substrate or within any semiconductor material deposited thereon.
  • FIG. 19 illustrates a monolithic multiplexing system 1900 in accordance with another exemplary embodiment of the present invention.
  • System 1900 includes a radiation source 1916, which includes one or more light sources (e. g. , light emitting diodes or lasers) 1902, 1904, 1906, 1908, and 1910, wherein each light source is capable of producing radiation having, respectively; a wavelength of 81, 82, 83, 84, and 85; a wave guide 1912; and a fiber optic cable 1914.
  • light sources e. g. , light emitting diodes or lasers
  • Light sources 1902-1910 and guide 1912 may be formed and cable 1914 may be attached to a substrate 1919 according to the methods described above in connection with FIGS. 9-17, except that in the embodiment illustrated in FIG. 19, guide 1912 includes multiple branches extending to a plurality of sources.
  • sources 1902-1910 are formed over an amorphous oxide layer such as layer 36, illustrated in FIG. 3, or a monocrystalline oxide layer such as layer 24, illustrated in FIG. 1, and guide 1912 is formed within or above the amorphous or monocrystalline layers.
  • source 1916 includes a radiation emitting source capable of emitting radiation over a spectrum of wavelengths and a grating coupled to the source for separating a plurality of wavelengths from the spectrum of wavelengths, such that a desired wavelength or wavelengths may be selected.
  • source 1916 may include a fiber optic cable coupled to a grating to selectively transmit light of a desired wavelength or wavelengths to a portion or portions of guide 1912.
  • FIG. 20 illustrates a top view of a monolithic demultiplexing system 2000 in accordance with another exemplary embodiment of the present invention.
  • System 2000 includes a radiation source which brings radiation having a plurality of wavelengths onto the chip and/or a radiation transmission medium such as a fiber optic cable 2004, a demultiplexer 2006, wave guides 2008, 2010, and 2012, and radiation detectors 2016, 2018, and 2020.
  • the source may include a plurality of radiation emitting devices ( e . g. , in an array) or a fiber optic cable carrying radiation having a plurality of wavelengths.
  • System 2000 is generally configured to transmit radiation of multiple wavelengths from source 2002 through a cable 2004, separate the radiation according to wavelength at demultiplexer 2006, and send radiation of a particular wavelength to each of detectors 2016-2020.
  • demultiplexer 2006 includes one or more directional couplers epitaxially formed over an oxide such an oxide described above in connection with FIGS. 1-3.
  • Each decoupler includes a grating and is configured to separate radiation of one wavelength from a stream of radiation including radiation of one or more wavelengths. The separated light may then be transmitted to one of detectors 2016-2020 through one of wave guides 2008-2012 and/or directed toward one of detectors 2016-2020 using beveled, reflective surfaces to direct the light toward the detector.
  • System 2000 may also suitably include a circuit 2022 configured to tune one or more of the directional couplers within demultiplexer 2006.
  • circuit 2022 may be formed within the Group IV substrate.
  • circuit 2022 may be formed within one or more of the epitaxial compound semiconductor layers formed above the Group IV substrate.
  • Source 2002, guides 2008-2012, and detectors 2016- 2020 may be formed in accordance with processes described above in connection with source 92, guide 94, and detector 96, and source 2002 may be formed on a separate substrate than the substrate that includes guides 2008-2012 and detectors 2016-2020. Further, cable 2004 may be coupled to source 2002 and demultiplexer 2006 according to the method described above in connection with attaching cable 1506 to source 1502.
  • FIG. 21 illustrates a system 2100, including a vertical cavity surface emitting laser (VCSEL) 2102 in accordance with another exemplary embodiment of the invention.
  • VCSEL 2102 includes bottom mirror layers 2104; a laser cavity region 2106; an upper mirror region 2108; a ring-shaped contact 2110; and a wave guide 2112, having cladding layers 2114 and a core layer 2116.
  • wave guide 2116 is illustrated as formed above VCSEL 2102, in accordance with an alternative embodiment of the present invention, VCSEL 2102 may be formed over a monocrystalline oxide layer (which may have been exposed to an anneal process to cause the oxide to become amorphous) , which oxide layer serves as a portion of the wave guide.
  • VCSEL 2102 may suitably be formed on top of or over a portion of the wave guide.
  • VCSEL 2102 is formed by epitaxially growing lower mirror layers 2104, laser cavity region 2106 layers, and upper mirror layers 2108 over a Group IV substrate 2122 (which may include various devices such as CMOS circuits formed therein) and an amorphous oxide layer 2124, as discussed above in connection with FIGS. 3 and 7.
  • a Group IV substrate 2122 which may include various devices such as CMOS circuits formed therein
  • amorphous oxide layer 2124 as discussed above in connection with FIGS. 3 and 7.
  • mirror layers 2104, 2108 and active region 2106 may be formed over a monocrystalline oxide layer as discussed above in connection with FIGS. 1-2.
  • Lower mirror layers 2104 include alternating layers of compound semiconductor materials.
  • VCSEL 2102 may be directly coupled to a fiber optic cable or other device.
  • a monolithically integrated optical system comprising:
  • an optical wave guide deposited in alignment with the compound semiconductor laser and configured to transmit emissions from the laser.
  • the monolithically integrated optical system of claim 1 further comprising a photo detector coupled monolithically to the wave guide and configured to receive the emissions from the laser.
  • optical wave guide comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.
  • a monolithically integrated system comprising:
  • a radiation emitting device formed of compound semiconductor material epitaxially deposited overlying the oxide layer
  • a wave guide deposited overlying the oxide layer and configured to receive and transmit radiation emitted from the radiation emitting device.
  • the system of claim 5 further comprising a radiation detector monolithically formed overlying the oxide layer and coupled to receive radiation transmitted by the wave guide.
  • the radiation detector is formed of material epitaxially grown overlying the oxide layer, the material selected from the group consisting of silicon, III-V compound semiconductor materials and II-VI compound semiconductor materials.
  • the radiation detector comprises a material selected from silicon, gallium arsenide, and indium gallium arsenide.

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Abstract

Il est possible de faire croître des couches épitaxiales de matériaux semi-conducteurs composites de haute qualité sur de grandes tranches de silicium et faisant croître tout d'abord une couche tampon réceptrice sur une tranche de silicium. Cette couche tampon réceptrice est une couche d'oxyde monocristallin séparée de la tranche de silicium par une couche d'interface amorphe de silice. Cette couche d'interface amorphe dissipe les contraintes et permet la croissance d'une couche tampon réceptrice d'oxyde monocristallin. Toute inadéquation de grille entre la couche tampon réceptrice et le substrat de silicium est compensée par la couche d'interface amorphe. Il est possible de créer des systèmes de rayonnement, dont des sources de rayonnement telles que des diodes électroluminescentes ou des lasers et des guides d'onde dans le matériau semi-conducteur composite épitaxial de haute qualité et au-dessus des couches d'oxyde.
PCT/US2001/022543 2000-07-24 2001-07-18 Systeme d'emission de rayonnements integre et son procede de fabrication WO2002009148A2 (fr)

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WO2010118529A1 (fr) * 2009-04-17 2010-10-21 Arise Technologies Corporation Structure de base pour dispositifs a semi-conducteur iii-v sur des substrats de groupe iv et son procédé de fabrication
CN114203838A (zh) * 2021-12-10 2022-03-18 中国电子科技集团公司第四十四研究所 一种集成侧向探测器的超辐射发光二极管芯片及制备方法

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US5225031A (en) * 1991-04-10 1993-07-06 Martin Marietta Energy Systems, Inc. Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process
US5323023A (en) * 1992-12-02 1994-06-21 Xerox Corporation Epitaxial magnesium oxide as a buffer layer on (111) tetrahedral semiconductors
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Publication number Priority date Publication date Assignee Title
WO2010118529A1 (fr) * 2009-04-17 2010-10-21 Arise Technologies Corporation Structure de base pour dispositifs a semi-conducteur iii-v sur des substrats de groupe iv et son procédé de fabrication
CN114203838A (zh) * 2021-12-10 2022-03-18 中国电子科技集团公司第四十四研究所 一种集成侧向探测器的超辐射发光二极管芯片及制备方法
CN114203838B (zh) * 2021-12-10 2024-03-29 中国电子科技集团公司第四十四研究所 一种集成侧向探测器的超辐射发光二极管芯片及制备方法

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