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WO2002007358A1 - Recepteur amcr - Google Patents

Recepteur amcr Download PDF

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Publication number
WO2002007358A1
WO2002007358A1 PCT/JP2000/004757 JP0004757W WO0207358A1 WO 2002007358 A1 WO2002007358 A1 WO 2002007358A1 JP 0004757 W JP0004757 W JP 0004757W WO 0207358 A1 WO0207358 A1 WO 0207358A1
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WO
WIPO (PCT)
Prior art keywords
interference
channel
selector
signal
interference replica
Prior art date
Application number
PCT/JP2000/004757
Other languages
English (en)
Japanese (ja)
Inventor
Tetsuhiro Futami
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2000/004757 priority Critical patent/WO2002007358A1/fr
Publication of WO2002007358A1 publication Critical patent/WO2002007358A1/fr

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  • the present invention relates to a CDMA receiver having a function of removing interference.
  • CDMA Code Division Multiple Access or Code Division Multiple Access
  • the CDMA system has features such as the ability to easily increase the system capacity and the flexibility to accommodate channels (users) of various communication speeds. Therefore, the CDMA system has attracted attention as an access method in mobile communication systems. I have.
  • the CDMA communication system needs a function to accurately remove the inter-channel interference from the received signal.
  • research on techniques for removing interference in a CDMA communication system has been conducted, and various proposals have already been made.
  • FIG. 1 is a block diagram of an example of a CDMA receiver having an interference canceling function.
  • a CDMA receiving device the basics in a CDMA communication system are described. Indicates a local office.
  • the signal received by the antenna 1 is converted by the receiver 2 into a signal in the baseband band.
  • the output of the receiving section 2 is given to an interference canceller 5 after being subjected to predetermined processing in an AZD converter 3 and a path search circuit 4.
  • the interference canceller 5 generates an interference replica of the received signal r (output of the path search circuit 4), and subtracts the interference replica from the received signal r. This eliminates interference between spreading codes, that is, interference between users.
  • the “interference replica” means an interference wave created simulated.
  • the received signal from which interference has been removed as described above is decoded for each channel by each of the decoders 6-1 to 6-n.
  • the multistage interference canceller can improve the accuracy of the received signal by repeating the interference removal processing. That is, first, in the first stage, an interference replica is generated for each channel, and interference is suppressed by subtracting interference replicas other than the target channel from the received signal. Subsequently, in the second stage or subsequent stages, a process of generating and subtracting an interference replica from the received signal in which interference has been suppressed by the process of the previous stage is performed. Then, in the final stage (demodulation stage), the signal is demodulated for each channel. At this time, in the demodulation stage, the process of generating an interference replica and subtracting it from the received signal is not performed.
  • the number of stages may be counted with or without the final stage (demodulation stage). In the following, the number of stages is counted without including the final stage.
  • FIG. 2 is a block diagram of an existing multi-stage interference canceller. Here, a two-stage parallel multistage interference canceller is shown.
  • Parallel multi-stage interference cancellers are installed in parallel with each other for each stage.
  • M interference replica generation units (IRU) 11 are provided.
  • each interference replica generation unit 11 of each stage is provided for a corresponding channel.
  • Each of the interference replica generation units 11 in the first stage is provided with a received signal (received signal r shown in FIG. 1). Then, each interference replica generation unit 11 generates an interference replica and a symbol replica based on the received signal. A “symbol replica” is a data symbol created simulated. Then, the interference replica power generated by each interference replica generation unit 11 is added by the adder 12, and the addition result is subtracted from the received signal.
  • the signal from which the interference replica has been subtracted is referred to as “interference residual signal (or residual signal)”.
  • the symbol replica generated by each interference replica generation unit MI is sent to the corresponding interference replica generation unit 11 of the second stage.
  • Each interference replica generation unit 11 of the second stage has an interference residual signal output from the first stage and a corresponding interference replica generation unit 11 of the first stage, respectively. You will be given a sympol replica. At this time, each interference replica generation unit 11 generates a new interference replay power and symbol replay power based on the given interference residual signal and symbol replica, respectively. Then, the interference replicas are added to each other, and the added value is subtracted from the interference residual signal output from the first stage. The interference residual signal from which the interference replica has been subtracted in the second stage is provided to each demodulator 13 of the demodulation stage. The symbol replica generated by each interference replica generation unit 11 of the second stage is provided to the corresponding demodulator 13. In the demodulation stage, each demodulator 13 demodulates a signal based on the interference residual signal output from the second stage and the corresponding symbol replica. This Thereby, data is demodulated for each channel.
  • the multi-stage interference canceller a plurality of interference replica generation units are assigned to each channel, and the received signal can be obtained with high accuracy by repeatedly removing interference components from the received signal. .
  • the number of interference replica generation units provided for each channel is fixedly determined. For example, in the configuration shown in FIG. 2, two interference replica generation units are fixedly provided for each channel.
  • the power of the transmission signal and the communication environment of the transmission path are different for each channel.
  • a channel in which three or more interference replica generation units are provided to improve characteristics and (2) an interference elimination characteristic is converged.
  • the interference component cannot be sufficiently removed in a specific channel.
  • the characteristics are degraded by repeating the interference removal processing more than necessary on a specific channel.
  • An object of the present invention is to appropriately or flexibly allocate resources for eliminating interference in a CDMA receiver having a function of eliminating interference.
  • a CDMA receiving apparatus of the present invention is configured to receive and demodulate a signal in which a plurality of channels are multiplexed in a CDMA communication system, and to remove a plurality of interference components of a corresponding channel from a received signal.
  • a desired number of removal units can be assigned to each channel. This makes it possible to flexibly set the number of times of interference cancellation processing to be performed for each channel. For example, it is possible to repeatedly execute the interference cancellation processing for a specific channel while executing the interference cancellation processing only once for another channel.
  • the control means determines, for example, the number of removal means to be assigned to each channel based on the characteristics of a signal transmitted via each channel. For example, if the determination is made based on the received power, more elimination means are assigned to the channel with the higher received power. Here, a channel having a large received power has a large interference with other channels. Therefore, by allocating more canceling means to a channel having a large received power, efficient interference cancellation is performed as a whole. As another method, the number of removing means to be assigned is determined based on, for example, a signal power to interference power ratio or a communication speed.
  • FIG. 1 is a block diagram of an example of a CDMA receiver having an interference canceling function.
  • FIG. 2 is a block diagram of an existing multi-stage interference canceller.
  • FIG. 3 is a block diagram of the CDMA receiver according to the first embodiment of the present invention.
  • FIG. 4 is a configuration diagram of the interference replica generation unit.
  • FIG. 5 is a configuration diagram of the demodulator.
  • FIG. 6 is a diagram illustrating an example of the first selector.
  • FIG. 7 is a diagram illustrating an example of the second selector.
  • FIG. 8 is a diagram illustrating an example of the selector block.
  • FIG. 9 is a diagram illustrating an example of the third selector.
  • FIG. 10 shows an example of the user management table.
  • FIG. 11 is an example of the selector management table.
  • FIG. 12 is a diagram illustrating an operation example of the interference canceller according to the first embodiment.
  • FIG. 13 is a block diagram of a CDMA receiver according to a second embodiment of the present invention.
  • FIG. 14 is a diagram illustrating an example of the fourth selector.
  • Figure 15 shows an example of the demodulator management table.
  • FIG. 16 is a diagram illustrating an operation example of the interference canceller according to the second embodiment.
  • FIG. 17 is a block diagram of a CDMA receiver according to the third embodiment of the present invention.
  • FIG. 18 is a diagram illustrating an example of the fifth selector.
  • Figure 19 is an example of the delay management table.
  • FIG. 20 is a block diagram of a CDMA receiver according to a fourth embodiment of the present invention.
  • FIG. 21 is a flowchart showing a process of assigning an interference cancellation stage to each channel based on received power.
  • FIG. 3 is a block diagram of a CDMA receiver according to the first embodiment of the present invention.
  • FIG. 3 shows only functions directly related to the present invention. Specifically, only the interference canceller 5 of the CDMA receiver shown in FIG. 1 is shown.
  • the interference canceller of this embodiment includes N interference replica generation units (IRUs) 21 1 to 21 1 -N, K interference replica subtraction units 22-:! to 22 2 K, and ⁇ Demodulators 23 1 to 23 3 are provided.
  • IRUs interference replica generation units
  • K interference replica subtraction units 22-:! to 22 2 K K interference replica subtraction units 22-:! to 22 2 K
  • ⁇ Demodulators 23 1 to 23 3 are provided.
  • ⁇ ⁇ That is, the number of interference replica generation units 21 is smaller than the number of demodulators 23.
  • ⁇ 3. That is, it is assumed that three interference replica subtraction units 22-1 to 22-3 are provided.
  • Each interference replica generation unit 21 is provided with a first selector 31, a second selector 32, a selector block 33, and a third selector 34.
  • the second selector 32 is not provided in the interference replica generation unit 21-1.
  • a control unit that controls the first selector 31, the second selector 32, the selector block 33, and the third selector 34 connected to the interference replica generation units 21-1 to 21- ⁇ , respectively. 4 1 is provided.
  • FIG. 4 is a configuration diagram of the interference replica generation unit 21.
  • a multipath environment is assumed, and it is assumed that each interference replica generation unit 21 has a RAKE reception function.
  • the interference replica generation unit 21 generates an interference replica and a new symbol replica of the channel using the interference residual signal and the symbol replica generated in the previous stage.
  • this interference replica generation unit operates as an interference replica generation unit provided in the first stage, a received signal is given instead of the interference residual signal, and “0 (zero)” is used as a symbol replica. Is given.
  • the received signal corresponds to the received signal r shown in FIG.
  • the given interference residual signal (or received signal) is despread by a despreader 501.
  • the spread code sequence assigned to the target channel is multiplied.
  • the adder 502 by adding the symbolic replica S to the output of the despreader 501 using the adder 502, a received symbol from which interference from paths other than the relevant path has been removed is obtained.
  • the channel estimation circuit 503 estimates the phase of the path based on the output of the adder 502, and outputs an estimated value of the phase and a complex conjugate of the estimated value of the phase.
  • the multiplier 504 multiplies the output of the adder 502 by the complex conjugate of the estimated value of the phase. As a result, the phase delay generated in the transmission path is compensated.
  • the despreader 501, the adder 502, the channel estimation circuit 503, and the multiplier 504 are provided for each path in the multipath environment (that is, for each finger). .
  • the received symbols, the phases of which have been compensated for each path, are added to each other by a rake combining unit 505, and then a data determination is performed by a determination unit 506.
  • a data judgment soft judgment (multi-value judgment) and hard judgment (binary judgment) are generally known.
  • Soft judgment multi-value judgment
  • hard judgment binary judgment
  • Multiplier 507 multiplies the judgment value output from judgment section 506 by the estimated phase value output from channel estimation circuit 503. As a result, the symbol in the state including the phase delay in the transmission path is reproduced. Then, the result of the multiplication is sent to the next stage as a symbol replica of the stage.
  • the subtractor 508 subtracts the symbol replica generated in the previous stage from the output of the multiplier 507. Then, the output of the subtractor 508 is spread again by the spreader 509. Note that the multiplier 507, the subtractor 508, and the spreading unit 509 are provided for each pass.
  • the combining section 5110 combines the signals spread by the spreader 509 for each path. Then, the output of the synthesizing unit 5110 is multiplied by the attenuation coefficient using the multiplier 511. The output of the multiplier 5 11 1 is sent to the interference replica attenuator 22 as an interference replica.
  • the attenuation coefficient is a weighting coefficient determined according to the reliability of the interference replica, and is effective in improving the interference removal characteristics. However, the use of the attenuation coefficient is not an essential requirement for practicing the present invention.
  • the interference replica generation unit 21 receives a received signal or a previous stage interference residual signal via the first selector 31 shown in FIG. In addition, it receives the symbol replica generated in the previous stage via the second selector. On the other hand, the interference replica generated by the interference replica generation unit 21 is sent to a predetermined interference replica subtraction unit 22 via a selector block 33. Further, the symbol replica generated by the interference replica generation unit 21 is sent to the corresponding demodulator 23 via the third selector 34 or to the interference replica generation unit of the next stage.
  • Each interference replica subtraction unit 22 is supplied with a received signal or an interference residual signal generated in the previous stage. Specifically, the received signal is given to the interference replica subtraction unit 22-1, and the interference replica subtraction units 22-2 and 22-3 are received. Each is provided with the interference residual signal generated in the previous stage. The received signal or the interference residual signal is sent to the subtracter after being delayed by the time required for the interference removal processing in the interference replica subtractor 22, respectively.
  • each interference replica subtraction unit 22 includes an interference replica generation unit 21 1 ::! 2 to 1 1 -N. Then, each interference replica subtracting section 22 performs a process of subtracting the synthesized interference replica from the received signal or the interference residual signal of the previous stage.
  • the outputs of the interference replica subtraction units 22-1, 22-2 are respectively sent to the interference replica subtraction unit of the next stage as interference residual signals, and the interference replica generation unit 22-2- :! It is also sent to ⁇ 22-N.
  • the output of the interference replica subtraction unit 22-3 is sent to each demodulator 23 _ :! ⁇ 23-M.
  • FIG. 5 is a configuration diagram of the demodulator 23.
  • the configuration of the demodulator 23 has many points in common with the configuration of the interference replica generation unit. That is, the demodulator 23 includes the despreading unit 501, the adder 502, the channel estimation circuit 503, the multiplier 504, the RAKE combining unit 505, and the decision unit shown in FIG. It consists of a part 506. Therefore, a detailed description of the demodulator 23 is omitted.
  • FIG. 6 is a diagram illustrating an example of the first selector 31.
  • One first selector 31 is provided on each input side of the interference replica generation unit 21-1-1-2_N.
  • the received signal is given to the # 0 input terminal.
  • the outputs of the corresponding interference replica subtraction units 22 are given to the # 1 input terminal to the # K-11 input terminal, respectively.
  • the output of the interference replica subtraction unit 22-1 is given to the # 1 input terminal
  • the output of the interference replica subtraction unit 22-2 is given to the # 2 input terminal.
  • the first selector 31 selects and outputs the signal of the input terminal indicated by the selector control information generated by the control unit 41.
  • the output of the first selector 31 is given to the corresponding interference replica generation unit 21.
  • FIG. 7 is a diagram showing an example of the second selector 32.
  • the second selector 32 is provided on each input side of the interference replica generation units 21-2 to 21-N.
  • "0 (zero)" is given to the # 0 input terminal.
  • the # 0 input terminal is, for example, grounded.
  • the # 1 input terminal is provided with the symbol replica generated by the interference replica generation unit 21 of the previous stage.
  • the second selector 32 selects and outputs the signal of the input terminal indicated by the selector control information generated by the control unit 41.
  • the output of the second selector 32 is provided to the corresponding interference replica generation unit 21.
  • FIG. 8 is a diagram illustrating an example of the selector block 33.
  • Selector block 3 3 is used for interference replica generation ut 2 1; ⁇ 2 1- N is provided for each output side.
  • the selector block 33 includes the same number of two-input selectors as the number of the interference replica subtractors 22. In this embodiment, three two-input selectors are provided.
  • each two-input selector is provided with the interference replica generated by the corresponding interference replica generation unit 21 and “0 (zero)”. Then, the selector block 33 determines an output according to the selector control information generated by the control unit 41.
  • the two-input selector specified by the selector control information selects the corresponding interference replica generated by the corresponding interference replica generation unit 21, and the other two-input selectors select “0”.
  • the interference replica generated by the interference replica generation unit 21 is sent to the interference replica subtraction unit 22 specified by the control unit 41, and “0” is sent to the other interference replica subtraction units 22. Will be done.
  • FIG. 9 is a diagram illustrating an example of the third selector 34.
  • the third selector 34 is provided for each of the output sides of the interference replica generation units 21-2 to 21-N. Provided. Here, "0 (zero)" is given to the # 0 input terminal. On the other hand, the symbol replica generated by the corresponding interference replica generation unit 21 is given to the # 1 input terminal. Then, the third selector 34 selects and outputs the signal of the input terminal indicated by the selector control information generated by the control unit 41. The output of the third selector 34 is sent to the corresponding demodulator 23.
  • the control unit 41 includes a user management table shown in FIG. 10 and a selector management table shown in FIG.
  • the user management table manages the number of stages of the interference replica generation unit 21 to be assigned for each user (that is, for each channel). In the example shown in FIG. 10, “3 stages”, “1 stage”, and “2 stages” are assigned to channels 1, 2, and 3, respectively. Note that the user management table may be fixedly set in advance, or may be dynamically updated according to a communication state or the like.
  • the selector management table shown in FIG. 11 includes a first selector 31, a second selector 32, a selector block 33, and a third selector provided for each interference replica generation unit 21. 3 Manages the selector control signal to be given to 4. The selector management table is automatically generated according to the user management table.
  • each interference replica generation unit 21 can operate as an interference replica generation unit provided for an arbitrary channel. It can operate as an interference replica generation unit installed at any stage.
  • the corresponding first selector 31 receives a signal. It is sufficient to select the signal r and generate control information such that the corresponding second selector 32 selects “0”.
  • the corresponding first selector 31 selects the interference residual signal of the first stage (interference replica signal).
  • Output of the power subtraction unit 2 2 — 1), and the corresponding second selector 3 2 generates control information that selects the symbol replica generated by the interference replica generation unit 2 1 _ ( ⁇ _1). Good.
  • the same channel is assigned to the interference replica generation units 2 1— (n) and 2 1 ⁇ 1 (n ⁇ 1), and the interference replica generation unit 2 1 ⁇ 1 (n ⁇ 1) is assigned to the first stage. It is assumed that it is operating as an interference replica generation unit. That is, when a plurality of interference stages are assigned to a certain channel (user), a plurality of interference replica generation units 21 adjacent to each other are assigned to the channel.
  • Each interference replica generation unit 21 generates an interference replica of the channel assigned to that unit. This interference replica is input to the corresponding selector block 33. Then, the selector block 33 determines the transfer destination of the interference replica according to the arrangement of the corresponding interference replica generation unit 21. For example, the selector block 33 provided for the interference replica generation unit 21 operating as the interference replica generation unit of the first stage converts the received interference replica into the interference replica subtraction unit 22 of the first stage. — Sends only 1 and sends “0” to other interference replica subtraction units. Note that the selector block 33 can also send “0” to all the interference replica subtraction units according to the control signal. By this means, when the reception quality of a certain channel does not satisfy the predetermined condition, it is possible to prohibit the interference removal processing for that channel.
  • the reception quality of each channel is, for example, It is determined based on the error rate after decoding the data.
  • the symbol replica generated by each interference replica generation unit 21 is sent to the second selector 32 of the interference replica generation unit of the next stage, and is also sent to the third selector 34 of the stage.
  • the corresponding third selector 34 converts the given symbol replica into a demodulator 23.
  • the corresponding third selector 34 sends “0” to the demodulator 23.
  • Each demodulator 23 is provided with an interference residual signal generated by the interference replica subtraction unit 22-1 to 22_3. Then, among the demodulators 23-1 to 23 -M, the demodulator to which a symbol replica is given from the interference replica generation unit 21 uses the symbol replica and the above-mentioned interference residual signal to demodulate data. Demodulate. On the other hand, a demodulator to which no symbol replica is given from the interference repliing force generation unit 21 is used to demodulate a channel that is not a target of interference cancellation.
  • interference cancellation processing is executed three times for channel 1 (user A) and only once for channel 2 (user B).
  • interference replica generation unit 2 1— :! 22 1-3 are assigned, and interference replica generation unit 21-4 is assigned to channel 2.
  • the spreading code sequence assigned to channel 1 is set in interference replica generation units 21-1 to 21-3, and interference replica generation unit 21-4 is set. It is assumed that the spreading code sequence assigned to channel 2 is set.
  • the interference components of the other channels have already been almost removed, and the interference removal accuracy of the channels is improved. Therefore, the interference of channel 2 is removed in the third stage. However, for some reason, it is possible to remove the interference of channel 2 only in the first or second stage. However, in this case, it is necessary to separately provide a circuit for delaying the symbol replica by a certain time in order to match the timing at which the symbol replica and the interference residual signal are received by the demodulator 23 with each other.
  • the operation of the interference canceller will be described assuming that the information shown in FIGS. 10 and 11 is set for channels 1 and 2.
  • the following control signals are given from the control unit 41 to each selector connected to the interference replica generation unit 21-1. That is, “0” is set for the first selector 31.
  • the received signal r is given to the interference replica generation unit 21-1 via the first selector 31.
  • “1” is set for the selector block 33.
  • the interference replica generated by the interference replica generation unit 21-1 is sent to the interference replica subtraction unit 22-1 via the selector block 33.
  • the selector block 33 sends “0” to the interference repli- cation subtraction units 22-2 and 22-3.
  • “0” is set for the third selector 34.
  • the symbol replica generated by the interference replica generation unit 21-1 is not transmitted to the demodulator 23-1 but is transmitted only to the interference replica generation unit 21-2.
  • the following control signal is given to each selector connected to the interference replica generation unit 21-2. That is, “1” for the first selector 3 1 Is set. Thereby, the interference residual signal generated by the interference replica subtractor 22-1 is given to the interference replica generation unit 21-2 via the first selector 31. Also, “1” is set to the second selector 32. As a result, the symbol replica generated by the interference replica generation unit 21-1 is provided to the interference replica generation unit 21-2 via the second selector 32. Further, “2” is set for the selector block 3 3. Thus, the interference replica generation force generated by the interference replica generation unit 21-2 is sent to the interference replica subtraction unit 22-2.
  • the selector block 33 sends “0” to the interference replica subtractors 2 2-1 and 2 2 _ 3. Further, “0” is set to the third selector 34. As a result, the symbol replica generated by the interference replica generation unit 21-2 is demodulated by the demodulator.
  • the following control signal is given to each selector connected to the interference replica generation unit 21-3. That is, “2” is set for the first selector 31. Thereby, the interference residual signal generated by the interference replica subtraction unit 22-2 is given to the interference replica generation unit 21-3 via the first selector 31. Also, “1” is set to the second selector 32. As a result, the symbol replica generated by the interference repli- cation force generation unit 21-12 is given to the interference replica generation unit 21-3 via the second selector 32. Further, “3” is set for the selector block 3 3. Thus, the interference replica generation force generated by the interference replica generation unit 21-3 is sent to the interference replica subtraction unit 22-3. At this time, the selector block
  • the received signal r is processed by the interference replica generation units 21-1 to 21-3 as follows. That is, given the received signal r, the interference replica generation unit 21-1 generates an interference replica of channel 1 and sends it to the interference replica subtraction unit 22-1, and also generates a symbol replica of the received signal. And sends it to the interference replica generation unit 21-2. At this time, the interference replica subtraction unit 22-1 generates a first residual signal by subtracting the interference replica generated by each interference replica generation unit 21 from the received signal r. In this embodiment, only the interference replica generated by the interference replica generation unit 21-1 is given to the interference replica subtraction unit 22-1.
  • the interference replica subtraction unit 22_1 subtracts the interference replica generated by the interference replica generation unit 21-1 from the received signal r.
  • the interference replica generation unit 2 1-2 receives the symbol replica from the interference replica generation unit 2 1-1, and receives the first residual signal from the interference replica subtraction unit 2 2-1. .
  • the interference replica generation unit 2 1-2 upon receiving the above two signals, the interference replica generation unit 2 1-2 generates an interference replica of channel 1 and sends it to the interference replica subtraction unit 2 2-2, and also generates a symbol replica of the received signal. And send it to the interference replica generation unit 21-13.
  • the interference replica subtraction unit 22-2 generates a second residual signal by subtracting the interference replica from the first residual signal generated by the interference replica subtraction unit 22-1.
  • the interference replica generation unit 21-3 receives the symbol replica from the interference replica generation unit 21-2, and receives the second residual signal from the interference replica subtraction unit 22-2.
  • interference replica generation units 21-3 receive these two signals. Then, an interference replica of channel 1 is generated and sent to the interference replica subtractor 22-3, and a symbol replica of the received signal is generated and sent to the demodulator 23-3. At this time, the interference replica subtraction unit 22-3 subtracts the interference replica generated by each interference replica generation unit 21 from the second residual signal generated by the interference replica subtraction unit 22-2. Generates a third residual signal. In this embodiment, the interference replica generated by the interference repli- cation force generation units 21-13 and 21-14 is given to the interference repli- cation force subtracting unit 22_3. Therefore, the interference replica subtraction unit 22-3 subtracts the interference replicas generated by the interference replica power generation units 21-3 and 21-4 from the second residual signal.
  • the third residual signal generated by the interference replica subtractor 23-3 is sent to the demodulator 23-3. Then, the demodulator 23-3 demodulates the signal of the channel 1 using the symbol replica generated by the interference replica power generation unit 21-13 and the third residual signal.
  • the interference replica generation units 21-1 to 21_3 operate as three serially connected interference replica generation units. Specifically, the interference replica generation units 21_1 to 21-3 operate as interference replica generation units of the first to third stages provided for removing the interference of channel 1, respectively. .
  • the following control signal is given to each selector connected to the interference replica generation unit 21-4. That is, “2” is set for the first selector 31. As a result, the interference residual signal generated by the interference replica subtractor 22-2 is supplied to the interference replica generation unit 21-4 via the first selector 31. Also, “0” is set to the second selector 32. As a result, “0” is given as a symbol replica to the interference replica generation units 21-4. Furthermore, “3” is set for selector block 3 3 Is done. Thus, the interference replica generated by the interference replica generation unit 21-4 is sent to the interference replica subtraction unit 22-3 via the selector block 33. At this time, the selector block 33 sends “0 J” to the interference replica subtraction units 22-1 and 22-2. Further, “1” is set to the third selector 34. As a result, the symbol replica generated by the interference replica generation unit 21-4 is sent to the demodulator 23-4.
  • the interference residual signal generated by the interference replica subtraction unit 22-2 according to the above sequence is processed by the interference replica generation unit 21_4 as follows. That is, given the interference residual signal, the interference replica generation unit 21-4 generates an interference replica of channel 2 and sends it to the interference replica subtraction unit 222, and also generates a symbol replica of the received signal. And sends it to demodulation section 23-4. At this time, the interference replica subtraction unit 22-3 subtracts the interference replica generated by each interference replica generation unit 21 from the second residual signal generated by the interference replica subtraction unit 22-2. Generates a third residual signal. In this embodiment, the interference replica subtraction units 22-3 are provided with the interference replicas generated by the interference replica generation units 21-3 and 21_4.
  • the interference replica subtracting unit 22-3 subtracts the interference replica generation power generated by the interference replica generation units 21-3 and 21-4 from the second residual signal.
  • the third residual signal generated by the interference replica subtractor 23-3 is sent to the demodulator 23-4.
  • the demodulator 23-4 demodulates the channel 2 signal using the symbol replica generated by the interference replica generation unit 21-4 and the third residual signal. That is, the interference replica generation unit 21-4 operates as a third stage interference replica generation unit provided for removing the interference of the channel 2.
  • the interference canceller according to the present embodiment is not multiplexed in the received signal. It is not necessary to cancel interference for all channels.
  • demodulators other than the demodulators 23-3 and 23-4 are used for demodulating signals of other channels. That is, the demodulators 23-1, 23-2, 23-5 to 23_M are used, for example, to demodulate a signal of a channel on which interference cancellation is not performed.
  • the selector management table includes a plurality of registers corresponding to interference replica generation units 21-1 to 21-N. Then, each register of this table is assigned to a predetermined channel determined based on the user management table. Specifically, when one or more interference replica generation units are allocated to a certain channel, the same number of registers as the interference replica generation unit are allocated to the channel.
  • “0” is set as “control information of the second selector 32”.
  • “1” is set as “control information of the third selector 34”.
  • FIG. 11
  • FIG. 13 is a block diagram of a CDMA receiver according to a second embodiment of the present invention. The symbols used in FIG. 3 among the symbols used in FIG. 13 indicate the same components.
  • the basic configuration of the interference canceller provided in the CDMA receiving apparatus of the second embodiment is the same as that of the first embodiment.
  • the interference canceller of the second embodiment is provided on the input side of each demodulator 23 in order to cope with the case where the number of interference replica generation units 21 is larger than the number of demodulators 23.
  • a fourth selector 35 is provided for each.
  • FIG. 14 is a diagram illustrating an example of the fourth selector 35.
  • the fourth selector 35 is basically a demodulator 23-:! One is provided for each input side of ⁇ 23-M. However, it is not always necessary to provide the fourth selector 35 for every demodulator 23, and when the upper limit of the number of channels from which interference should be removed using this interference canceller is predetermined. The fourth selector 35 may be provided for the same number of demodulators 23 as the upper limit.
  • the # 0 input terminal of the fourth selector 35 receives the output of the third selector 34 provided for the interference replica generation units 21_1 to 211-1N, respectively. Each third selector 34 outputs a symbol replica or “0” of the corresponding channel. Then, the fourth selector 35 selects and outputs the signal of the input terminal indicated by the selector control information generated by the control unit 41. The output of the fourth selector 35 is provided to the corresponding demodulator 23.
  • Figure 15 shows an example of the demodulator management table.
  • the demodulator management table manages control signals supplied to each fourth selector 35. That is, this table stores information indicating an input terminal to be selected by the fourth selector 35 provided in each demodulator 23.
  • demodulator 2 The fourth selector 35 provided in 3-1 selects the signal given to the # 3 input terminal, and the fourth selector 35 provided in the demodulator 23-2 is # 4 Select the signal given to the input terminal.
  • the demodulators 23-1 to 23-C demodulate the signals of those channels. Is also good. That is, the demodulators 23 having the smaller identification numbers may be sequentially allocated to the respective channels.
  • the fourth selectors 35 provided in the demodulators 23-(C + 1) to 23-M each select “0”. However, in FIG. 13, the fourth selector 35 provided in the demodulators 23-(C + 1) to 23 -M is omitted.
  • interference replica generation units 21-1 to 21-3 are assigned to channel 1 (user A), and interference replica generation units 21-4 are assigned to channel 2 (user B). Is assigned. Further, it is assumed that the first selector 31, the second selector 32, the selector block 33, and the third selector 34 are controlled in the same manner as in the example shown in FIG. Further, it is assumed that control information for controlling the fourth selector 35 is in a state shown in FIG.
  • each third selector 34 is sent to each fourth selector 35.
  • the third selectors 34 provided in the interference replica generation units 21-1 and 21-2 each output "0".
  • the third selector 34 provided in the interference replica generation unit 21-3 outputs the symbol replica of channel 1, and the third selector 34 provided in the interference replica generation unit 21-4.
  • the selector 34 outputs a symbol replica of channel 2. Therefore, demodulation Table 2 3— :!
  • Each of the fourth selectors 35 provided in ⁇ 2 3-3 is provided with “0” to the # 1 input terminal and the # 2 input terminal, and the symbol replica of the channel 1 is provided to the # 3 input terminal.
  • the symbol replica of channel 2 is supplied to the # 4 input terminal.
  • FIG. 17 is a block diagram of a CDMA receiver according to the third embodiment of the present invention.
  • the reference numerals used in FIG. 3 among the reference numerals used in FIG. 17 indicate the same parts.
  • each interference replica subtraction unit 22 includes a fifth selector 36. Note that as a more realistic configuration, it is not necessary to provide the fifth selector 36 for all the interference replica subtractors 22-1 to 22-3, for example, the first stage or the final stage. The interference replica subtracting section of the stage may not be provided. In the example shown in FIG. 17, the fifth stage selector 36 is not provided in the first stage replied force subtraction unit 22-1.
  • FIG. 18 is a diagram illustrating an example of the fifth selector 36.
  • the output of the delay circuit of the interference replica subtractor 22 is given to the # 0 input terminal of the fifth selector 36.
  • the output of the interference replica subtraction unit 22 of the previous stage is given to the # 1 input terminal.
  • the output of the fifth selector 36 is supplied to a subtractor (a subtracter for subtracting a symbol replica from an interference residual signal) of the interference replica subtraction unit 22. That is, the fifth selector 36 determines whether to delay the received signal r or the interference residual signal generated in the previous stage. Note that the fifth selector 36 is controlled by the control unit 41.
  • Figure 19 is an example of the delay management table.
  • the delay management table manages a control signal given to each fifth selector 36. That is, this table stores information indicating an input terminal to be selected by the fifth selector 36 provided in each interference replica subtraction unit 22.
  • the fifth selector 36 provided in the interference replica subtraction unit 22-2 selects the output of the delay circuit. In this case, the signal is delayed by the delay.
  • the fifth selector 36 provided in the interference replica subtraction section 22-3 selects the interference residual signal generated by the interference replica subtraction section of the previous stage. In this case, this signal is sent to the subtractor without delay.
  • the delay circuit table is generated, for example, as follows. First, “control information of selector block 33” in the selector management table shown in FIG. 11 is referred to.
  • the “control information of the selector block 33” represents the interference replica subtraction unit 22 to which the interference replica is to be transferred. Therefore, by referring to the “control information of selector block 33”, an interference replica subtraction unit that does not receive an interference replica from any interference replica generation unit 21 2 2 can be detected.
  • “1” is set for the interference replica subtraction unit 22 that does not receive the interference replica, and for the interference replica subtraction unit 22 that receives one or more interference replicas. “0” is set.
  • the maximum value of the number of interference cancellation stages assigned to each channel is “2”, and it is assumed that none of the channels uses the third stage. I do.
  • the control unit 41 gives “1” to the fifth selector 36 provided in the interference replica subtraction unit 22-3.
  • the interference residual signal generated by the interference replica subtraction unit 22-2 is provided to the subtractor of the interference replica subtraction unit 22-3 without being delayed.
  • each interference replica generation unit 2 1— :! to 2 1—N transfers “0” as an interference replica to the interference replica subtraction unit 22-3.
  • the interference replica subtraction unit 22-3 subtracts “0” from the interference residual signal and sends the subtraction result to each demodulator 23.
  • the interference residual signal generated by the interference replica subtractor 2 2-2 is not delayed, and the demodulators 2 3-1 to 2-3 are not delayed and the interference removal processing is not substantially performed.
  • FIG. 20 is a block diagram of a CDMA receiver according to a fourth embodiment of the present invention.
  • the basic configuration of the interference canceller provided in the CDMA receiver of the fourth embodiment is the same as that of the first or third embodiment. However, the interference canceller of the fourth embodiment is based on the characteristics of the signal of each channel multiplexed in the received signal. Function to automatically change the allocation method of the interference replica generation unit 21.
  • a reception power detection unit 51 is provided, and the user management table shown in FIG. 10 is updated based on the reception power of the signal of each channel. Then, with the updating of the user management template, the selector management table shown in FIG. 11 is updated, whereby the assignment of the interference replica generation unit 21 is changed.
  • the method of detecting the power of the signal transmitted via each channel is an existing technology and will not be described in detail.For example, for each channel, the I component and the Q component of the signal are squared and added. It is calculated by:
  • the control unit 41 determines the number of interference cancellation stages to be assigned to each channel based on the power of each channel detected by the reception power detection unit 51. Specifically, for example, many interference cancellation stages are assigned to a channel having a large received power.
  • FIG. 21 is a flowchart illustrating a process of assigning an interference cancellation stage to each channel based on received power.
  • N represents the number of interference replica generation units
  • k represents the number of interference replica subtraction units 22
  • L represents the number of communicating channels.
  • I is a number for identifying a channel.
  • step S2 the processing after step S2 is executed for each channel.
  • step S2 it is checked whether or not the interference repliing power generation unit 21 that can be assigned to the channel i remains.
  • step S3 it is checked whether or not the processing in step S4 and subsequent steps has been executed for all the channels being communicated. And an interference replica that can be assigned to channel i. If the force generation unit 21 remains and a channel for which the processing of step S4 and subsequent steps has not been executed remains, the process proceeds to step S4.
  • steps S4 to S6 the received power of channel i is compared with a plurality of preset thresholds, and the corresponding step in steps S7 to S9 is executed based on the comparison result. .
  • the received power (received power S (i)) of the channel i is larger than the threshold value T (k)
  • k interference replica generation units 21 are allocated to the channel in step S7.
  • the threshold T (] £ -1) and the receiving power 3 (1) ⁇ the threshold ([£)) in step S8, (k-1) interferences on the channel Replica generation unit 21 is assigned.
  • the number of interference replica generation units 21 according to the received power is allocated to the corresponding channel.
  • interference replica generation unit 21 is not assigned to that channel.
  • step SI1 the "total number of interference replica generation units 21 already allocated (Total)" is updated. Thereafter, the process returns to step S2 and the same processing is repeated for the next channel.
  • step S12 If there is no interference repliing force generation unit 21 to be assigned to channel i (step S2: No), in step S12, the channel immediately before (channel (i-1)) After adjusting the number of allocated interference replica generation units 21, the process ends. Specifically, the number of interference replica generation units 21 assigned to the immediately preceding channel is reduced by “Total-N”. On the other hand, if the above-mentioned assignment processing has been executed for all the channels being communicated (step S3: No), the processing is terminated.
  • the interference level to be assigned to each channel by the processing of the above flowchart When the number of the precursor generation units 21 is determined, the result is written in the user management table shown in FIG. Subsequently, a selector management table shown in FIG. 11 is generated based on the contents of the user management table. Each selector is controlled according to the selector management table. As a result, the resources of the interference canceller are appropriately allocated to the channels according to the received power of the signals transmitted via the channels.
  • reception power is used as one of the characteristics of the signal of each channel multiplexed in the reception signal, but the present invention is not limited to this. That is, instead of the received power, for example, an interference replica generation unit to be assigned to each channel using “SIR: signal power to interference power ratio” or “communication speed (eg, symbol rate)” Determine the number of 2 1
  • SIR signal power to interference power ratio
  • communication speed eg, symbol rate
  • a known technique is used to detect SIR for each channel.
  • many interference replica generation units 21 are assigned to a channel having a high communication speed.
  • a signal having a high communication speed generally has a large power. Therefore, if more interference replica generation units 21 are allocated to a channel having a high communication speed, the efficiency of interference cancellation is increased, and the capacity of the communication system is likewise improved.
  • the method of detecting the communication speed for each channel is, for example, In a system in which the information to be indicated is notified from the transmitting device to the receiving device or a system in which the network notifies the receiving device, the notification may be used.
  • the flowchart shown in FIG. 21 can be used as it is by appropriately setting the threshold value.
  • FIGS. 3 to 21 is based on the assumption that a CDMA receiving apparatus receives a code multiplexed signal in a CDMA communication system, but the present invention is not limited to this. Absent.
  • the number of interference cancellation stages to be assigned to each channel can be flexibly changed. Therefore, good interference cancellation characteristics can be realized while effectively using the resources of the interference canceller.

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Abstract

L'invention concerne un éliminateur d'interférences comprenant des unités de génération de répliques d'interférence (21-1 à 21-N). Une ou plusieurs unités de génération de répliques d'interférence sont attribuées à chaque canal de communication AMCR. Un canal auquel une unité de génération de répliques d'interférence est attribuée effectue une opération d'élimination des interférences. Un canal auquel plusieurs unités de génération de répliques d'interférence sont attribuées répète une opération d'élimination des interférences.
PCT/JP2000/004757 2000-07-14 2000-07-14 Recepteur amcr WO2002007358A1 (fr)

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PCT/JP2000/004757 WO2002007358A1 (fr) 2000-07-14 2000-07-14 Recepteur amcr

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PCT/JP2000/004757 WO2002007358A1 (fr) 2000-07-14 2000-07-14 Recepteur amcr

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WO2002007358A1 true WO2002007358A1 (fr) 2002-01-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103092817A (zh) * 2013-01-18 2013-05-08 五八同城信息技术有限公司 一种基于脚本引擎的数据采集方法和装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0923199A2 (fr) * 1997-12-05 1999-06-16 Fujitsu Limited Annuleur d'interférence en CDMA
JPH11251959A (ja) * 1998-03-05 1999-09-17 Fujitsu Ltd 干渉キャンセラ装置及び無線通信装置
EP0954112A2 (fr) * 1998-05-01 1999-11-03 Nec Corporation Appareil récepteur AMDC à utilisateurs multiples comprenant annuleur d'interférence avec état de réception optimal
EP0967734A2 (fr) * 1998-06-25 1999-12-29 Nec Corporation Annuleur d'interférence pour des utilisateurs multiples pour un système de AMRC à séquence directe
JP2000138605A (ja) * 1998-10-30 2000-05-16 Nec Corp マルチユーザ受信装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0923199A2 (fr) * 1997-12-05 1999-06-16 Fujitsu Limited Annuleur d'interférence en CDMA
JPH11251959A (ja) * 1998-03-05 1999-09-17 Fujitsu Ltd 干渉キャンセラ装置及び無線通信装置
EP0954112A2 (fr) * 1998-05-01 1999-11-03 Nec Corporation Appareil récepteur AMDC à utilisateurs multiples comprenant annuleur d'interférence avec état de réception optimal
EP0967734A2 (fr) * 1998-06-25 1999-12-29 Nec Corporation Annuleur d'interférence pour des utilisateurs multiples pour un système de AMRC à séquence directe
JP2000138605A (ja) * 1998-10-30 2000-05-16 Nec Corp マルチユーザ受信装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103092817A (zh) * 2013-01-18 2013-05-08 五八同城信息技术有限公司 一种基于脚本引擎的数据采集方法和装置

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