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WO2002007198A3 - Deposition of low stress tantalum films - Google Patents

Deposition of low stress tantalum films Download PDF

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Publication number
WO2002007198A3
WO2002007198A3 PCT/US2001/022062 US0122062W WO0207198A3 WO 2002007198 A3 WO2002007198 A3 WO 2002007198A3 US 0122062 W US0122062 W US 0122062W WO 0207198 A3 WO0207198 A3 WO 0207198A3
Authority
WO
WIPO (PCT)
Prior art keywords
deposition
films
low stress
substrate
deposited
Prior art date
Application number
PCT/US2001/022062
Other languages
French (fr)
Other versions
WO2002007198A2 (en
Inventor
Arvind Sundarrajan
Tony P Chiang
Tse-Yong Yao
Peijun Ding
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2002007198A2 publication Critical patent/WO2002007198A2/en
Publication of WO2002007198A3 publication Critical patent/WO2002007198A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In order to deposit tantalum-containing barrier layer films for copper, the barrier layers are deposited in a high density plasma sputtering chamber. High aspect ratio openings can be filled using such a chamber, but the substrate temperature becomes elevated to temperatures that compressively stress the barrier films. Thus the films are deposited at reduced temperatures by clamping the substrate to a temperature controllable substrate support during the deposition.
PCT/US2001/022062 2000-07-18 2001-07-13 Deposition of low stress tantalum films WO2002007198A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61836400A 2000-07-18 2000-07-18
US09/618,364 2000-07-18

Publications (2)

Publication Number Publication Date
WO2002007198A2 WO2002007198A2 (en) 2002-01-24
WO2002007198A3 true WO2002007198A3 (en) 2002-07-18

Family

ID=24477393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022062 WO2002007198A2 (en) 2000-07-18 2001-07-13 Deposition of low stress tantalum films

Country Status (1)

Country Link
WO (1) WO2002007198A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041598A1 (en) * 1996-04-26 1997-11-06 Sony Corporation Apparatus and method for improved deposition of conformal liner films and plugs in high aspect ratio contacts
EP0840360A2 (en) * 1996-11-05 1998-05-06 Applied Materials, Inc. Wafer support with improved temperature control
WO1998054377A2 (en) * 1997-05-27 1998-12-03 Applied Materials, Inc. Stress tuned tantalum and tantalum nitride films
EP0939437A2 (en) * 1998-02-27 1999-09-01 Nec Corporation Planarization of wiring layers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041598A1 (en) * 1996-04-26 1997-11-06 Sony Corporation Apparatus and method for improved deposition of conformal liner films and plugs in high aspect ratio contacts
EP0840360A2 (en) * 1996-11-05 1998-05-06 Applied Materials, Inc. Wafer support with improved temperature control
WO1998054377A2 (en) * 1997-05-27 1998-12-03 Applied Materials, Inc. Stress tuned tantalum and tantalum nitride films
EP0939437A2 (en) * 1998-02-27 1999-09-01 Nec Corporation Planarization of wiring layers

Also Published As

Publication number Publication date
WO2002007198A2 (en) 2002-01-24

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