WO2002003551A2

WO2002003551A2 - Digital delay element

Info

Publication number: WO2002003551A2
Application number: PCT/CA2001/000948
Authority: WO
Inventors: Paul Demone
Original assignee: Mosaid Technologies Incorporated
Priority date: 2000-06-30
Filing date: 2001-06-29
Publication date: 2002-01-10
Also published as: KR20030028496A; WO2002003551A3; CA2313286A1; AU2001267245A1

Abstract

A delay circuit for delaying propagation of a signal between an input node and an output node, the circuit consisting a delay node coupled to receive the signal at the input node; a first transistor coupled between the delay node and an intermediate node; a second transistor coupled between the intermediate node and a supply voltage and having its gate node coupled to the intermediate node, the first and second transistors operate to delay the signal being propagated from the input node to the output node whereby the transistors compensate for processing variation on propagation delay.

Description

DIGITAL DELAY ELEMENT The present invention relates to the field of digital delay elements, and more particularly to a process independent digital delay element.

BACKGROUND OF THE INVENTION

Self-timed circuit design techniques are used extensively in high-speed circuits and electronic memories for performing a sequential series of operations. The operations require certain timing constraints in the absence of sufficient or appropriate conventional timing reference sources, such as clock or strobe signals. Self-timed circuits rely on a set of serially connected digital delay elements to derive, relative to an initial reference pulse or edge, all the necessary timing reference signals to perform a discrete series of sequential operations on data. These operations include capture of data in a latch or flip-flop, precharging or equalization of signals, evaluation of dynamic logic stage(s), and the transitioning of tri-state driver(s) into or out of a high- impedance state.

Referring to Figure 1, a general form of a self-timed circuit is illustrated. The self-timed circuit consists of two parallel paths. A first path is comprised of a set of logic stages and memory elements through which data signals progress in discrete propagation delay steps F_n. A second path consists of a chain of delay elements D_n. Each delay element D_n is designed to have a worst case input to output propagation delay that is greater than or equal to the worst case propagation delay of its associated data function step F_n under all conditions. This ensures that the outputs of data stage F_n are all stable by the time the memory or dynamic logic elements separating F_n and F_n+1 are activated by the output of delay element D_n.

The functional steps F_n that are generally composed exclusively of low fanout sub- micron gate length MOS combinational logic gates with localized interconnect are referred to as "transistor-dominated". For transistor-dominated functional steps F_n, the ratio of maximum to minimum propagation delay can be 2:1 or higher over a typical range of temperature, supply voltage and process variation. If the data path of a self-timed circuit consisted entirely of transistor-dominated function steps F_n then the associated delay elements D_n could be constructed of an appropriately long series of logic gates, such as inverters or two-input NAND gates. The propagation delays in the two parallel paths of the self-timed circuit could also be arranged to closely track each other over temperature, supply voltage, and processing variation. The closer the timing of the paths' track the less timing margin overhead must be built into a self-timed circuit to ensure correct operation. Reducing the timing margin allows the self-timed circuit to operate closer to the theoretical peak data throughput rate defined by the worst case timing of the functional steps F_n.

However in the case of memory arrays, data buses and other large scale physical circuit elements, a significant portion of the propagation delay of at least some of the functional steps F_n step can be dominated by distributed resistive and capacitive (RC) delays. The variation in RC delays usually has very little correlation with the delays in transistor-dominated logic. This requires an excessive amount of timing margin be reserved when a transistor-dominated delay element F_n is teamed with an RC- dominated function step D_n.

An RC-dominated delay element D_n that tracked variation in a RC dominated function step Fn would be ideal. This is usually impractical because the RC delay is a parasitic effect on large circuit elements and the delay elements would have to be physically large to achieve the same effect. A less efficient but much more practical approach to this problem is to create a compact delay element D_n whose propagation delay varies less with temperature, supply voltage and processing than transistor-dominated logic. Such an element would permit self-timed circuits with RC-dominated function steps to operate more efficiently and closer to its theoretical peak throughput.

hi the past, transistor-processing insensitive delay elements could be constructed by combining discrete resistive and capacitive circuit elements available in an integrated circuit. However, this approach has two basic drawbacks. First, it consumes a large chip area, and second, the variability of the RC characteristic delay may be as poor as that of transistor-dominated logic. Further, acceptably compact realizations of RC delay elements do not necessarily track the delay characteristics of the large scale physical elements such as long word lines or data buses found in RC-dominated function steps that may be found in self-timed circuits. Yet further, RC-based delay elements have poor process portability and scaling characteristics in deep sub-micron digital CMOS processes.

There are more advanced methods of obtaining low variability delay elements within an integrated circuit. These include active circuit techniques such as compensating delay elements by slaving them to delay-locked loops (DLLs) references using bias voltages or currents. Unfortunately such active circuit approaches consumes a great deal of chip area and power, are complex to design, prone to failure, and achieve a degree of timing precision unnecessary for most self-timed circuits.

Circuit elements that can be adjusted after manufacturing through techniques such as laser trimming of resistive elements can also provide high precision delay elements. But approaches like these add extra, potentially costly, manufacturing steps. They also require the presence of externally measurable reference delays to control the trimming process.

Therefore, an all-MOSFET solution is desirable for enhanced portability and compatibility with future processes with smaller feature sizes. It is an object of the present invention to obviate or mitigate at least some of the above mentioned disadvantages.

SUMMARY OF THE INVENTION hi accordance with the present invention there is provided a delay circuit for delaying propagation of a signal between an input node and an output node, the circuit comprising: (a) a driving circuit coupled to the input node for receiving the signal and driving an output current proportional to the input signal; (b) a load circuit receiving the output current and coupled to the output node for driving the output node with a delayed input signal; and

(c) a delay element coupled between the driving circuit and the load element, for generating a delay of the input signal which is proportion to the output current.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the present invention will now be described by way of example only with reference to the following drawings in which:

Figure 1 is a block diagram of a general self-timed circuit (prior art); Figure 2 is a schematic diagram a MOSFET circuit stage according to an embodiment of the present invention; Figure 3(a) is a schematic diagram of the MOSFET circuit stage illustrated in

Figure 2 for transistors having a strong drive; Figure 3(b) is a schematic diagram of the MOSFET circuit stage illustrated in Figure 2 for transistors having a weak drive;

Figure 4 is a schematic diagram of a process variation compensation capacitor; and Figures 5(a) and (b) show a circuit and graph illustrating the combined effect of physical variations for the circuit shown in Figure 4 over temperature and voltage variations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT h the following description like numerals refer to like structures in the drawings.

Referring to Figure 2, a MOSFET circuit stage according to an embodiment of the present invention is shown generally by numeral 200. The MOSFET circuit stage comprises a driving circuit element 202 that drives a driven circuit element 204. The delay of the MOSFET circuit stage 200, to a first approximation, is directly proportional to the output current of the driving circuit element 202 (having either an n- channel FET pull-down or an p-channel FET pull-up) and inversely proportional to the input capacitance of the driven circuit element 204. Conceptually the variation of this delay could be reduced by deliberately introducing a capacitive element between the circuit elements 202 and 204. The capacitance of the capacitive element varies with temperature, supply voltage, proportionally to the output current of the driving circuit element which varies over the same conditions. That is, this compensation capacitance Ccomp has a large value when transistors have strong drive (high output current) and a low value -when transistors have weak drive (low output current), as shown schematically in Figures 3(a) and 3(b) respectively. If the value of the compensation capacitance is increased, the overall circuit delay increases too but its relative variability is reduced.

Referring now to Figure 4, there is shown a compensation capacitor circuit 400 constructed from two n-channel FETs Ni and N . This compensation capacitor 400 is subject to process variation while still having sufficient useful quality. Transistor Ni acts as a resistive element while N₂ is configured to act as a MOS capacitor. The circuit is designed to make the propagation delay for a logic '0' to '1' input transitions much less sensitive to process variation than conventional MOS logic elements. The effective capacitance of the Nι/N₂ element tends to vary inversely with MOSFET drive strength through the combination of three different physical effects.

The first effect is threshold voltage variation. The input capacitance of an n-channel MOS capacitor is many times lower in the sub-threshold region (Vgs < Vt) than in the inversion region (Vgs > Vt). When FET drive is at a peak drive, a Vdd supply voltage is at its maximum and the threshold voltages are at a minimum. This means that a rising transition on Vc2 sees the higher capacitance of the inversion region for a much larger fraction of the transition than when FET drive is at a minimum (i.e. minimum Vdd, maximum Vt). The FET drive is simply the maximum current an n-channel FET can sink to Vss and a p-channel FET can source from Vss. It is influenced by three basic factors: power supply voltage (Vdd), device operating temperature, and device to device variation (i.e. processing spread). The processing spread is attributable to three main factors, which in usual order of importance are: transistor gate length variation, gate oxide thickness variation, and threshold voltage variation. Also, the worst case transistor drive occurs in a slow process and Vdd is minimum and the best-case transistor drive occurs in a fast process and Vdd is maximum. These are the two process and voltage corner cases that define the minimum and maximum delay of a circuit element. For clarity, the terms "fast process" and "slow process" as used in the present description are a subset of what is more generally referred to as "fast operating conditions" or "slow operating conditions". In the present context a device operating under "fast operating conditions" is a device having a combination of: -a fast process (i.e. minimum gate length device, uniform gate oxides etc. in general, optimal process steps with minimum process variations), maximum operating voltage and minimum operating temperature. On the other hand, for "slow conditions" we refer to a device having a combination of a slow Process (i.e. large gate lengths, non-uniform oxide thickenesses etc. in general, non-optimal processing steps with lots of unintentional variations), minimum operating voltage and maximum temperature.

The second effect is the threshold voltage drop across NI. When the FET drive is high, Vdd is at its maximum value and the voltage swing reduction from the body-effect enhanced threshold voltage drop from Vcl to Vc2 is relatively smaller than when Vdd is at its minimum value and the FET device is operating in a slow process. This effect reduces the effective input capacitance of N1/N2 for low Vdd and a slow process. Here again this refers to the best and worst case process and supply voltage conditions for minimum and maximum delay. The minimum delay condition occurs for fast process and maximum Vdd. i the fast process gate lengths are shortest, gate oxide is thinnest, and threshold voltage Vt is minimum. When this occurs the Vt drop from Vcl to Vc2 is both smaller in absolute terms and smaller as fraction of the full Vdd swing than for the slowest delay case (which occurs when Vdd is minimum and process is slow, i.e. Vt maximum). The net effect is that the capacitor has the highest effective capacitance for the fastest delay case (which moderates it to a slower delay value) and the lowest effective capacitance for the slowest delay case (which moderates it to a faster delay value). The third effect is the reduction of dynamic input capacitance for rising transitions on Vcl due to the effective RC delay induced by the on-resistance of NI when circuit elements are correctly sized. When FET strength is high this RC delay is minimal and most of the input capacitance of N2 is seen during the rising transition of Vcl. When FET strength is low this RC delay is more significant and the time lag between the voltage on Vc2 relative to Vcl means that the input transition can be recognized by inverter 13 before N2 has been completely charged. Although the capacitance is not lowered by this time lag, part of the capacitance of N2 is effectively nullified in terms of affecting the delay between the rising transition on Vcl and the fall of the output of inverter 13. hi other words, the RC delay refers to the ON-resistance of transistor NI and the input capacitance of the MOS capacitor N2. When the FET drive is strong, the RC delay is small, and when FET drive is weak, the RC delay is large.

The combined effect of these three physical mechanisms on the input capacitance of the indicated N₁/N₂ structure for a rising transition on V_cl under worst case and best case process, voltage, and temperature variations are shown in Fig 5. The Nι/N₂ FETs are manufactured in a typical 0.25 μm bulk single poly CMOS process. The ratio of worst case to best case propagation delay for rising input transitions in a high output drive circuit embodiment of this invention is about 1.4 to 1 as compared to a ratio in excess of 2 to 1 for conventional transistor-dominated logic gates.

The circuit shown in Figure 4 is designed to make the propagation delay for a logic '0' to ' 1 ' input transitions much less sensitive to process variation than conventional MOS logic elements. This embodiment of the invention can be adopted to compensate falling edge delays instead by either eliminating inverters I_\ and I , or replacing N1/N2 with an equivalent p-channel dual FET structure P₁/P₂ with P₂ acting as a MOS capacitor to Vdd-

Delay elements compensated for both rising and falling transitions can be realized by either concatenating two compensation capacitance stages with a logical inversion between them, or combining both n-channel and p-channel embodiments of the invention in a single delay stage.

Through careful circuit design the invention can be used to nearly perfectly compensate for the effect of FET processing variation on propagation delay. The delay circuit will still be susceptible to delay variation induced by changes to device temperature or supply voltage. This circuit could be used as a temperature-to-delay transducer if the supply voltage is stabilized using active circuit elements controlled by a high precision reference circuit such as a bandgap voltage reference. Multiple instances of this circuit could also be arranged in a ring oscillator topology to create a temperature-to-frequency transducer. In such a role the circuit delay/output frequency would vary over a 1.2:1 range or better for temperature variations from 0 to 100 degrees C.

The terms and expressions which have been employed in the specification are used as terms of description and not of limitations, there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described or portions "thereof, but it is recognized that various modifications are possible within the scope of the claims to the invention.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A delay circuit for delaying propagation of a signal between an input node and an output node, said element comprising:

(a) a driving circuit coupled to said input node for receiving said signal and driving an output current proportional to said input signal;

(b) a load circuit receiving said output current and coupled to said output node for driving said output node with a delayed input signal; and (c) a delay element coupled between said driving circuit and said load element, for generating a delay of said input signal which is proportion to said output current.

2. A delay circuit as defined in claim 1, said delay element being a resistive-capacitive delay element.

3. A delay circuit as defined in claim 1, said delay element comprised only of transistors.

4. A delay circuit as defined in claim 3, said delay element comprising a first and second transistor configured as a resistive element and a capacitive element respectively.

5. A delay circuit as defined in claim 4, said transistors being n-channel FET's.

6. A delay circuit for delaying propagation of a signal between an input node and an output node, said element comprising:

(a) a delay node coupled to receive said signal at said input node;

(b) a first transistor coupled between the delay node and an intermediate node;

(c) a second transistor coupled between said intermediate node and a supply voltage and having its gate node coupled to the intermediate node, whereby said first and second transistors operate to delay said signal being propagated from said input node to said output node.

7. A delay circuit as defined in claim 4, said first and second transistors being n- channel FETS.