WO2002001619A1 - Procede de gravure - Google Patents
Procede de gravure Download PDFInfo
- Publication number
- WO2002001619A1 WO2002001619A1 PCT/JP2001/005442 JP0105442W WO0201619A1 WO 2002001619 A1 WO2002001619 A1 WO 2002001619A1 JP 0105442 W JP0105442 W JP 0105442W WO 0201619 A1 WO0201619 A1 WO 0201619A1
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- WIPO (PCT)
- Prior art keywords
- etching
- process gas
- layer
- film
- organic
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 112
- 238000005530 etching Methods 0.000 title claims abstract description 70
- 239000007789 gas Substances 0.000 claims abstract description 97
- 230000008569 process Effects 0.000 claims abstract description 79
- 230000009977 dual effect Effects 0.000 claims abstract description 19
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 239000000203 mixture Substances 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- -1 silicon oxide nitride Chemical class 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 150000003377 silicon compounds Chemical class 0.000 claims 2
- 230000001681 protective effect Effects 0.000 abstract description 17
- 239000010410 layer Substances 0.000 description 64
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000012545 processing Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229920000642 polymer Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920006254 polymer film Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- GZVOTYAHILEUEN-UHFFFAOYSA-N C1CC=2C1=CC=CC2.C2(C=CC(N2)=O)=O Chemical compound C1CC=2C1=CC=CC2.C2(C=CC(N2)=O)=O GZVOTYAHILEUEN-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 150000008378 aryl ethers Chemical class 0.000 description 1
- 239000010426 asphalt Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000002790 naphthalenes Chemical class 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001420 photoelectron spectroscopy Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Definitions
- the present invention relates to an etching method.
- a so-called damascene structure is used, in which wiring is buried using metal CMP technology. Furthermore, recently, trench wiring connecting each element developed in the horizontal direction and each element developed in the vertical direction have been developed. Semiconductor devices with a so-called dual damascene structure, which simultaneously creates via wiring to connect devices, have become widespread.
- a via is further formed in a trench formed in an interlayer insulating film composed of an organic ow K film, a junction between the trench and the via (a via edge portion) is formed. Shoulder loss, a so-called shoulder drop, is likely to occur.
- the present invention has been made in view of the above-described problems in forming a conventional dual damascene structure, and is intended for a case where a via is further formed in a trench formed in an interlayer insulating film composed of an organic Low K film.
- a via is further formed in a trench formed in an interlayer insulating film composed of an organic Low K film.
- the purpose is to provide a new and improved etching method capable of forming a structure.
- an organic low K film and a mask layer formed thereon are used as a layer to be etched, and the organic low k film layer has a shoulder portion.
- New damascene structure is formed by dry etching using at least two or more process gases.
- a clean and improved method is provided. That is, in the invention according to the first aspect of the present invention, after the mask layer is etched by the first process gas, the organic Low K film layer is continuously etched to the predetermined depth by the first process gas.
- the method is characterized by including a step and a second step of etching the organic Low K film layer with a second process gas after the first step.
- the invention according to the second aspect of the present invention is that, after etching the silicon nitride layer with the first process gas, the organic Low K film layer is subsequently subjected to at least dual damascene with the first process gas.
- the first process gas may include at least C and F.
- the first process gas may be a process gas of CF 4 and 0 2 and A r.
- the second process gas may include at least N and H.
- the second process gas may be a mixed gas of N 2 and H 2 .
- the first process gas for example, CF 4 and 0 2 and the mask layer in a mixed gas of r, for example, S i the N layer after etching continues organic L ow K film a predetermined thickness, such as at least a dual damascene structure
- the protective wall eg, C-F polymer
- the deposited polymer acts as a protective wall, and a shoulder loss at the junction between the via and the trench is formed. ).
- the shoulder is formed in a shape close to an ideal right angle, and a wiring structure having desired electrical characteristics can be obtained.
- FIG. 1 is a schematic configuration diagram of an etching apparatus to which the present invention can be applied.
- FIG. 2 is a process diagram of an etching method according to the present embodiment.
- FIG. 3 is a process chart of the etching method according to the present embodiment.
- FIG. 4 is a process chart of the etching method according to the present embodiment.
- FIG. 5 is a schematic configuration diagram of a dual damascene structure according to the present embodiment.
- Figure 6 shows the condition of shoulder loss at the junction between the trench and the via
- FIG. 7 is a graph showing the relationship between via etching time and shoulder loss.
- FIG. 1 is a schematic configuration diagram of an etching apparatus to which the present invention can be applied.
- FIG. 2 is a process diagram of an etching method according to the present embodiment.
- FIG. 3 is a process chart of the etching method according to the present embodiment.
- FIG. 4 is a process chart of the etching method according to the present embodiment.
- FIG. 5 is
- FIG. 8 is a graph showing CI s orbital photoelectron intensity when the overetching time is long (sIot25) and when it is short (sIot24).
- 9 If over first etch time is long (s I ot 25) and short have if (s I ot 24) and the CI s orbital photoelectron scan Bae-vector of S i LK, CHF - CH 2 , the GHF- CHF It is a graph which shows the result of having separated each peak.
- Figure 1 0 is a table showing CHF- CH 2, CH F- photoelectron intensity ratio of CHF that peak separation.
- FIG. 1 A schematic configuration of a parallel plate type plasma etching apparatus will be described as an example of an etching apparatus for performing the above.
- a processing chamber 104 is formed in a processing vessel 102 grounded for safety in the etching apparatus 100 shown in the figure, and a susceptor that can move up and down is provided in the processing chamber 104.
- the constituent lower electrode 106 is arranged.
- An electrostatic chuck 110 connected to a high-voltage DC power supply 108 is provided above the lower electrode 106.
- an object to be processed for example, a semiconductor wafer ( Hereinafter, it is referred to as “wafer”.) W is placed on the upper surface of the electrostatic chuck 110.
- An insulating focus ring 112 is placed around the wafer W placed on the lower electrode 106.
- a high-frequency power supply 120 is connected to the lower electrode 106 via a matching device 118.
- an upper electrode 122 having a number of gas discharge holes 122a is arranged on the ceiling of the processing chamber 104 facing the mounting surface of the lower electrode 106.
- An insulator 123 is interposed between the upper electrode 122 and the processing vessel 102 to be electrically insulated.
- a high-frequency power supply 121 that outputs plasma-generating high-frequency power via a matching box 119 is connected to the upper electrode 122.
- a gas supply pipe 124 is connected to the gas discharge hole 122a, and a first process gas, for example, a gas containing at least C and F, is connected to the gas supply pipe 124. to include CF 4, O 2, and a r first process gas supply system that supplies 1 2 6 a, 1 2 6 b, 1 2 6 c, the second process gas, for example at least N and H
- a second process gas supply system for supplying gases, more specifically N 2 and H 2 is connected to 126 d and 126 e.
- the first process gas supply systems 1 26 a, 126 b, and 126 c include on-off valves 13 2 a, 132 b, and 13 2 c and flow control valves 13 4 a, 134 b, 1 34 supplies a first process gas through a G CF 4 gas supply source 1 3 6 a, 0 2 gas supply source 1 3 6 b, a r gas source 1 36 c are connected.
- the second process gas supply systems 126 d and 126 e are supplied with the second process gas via on-off valves 132 d and 132 e and flow control valves 134 d and 134 e.
- the N 2 gas supply source 1336 d and the H 2 gas supply source 136 e are connected respectively.
- FIG. 1 shows a process of simultaneously forming a via wiring connecting the upper circuit pattern to the Cu wiring 204 of the lower circuit pattern and a trench wiring between the upper circuit patterns.
- the Cu wiring 204 of the lower circuit pattern is formed in the SiLK layer 202.
- a Si1 ⁇ 1 layer 206 As a protective film, an organic layer constituting an interlayer insulating film layer, a SiLK layer 208 as an owK film, and further trenches and vias are formed.
- the first hard mask as a hard mask layer of
- the SIN layer 210 and an oxide film layer 212 serving as a second hard mask are formed.
- a photoresist (PR) layer for forming a trench is formed, and a PR pattern for trench 224 is formed by a predetermined lithographic process. Further, as shown in FIG.
- PR photoresist
- the oxide layer 211 is etched by using the PR pattern 214 for the trench to form a hard mask for the trench, and the remaining photoresist layer is formed. Attach and remove 214.
- a photoresist (PR) layer for via formation is formed, and a via PR pattern 216 is formed by a predetermined lithographic process.
- the SiN layer 210 is first etched to form a via hard mask, and the via Vias are etched in the SiLK layer 208, which is an organic LowK film, using a hard mask.
- the etchability of the SiN as the hard mask and the SiLK as the organic LowK film is improved.
- first process gas with, for example, a mixed gas of CF 4 and 0 2 and a r, shoulder S i a N layer after etching, subsequently the organic and o wK film a predetermined thickness, such as at least a dual damascene structure Over-etch to the depth corresponding to the part.
- a protective wall for example, a CF polymer can be deposited on the side wall of the via formed in the organic owK film. You. Next, as shown in Fig.
- the via PR pattern 216 is asshinged, and a via hole is further dug into the SiLK layer 208.
- the second process gas having a high selectivity with respect to the hard mask layer for example, a gas mixture of N 2 and H 2 is used to assemble the via PR pattern 2 16. And etching of the SiLK layer 208 are performed. Furthermore, (3 Step) As shown in FIG.
- the third process gas showing a high selectivity ratio to O Xide, for example using a mixed gas of CH 2 F 2 0 2 and A r , OX ⁇ de layer 211 as a hard mask, and etching the SiN layer 210 to form a trench hard mask 210 comprising the oxide layer 212 and the SiN layer 210. No 2 is formed.
- the processing gas is switched again to the second process gas having a high selectivity to the hard mask layer, and the hard mask for trench is removed. Etch the SiLK layer 208 using 0/2 12 to form a trench above the via and also dig the via down to the upper part of the SiN layer 206.
- the processing gas is switched again to the third process gas having a high selectivity to the hard mask, Si LK and Cu, and the Cu wiring 2 Etch the SiN layer 206 formed on the top of 06 to penetrate the via.
- a dual damascene structure in which trenches and vias are formed simultaneously is completed.
- FIG. 5 shows, in order to better understand the features of the etching method according to the present embodiment described with reference to FIGS. The figures are shown in association with the signs of ⁇ , and the reference film thickness of each layer is also shown.
- the etching of the SiN layer by using the first process gas by the via PR pattern for via formation is performed. Over-etching is performed at the same time, and a via with a predetermined depth is simultaneously formed in the SiLK layer. Then, the vias (1 ') formed in the SiLK layer formed in this step are dug deeper than the trenches (4) in the subsequent process.
- a shoulder S is formed at the junction between the trench and the via formed in the SILK layer. Most preferably, the shoulder S is formed at a right angle. However, in practice, the shoulder is also etched during via formation, resulting in shoulder loss (shoulder drop). This degree of shoulder loss can be expressed by the a and b values shown in Fig.
- Figure 7 shows the relationship between shoulder loss (b value) and via etching time. As shown in the figure, the longer the via etching time, the lower the shoulder loss. This is because not only the S SN layer (part (1) in Fig. 5) is etched as in the past, but also after the via etching of the SIN layer is completed, it extends to the area of the SILK layer where further trenches are formed. By continuing via etching, it is assumed that this is the result of the formation of the via side wall [this protective wall]. The formation of the protective wall on the side wall of the organic Low K film by the etching method according to the present embodiment will be further described with reference to FIGS.
- the examples shown in the charts shown in Figs. 8 to 10 show the first process in which the SiN layer is etched with the first process gas and then the SiLK layer is over-etched, and the second process gas is used.
- the second step of etching the SiLK layer is performed in sequence to perform wiring. This shows the result when a groove is formed.
- sI ot 24 indicates the case where the first step was performed for about 20 seconds and the second step was performed for about 60 seconds (that is, the over-etching time was short).
- the case where the first step was performed for about 60 seconds and the second step was performed for about 30 seconds (that is, the over-etching time is long) are shown.
- Figure 8 shows raw data obtained by measuring the electron binding energy using photoelectron spectroscopy (XPS) for each of sIot24 and sIot25.
- XPS photoelectron spectroscopy
- Figure 1 0, GHF - CH 2, or GHF- pull the peak area of Burankurebe Le from the peak area of CHF, C-C as (S i LK) 1 00 The peak area of each peak area to which The ratio was calculated.
- Figure 1 As shown in 0, towards the over-etching time is long s I ot 25 is than overetching time is shorter s I ot 24 CHF- CH 2 or CH F -CHF a higher corresponding photoelectron intensity ratio connexion As a result, it can be seen that a strong protection wall is formed on the via sidewall.
- the etching of the SiN layer is followed by the over etching of the SiLK layer to a predetermined depth, thereby forming a protective wall on the side wall of the via. It is possible to reduce the shoulder loss generated in the shoulder region at the junction between the wrench and the via. ( Note that this protective wall is removed by a cleaning process using an organic amine-based organic solvent or an ammonium fluoride-added organic solvent.
- the plasma etching apparatus shown in FIG. 1 has been described as an example of an apparatus for performing the etching method according to the present embodiment, but the present invention is not limited to this example.
- the plasma etching apparatus shown in FIG. 1 has been described as an example of an apparatus for performing the etching method according to the present embodiment, but the present invention is not limited to this example.
- SiLK was used as the organic LowK film, but the present invention is not limited to such an example.
- the organic low K film examples include a polyfluorinated naphthalene polymer film, a maleimide benzocyclobutene polymer film, a polyperfluorocyclobutene aromatic ether film, a polyimide film, a polyallyl ether film, a parylene film, a hydrogenated diamond film, Applicable to polytetrafluoroethylene.
- the present invention can be applied to a divinylsiloxane benzocyclobutene polymer film in which silica is partially substituted and added to an organic polymer film, a silica-added polyimide film, and the like.
- the present invention is not limited to such an example.
- a so-called hard mask in addition to the silicon nitride film (SiN) as the first hard mask, a silicon oxide film (S ⁇ 02)
- insulating films such as one-pilot (S ⁇ C)
- porous silicon nitride film silicon oxynitride film (S i ON), alumina nitride (AIN) or silica film
- titanium nitride Ti N
- Metal nitride films such as tantalum nitride (TaN) and titanium alloys Bitumen (TiC) can be used.
- a conductive nitride film such as a TiN film or a TaN film
- copper is buried in such wiring trenches and vias, and then the conductive nitride film is removed by a chemical mechanical polishing method or a dry etching method.
- a second hard mask in addition to the silicon oxide film (Si02), an insulating film such as a silicon nitride film (SiN) porous silica film, a silicon nitride film, or a silicon oxynitride film, or a titanium nitride (SiN2) film is used.
- Metal nitride films such as TiN) and tantalum nitride (TaN) or titanium carbide films (TiC) can be used.
- the important points in selecting these hard masks are (1) the materials of the first hard mask and the second hard mask are different, and (2) at least the first hard mask has at least C.
- a protective wall is deposited when a via hole is formed in the underlying organic low K film that is etched with a mixed gas containing F and subsequently etched.
- the over-etching in the first step is performed to a depth exceeding the shoulder region which is the junction between the trench and the via has been described as an example, but the present invention is not limited to such an example. Not done.
- the amount and time of over-etching can be arbitrarily set according to the specifications required for the final product. Even if the over-etching is performed to a depth that does not reach the above-mentioned shoulder region, a certain amount of shoulder loss can be reduced. The effect can be obtained.
- the first process gas has been described as an example a case of using a mixed gas of GF 4 0 2 and A r, the present invention is not limited to such an example.
- the first process gas Is a mixed gas of fluorocarbon gas such as CHF 3 , C 4 F a , CH 2 F 2 , C 4 F 6, and C 5 F 8 , oxygen and a rare gas. Any material that sometimes forms a protective wall containing GF may be used.
- the present invention is not limited to such an example.
- Ammonia (NH 3 gas) or N 2 H 4 may be used as the second process gas.
- What is important for the second process gas is that it has a high etching selectivity for organic and low-wK films, and at the same time has an etching property for photo-resist. This means that the etching selectivity with respect to the SiN film 206) is low (the etching rate is relatively small).
- the protective film 206 may be a silicon carbide / porous silicon nitride film. Further, the present invention is not limited to the processing method of the above embodiment.
- a dual damascene structure having an organic low wK film and a mask layer formed thereon as a layer to be etched and having a shoulder portion in the organic low wk film layer
- the second process gas etches the trench.
- Any treatment method can be used as long as the treated polymer acts as a protective wall to suppress shoulder loss at the junction between the via and the wrench.
- the treatment with the second process gas can be performed. Before or second It does not limit the use of any process gas after the treatment with the process gas.
- the first process gas for example, CF 4 and 0 2 and the mask layer in a mixed gas of A r, for example, S i N layer
- the organic low K film is etched to a predetermined thickness, for example, at least to a depth corresponding to the shoulder portion of the dual damascene structure, so that the protective wall, for example, a CF-based polymer becomes a via sidewall. Will accumulate on the ground.
- the deposited polymer acts as a protective wall, and a shoulder loss at the junction between the via and the trench is formed. ).
- a second process gas for example, a mixed gas of N 2 and H 2
- the shoulder is formed in a shape close to an ideal right angle, and a desired wiring structure can be obtained. Work time can be reduced.
- the present invention is applicable to a semiconductor device manufacturing process, particularly an etching process. More specifically, the present invention covers an organic Low K film and a mask layer formed thereon. The present invention can be used for a method of forming a dual damascene structure having a shoulder portion in the organic Low K film layer as an etching layer by dry etching using at least two or more process gases.
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Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/312,292 US7030028B2 (en) | 2000-06-26 | 2001-06-26 | Etching method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000191378A JP4477750B2 (ja) | 2000-06-26 | 2000-06-26 | エッチング方法 |
JP2000-191378 | 2000-06-26 |
Publications (1)
Publication Number | Publication Date |
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WO2002001619A1 true WO2002001619A1 (fr) | 2002-01-03 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2001/005442 WO2002001619A1 (fr) | 2000-06-26 | 2001-06-26 | Procede de gravure |
Country Status (5)
Country | Link |
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US (1) | US7030028B2 (ja) |
JP (1) | JP4477750B2 (ja) |
KR (1) | KR20030021180A (ja) |
TW (1) | TW514965B (ja) |
WO (1) | WO2002001619A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10247913A1 (de) * | 2002-10-14 | 2004-04-22 | Robert Bosch Gmbh | Plasmaanlage und Verfahren zum anisotropen Einätzen von Strukturen in ein Substrat |
EP1720202A4 (en) * | 2004-02-09 | 2009-04-29 | Found Advancement Int Science | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND INSULATION FILM COATING METHOD |
JP4723871B2 (ja) * | 2004-06-23 | 2011-07-13 | 株式会社日立ハイテクノロジーズ | ドライエッチング装置 |
JP4543976B2 (ja) * | 2005-03-16 | 2010-09-15 | ヤマハ株式会社 | 接続孔形成法 |
US7569478B2 (en) * | 2005-08-25 | 2009-08-04 | Tokyo Electron Limited | Method and apparatus for manufacturing semiconductor device, control program and computer storage medium |
JP5011782B2 (ja) * | 2006-03-28 | 2012-08-29 | 東京エレクトロン株式会社 | 半導体装置の製造方法、プラズマ処理装置及び記憶媒体。 |
US8263498B2 (en) | 2006-03-28 | 2012-09-11 | Tokyo Electron Limited | Semiconductor device fabricating method, plasma processing system and storage medium |
US8547986B2 (en) * | 2007-04-30 | 2013-10-01 | Apple Inc. | System and method for resource block-specific control signaling |
JP5067068B2 (ja) | 2007-08-17 | 2012-11-07 | 東京エレクトロン株式会社 | 半導体装置の製造方法及び記憶媒体 |
JPWO2009154173A1 (ja) * | 2008-06-17 | 2011-12-01 | 株式会社アルバック | 多段型基板の製造方法 |
JP2012064713A (ja) * | 2010-09-15 | 2012-03-29 | Toshiba Corp | 半導体装置の製造方法 |
US8580694B2 (en) * | 2011-08-25 | 2013-11-12 | United Microelectronics Corp. | Method of patterning hard mask layer for defining deep trench |
US9761436B2 (en) | 2014-06-30 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US9245763B2 (en) * | 2014-03-13 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US9601348B2 (en) * | 2014-03-13 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming same |
JP2015198135A (ja) * | 2014-03-31 | 2015-11-09 | 株式会社東芝 | 半導体装置の製造方法 |
JP6877290B2 (ja) * | 2017-08-03 | 2021-05-26 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
US11002063B2 (en) * | 2018-10-26 | 2021-05-11 | Graffiti Shield, Inc. | Anti-graffiti laminate with visual indicia |
CN110112079B (zh) * | 2019-04-29 | 2021-06-15 | 中国电子科技集团公司第十三研究所 | 台阶样块的刻蚀工艺参数评价方法 |
US20210066064A1 (en) * | 2019-08-30 | 2021-03-04 | Applied Materials, Inc. | Methods and apparatus for cleaning metal contacts |
Citations (2)
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JP2000114373A (ja) * | 1998-10-08 | 2000-04-21 | Toshiba Corp | 半導体装置の製造方法 |
JP2000269329A (ja) * | 1999-03-16 | 2000-09-29 | Nec Corp | 半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW374224B (en) * | 1998-04-03 | 1999-11-11 | United Microelectronics Corp | Dual damascene process for manufacturing low k dielectrics |
US6284149B1 (en) * | 1998-09-18 | 2001-09-04 | Applied Materials, Inc. | High-density plasma etching of carbon-based low-k materials in a integrated circuit |
TW400619B (en) * | 1999-03-05 | 2000-08-01 | United Microelectronics Corp | The manufacture method of dual damascene structure |
US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
US6309962B1 (en) * | 1999-09-15 | 2001-10-30 | Taiwan Semiconductor Manufacturing Company | Film stack and etching sequence for dual damascene |
-
2000
- 2000-06-26 JP JP2000191378A patent/JP4477750B2/ja not_active Expired - Fee Related
-
2001
- 2001-06-26 TW TW090115401A patent/TW514965B/zh not_active IP Right Cessation
- 2001-06-26 KR KR1020027017662A patent/KR20030021180A/ko not_active Withdrawn
- 2001-06-26 WO PCT/JP2001/005442 patent/WO2002001619A1/ja active Application Filing
- 2001-06-26 US US10/312,292 patent/US7030028B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000114373A (ja) * | 1998-10-08 | 2000-04-21 | Toshiba Corp | 半導体装置の製造方法 |
JP2000269329A (ja) * | 1999-03-16 | 2000-09-29 | Nec Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
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JP2002009058A (ja) | 2002-01-11 |
KR20030021180A (ko) | 2003-03-12 |
JP4477750B2 (ja) | 2010-06-09 |
US20040063331A1 (en) | 2004-04-01 |
US7030028B2 (en) | 2006-04-18 |
TW514965B (en) | 2002-12-21 |
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