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WO2002001364A2 - Memoire cache non volatile integree a un dispositif de stockage de masse - Google Patents

Memoire cache non volatile integree a un dispositif de stockage de masse Download PDF

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Publication number
WO2002001364A2
WO2002001364A2 PCT/US2001/017845 US0117845W WO0201364A2 WO 2002001364 A2 WO2002001364 A2 WO 2002001364A2 US 0117845 W US0117845 W US 0117845W WO 0201364 A2 WO0201364 A2 WO 0201364A2
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WO
WIPO (PCT)
Prior art keywords
volatile
data
mass storage
storage device
cache
Prior art date
Application number
PCT/US2001/017845
Other languages
English (en)
Other versions
WO2002001364A3 (fr
Inventor
Richard Coulson
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to GB0228874A priority Critical patent/GB2380031B/en
Priority to JP2002506433A priority patent/JP2004502237A/ja
Priority to DE10196383T priority patent/DE10196383T1/de
Priority to AU2001266657A priority patent/AU2001266657A1/en
Publication of WO2002001364A2 publication Critical patent/WO2002001364A2/fr
Publication of WO2002001364A3 publication Critical patent/WO2002001364A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21—Employing a record carrier using a specific recording technology
    • G06F2212/214—Solid state disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/313—In storage device

Definitions

  • Embodiments of the present invention relate to data storage. More particularly, embodiments of the present invention relate to a mass storage device having a non- volatile cache.
  • a computer can store data both in a volatile memory and a non-volatile mass storage device.
  • volatile memory include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), Rambus dynamic random access memory (RDRAM), etc.
  • Examples of a non-volatile mass storage device include, but are not limited to, a hard disk drive, a 3.5-inch diskette, a 5.25-inch floppy diskette, a ZIP® disk (e.g., manufactured by Iomega Corporation of Roy, Utah), a Jaz® disk (e.g., manufactured by Iomega Corporation), an LS-120 Superdisk (e.g., manufactured by Imation Corporation of Oakdale, Minnesota), a rewritable Digital Versatile Disc (DVD-RAM), a Read/ Write Compact Disk (CD-RW), a magnetic mass storage device, an optical mass storage device, a magneto-optical mass storage device, a holographic storage device, etc.
  • Examples of data stored in a non-volatile memory of a computer include computer instructions (e.g., an operating system, one or application programs, etc.) and data that is accessed by computer instructions.
  • Non-volatile mass storage devices such as hard disk drives, typically do not lose the data stored thereon when the non-volatile mass storage device loses power (e.g., when power to the computer is turned off, due to a power outage, etc.).
  • Non-volatile memory generally has significantly greater access times for retrieval and storage of data as compared to volatile memory.
  • Non-volatile memory is also typically less expensive per storage unit (e.g., per megabyte, per gigabyte, etc.) than certain volatile memory such as DRAM, SRAM, RDRAM, etc.
  • a computer typically includes a processor that can perform operations based on instructions and data. Instructions and data to be operated on by the processor can be copied from the slower, non-volatile mass storage device (e.g., a hard disk drive, etc.) to the faster, volatile memory (e.g., a DRAM main memory, an SRAM cache, etc.) because the faster, volatile memory typically has a significantly lesser memory access time than the non-volatile mass storage device. Processor performance and computer performance can be enhanced when memory access times are reduced.
  • non-volatile mass storage device e.g., a hard disk drive, etc.
  • volatile memory e.g., a DRAM main memory, an SRAM cache, etc.
  • non- volatile mass storage device e.g., disk drive
  • volatile memory e.g., DRAM main memory, SRAM cache, etc.
  • the non-volatile mass storage device is often a performance bottleneck.
  • Known disk drives include a volatile cache (e.g., a DRAM cache, an SRAM cache), but such volatile caches are typically part of the disk drive's microcontoUer's main memory address space and thereby byte addressed.
  • FIG. 1 shows an illustration a computer system in accordance with an embodiment of the present invention.
  • FIG. 2 shows an illustration of the organization of a non-volatile cache in accordance with an embodiment of the present invention.
  • FIG. 3 shows a method in accordance with an embodiment of the present invention.
  • FIG. 4 shows a method in accordance with an embodiment of the present invention.
  • a non- volatile mass storage device includes a non-volatile cache.
  • the non-volatile cache can store information that is written to, or can be read from, the main mass storage medium of the non-volatile mass storage device.
  • the non-volatile cache can have a lesser access time with respect to a data read as compared to the access time of a data read from the main mass storage medium of the non-volatile mass storage device.
  • a computer system incorporating an embodiment of the present invention can have increased system performance when data stored on the nonvolatile mass storage device is read from the non-volatile cache instead of from the main mass storage medium of the non-volatile mass storage device.
  • FIG. 1 shows an illustration a computer system ("computer") in accordance with an embodiment of the present invention.
  • Computer 110 can include a processor 120 coupled to a memory 130.
  • the term “coupled” encompasses a direct connection, an indirect connection, a direct communication, an indirect communication, etc.
  • Processor 120 can be, for example, a Pentium® III processor manufactured by Intel Corporation of Santa Clara, California, an application specific integrated circuit (ASIC), a microcontroller, etc.
  • Memory 130 encompasses devices that store digital information such as DRAM, RDRAM, SRAM, read only memory (ROM), flash memory, etc.
  • a system bus can provide a communication path between the processor 120 and system components.
  • the system bus can be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture Bus (EISA), etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture Bus
  • a chipset can be coupled to, and manages interaction between, the processor 120 and other system components, such as the memory 130, mass storage device 140, peripheral components attached to an expansion bus, etc.
  • the term chipset encompasses a group of one or more integrated circuit chips that acts as a hub (or core) to transfer data between the processor and other system components. Examples of a chipset include the 820 and 810E chipsets made by Intel Corporation.
  • a chipset can be a single integrated circuit chip or can comprise two or more integrated circuit chips.
  • a chipset can include a memory control hub. In an embodiment including a PCI bus, a memory control hub can perform functionality known as "northbridge functionality.”
  • a chipset can include an input/output controller hub.
  • an input/output controller hub can perform functionality known as "southbridge functionality.”
  • Processor 120 is also coupled to mass storage device 140 via a communication path 135.
  • communication path 135 can be an Integrated Device Electronics (IDE) bus, an Enhanced IDE (EIDE) bus, an AT Attachment (ATA) bus, etc.
  • the communication path 135 can be an expansion bus such as a small computer system interface (SCSI) bus, an IEEE 1394 bus, a Universal Serial Bus (USB), etc.
  • mass storage device 140 examples include a hard disk drive, a ZIP ® drive, a Jaz ® drive, a CD-RW drive, a DVD-RAM drive, an LS-120 Superdisk drive, a magnetic storage device, an optical storage device, a magneto-optical storage device, a holographic storage device, etc.
  • a hard disk drive is the Cheetah 18XL hard disk drive manufactured by Seagate Technology Inc. of Scotts Valley, California.
  • Mass storage device 140 can include a mass storage device controller 141, a main mass storage medium 148, and a non- volatile cache 149.
  • the mass storage device controller 141 can include a microcontroller 142, a memory 143, interface logic 144, main mass storage medium ECC (error control and checking) logic 145, and non-volatile cache ECC logic 146.
  • mass storage device controller 141 can include one or more ASICs implementing functions to operate mass storage device 140 (e.g., a first ASIC incorporating a processor, a memory and interface logic and a second ASIC implementing ECC logic, etc.).
  • Microcontroller 142 can execute instructions stored in memory 143 to control the operations of mass storage device 140 (e.g., memory 143 can include read only memory that stores program instructions to initialize and operate mass storage device 140 upon power up, memory 143 can store instructions to perform reads of data from mass storage device 140, memory 143 can store instructions to control formatting of and/or writing data to mass storage device 140, etc.).
  • the memory 143 can also include a buffer (e.g., a volatile memory buffer, etc.) that can temporarily hold data that is being written to, or read from, mass storage device 140.
  • Microcontroller 142 and interface logic 144 can process requests from processor 120 to read data from, or write data to, mass storage device 140.
  • mass storage device 140 is a hard disk drive and interface logic 144 can be IDE interface logic, EIDE interface logic, ATA interface logic, SCSI interface logic, Fibre Channel interface logic, InfiniBand interface logic, etc.
  • mass storage device 140 is a CD-RW drive or a DVD-RAM drive and interface logic 144 is ATA Packet Interface (ATAPI) logic.
  • ATAPI ATA Packet Interface
  • logic encompasses hardware, firmware, software, a combination thereof, etc.
  • the mass storage device 140 is a hard disk drive
  • the main mass storage medium 148 includes one or more platters.
  • Each platter can have one or more recordable surfaces, and each recordable surface can be read/written by a particular read/write head.
  • Each surface can be divided into a plurality of tracks; and each track can be divided into a plurality of physical sectors.
  • a hard disk drive has a plurality of recordable surfaces, the collection of all the tracks at the same radial location on all recordable surfaces is called a cylinder.
  • the location of each physical sector of a hard disk drive can be specified by a physical address specifying the cylinder, head (surface), and physical sector.
  • Logical addresses of hard disk data can include logical sector addresses, logical block addresses, etc.
  • the hard disk drive controller of the hard disk drive can organize all of physical sectors into logical sectors (e.g., assigning each physical sector a logical sector address, etc.), and a mapping algorithm can map each logical sector address to a particular physical address.
  • the hard disk drive can be considered sector- oriented (i.e., sector addressable).
  • a hard disk drive controller can also map collections of physical sectors into particular logical block addresses.
  • the hard disk drive can be considered block-oriented (i.e., block addressable).
  • Non- volatile cache 149 can cache data that is typically stored on main mass storage medium 148.
  • Non-volatile cache 149 can cache data read from, and written to, main mass storage medium 148.
  • Non-volatile cache 149 can have a faster access time as compared to the access time of main mass storage medium 148. Accordingly, data reads from, and data writes to, mass storage device 140 can be completed faster as compared to data read/writes to main mass storage medium 148.
  • data read/writes to non-volatile cache 149 require less power as compared to data read/writes.
  • Write-back algorithms i.e., write backs from the non-volatile cache 149 to the main mass storage medium 148) can be implemented to increase cache performance. In another embodiment, write-through caching is implemented.
  • Non- volatile cache 149 can store a duplicate copy of frequently used mass storage device data and provide reduced access times for that frequently used data.
  • a copy of the data can be stored in non-volatile cache 149;
  • the data can be written to non-volatile cache 149 and written to main mass storage medium 148 according to a write-back algorithm, a write-through protocol, etc.
  • Non-volatile cache 149 is a non-volatile memory
  • the data saved in the non-volatile cache is typically not lost when the power (e.g., power to the mass storage device 140, power to the computer 110, etc.) is turned off.
  • Non-volatile cache 149 can be any type of memory that can be read from/written to and retain its data when power external to the non-volatile cache 149 is removed or turned off.
  • Non-volatile cache 149 can be, for example, a flash memory, a battery backed-up DRAM, a battery backed-up SRAM, an atomic force probe memory, a magnetic RAM, a ferro-electric RAM, a holographic memory, a storage array, etc.
  • reads from non-volatile cache 149 can be destructive reads.
  • Non-volatile cache 149 can be a block-oriented cache where data is accessed (e.g., written, read, etc.) in logical blocks.
  • mass storage device 140 when mass storage device 140 receives a data request (e.g., a data request to read data from mass storage device 140 onto communications path 135, a data request to write data to the mass storage device 140 from communications path 135, etc.), the data request can contain an address that is a logical block address, a logical sector address, etc.
  • each of the data entries stored in non-volatile cache 149 corresponds to data stored at a logical address of main mass storage medium 148.
  • a nonvolatile cache 149 can increase system perform because data reads/writes from the nonvolatile cache 149 do not require the warm-up time incidental in writing/reading data from hard disk drive platters (e.g., spinning the platters up to operational speed, positioning read/write heads, etc.). For example, the time required for system boot-up of computer 110 can be reduced when boot-up information (e.g., operating system data, device drivers, application data, etc.) is read from a non-volatile cache 149 as opposed to hard disk drive platters. Keystroke/mouseclick latency experienced by a user of computer 110 can also be reduced.
  • boot-up information e.g., operating system data, device drivers, application data, etc.
  • cache management instructions can manage data reads from/writes to non-volatile cache 149.
  • the cache management instructions can be stored in memory 143, can be part of a mass storage device driver, etc.
  • Cache management instructions can make decisions regarding what data can be cached, what data can be evicted from the cache, what data can be written back to the main mass storage medium, when data write-backs occur, etc.
  • Cache management instructions can also determine what data can be pre-fetched into the non-volatile cache 149. Cache management determinations, such as whether certain data should be cached in non- volatile cache 149, can be made using known cache management algorithms.
  • cache management instructions can determine which data to write back using, for example, a least recently used (LRU) algorithm, a random replacement algorithm, etc.
  • LRU least recently used
  • a mass storage device driver for the mass storage device 140 can be a typical mass storage device driver (e.g., AT API. SYS in a WIN98 environment, etc.), and the cache management instructions can be stored in memory 143.
  • the existence of non-volatile cache can be transparent to the operating system.
  • the cache management instructions can be part of cache management logic of mass storage device controller 141.
  • FIG. 2 shows an illustration of the organization of a non-volatile cache in accordance with an embodiment of the present invention.
  • a non-volatile cache 200 (e.g., non- volatile cache 149 of FIG.1) may store a plurality of cache entries 205. Each cache entry 205 can include a table entry field 210 and a data entry 220.
  • Data entry 220 can include a valid field 222, a modified field 224, an address field 226, a data field 228, and an ECC field 229.
  • the table entry field 210 of a cache entry 205 can correspond to tag/index information for each data entry 220 of the cache entry 205.
  • the plurality of table entry fields 210 can comprise a cache directory table 215, and the cache directory can be accessed to determine whether a specific set of data of a mass storage device (e.g., a disk sector of a hard disk drive, a logical block of a hard disk drive, etc.) is present in the non- volatile cache.
  • a mass storage device e.g., a disk sector of a hard disk drive, a logical block of a hard disk drive, etc.
  • the table entry field 210 of a cache entry 205 can store an address (e.g., a logical sector address, a logic block address, etc.) of the data entry 220 of the cache entry 205.
  • the cache directory table 215 can be searched using, for example, a known search algorithm. Alternatively, the cache directory can be sorted using a hashing algorithm.
  • the mass storage device is a hard disk drive
  • the presence of a requested disk sector in a non-volatile cache can be confirmed by comparing the sector address of the requested disk against the sector addresses stored in the cache directory table 215.
  • a non-volatile cache can be a fully associative cache.
  • a non-volatile cache can be a set associative cache.
  • each of the cache entries 205 stored in a non-volatile cache of a mass storage device corresponds to a logical block of a mass storage device. In another embodiment, each of the cache entries 205 stored in a non-volatile cache of a mass storage device corresponds to a sector (e.g., a physical sector, a logical sector) of a mass storage device.
  • each table entry of the cache directory table 215 can be four bytes long, and the cache directory table 215 can use eight megabytes of non-volatile memory.
  • the size of a cache directory table 215 can be reduced (and thus the speed of the average cache access increased) by including a block of multiple disk sectors in each cache entry.
  • a data entry 220 of a cache entry 205 may have a valid field 222, a modified field 224, an address field 226, a data field 228, and an ECC field 229.
  • Valid field 222 may be set to "valid” (e.g., one of a logical one and a logical zero, etc.) when cache entry 205 contains valid data and may be set to "invalid" (e.g., the other of a logical one and a logical zero, etc.) when cache entry 205 does not contain valid data.
  • valid fields of the evicted data entries can be changed from
  • Modified field 224 can be set to "modified” if the data in cache entry 205 is not identical to the data stored in the corresponding location on the main mass storage medium of the mass storage device. For example, and referring to FIGS. 1 and 2, when data corresponding to a logical address of the mass storage device 140 is written back to the mass storage device 140 and stored in the non-volatile cache 149, and that data was modified after having been read from the main mass storage medium 140, then the modified field 224 for the non-volatile cache entry 205 can be set to "modified" to indicate that the copy of the data corresponding to that logical address stored in the non-volatile cache 149 is different than the data corresponding to that logical address stored on the main mass storage medium 148.
  • Modified field 224 can be referred to as a "dirty bit" and can be cleared when the data is successfully written-back to the main mass storage medium 148 and retained in the non- volatile cache 149.
  • Address field 226 can contain the address (e.g., logical address, physical address) for the data stored in the cache entry 205.
  • the address field 226 can store the sector address and can be referred to as a "sector identifier.”
  • address field 226 can contain the starting sector address of the logical block where each logical block has a known fixed size.
  • Data field 228 can store the data of cache entry 205.
  • data field 228 can contain a disk sector of data (e.g., 512 bytes), a logical block of data, etc.
  • ECC field 229 can stores error correcting codes for the data of the cache entry 205.
  • each logical block of data is associated with an error correcting code.
  • FIG. 3 shows a method in accordance with an embodiment of the present invention.
  • a mass storage device receives a request for data (e.g., a request from processor 120, a request from an operating system of computer 110, a request from an application being executed on computer 110, etc.) (box 310). Whether the requested data is stored in a non-volatile cache of the mass storage device is determined (box 320).
  • the request for data includes an address, and that address is used to generate a cache hit or cache miss indication.
  • a cache directory includes addresses of the data cached in the nonvolatile cache, and an indication that the requested data is cached in the non-volatile cache can be generated based on the cache directory and the address of the requested data.
  • the data is read from the nonvolatile cache (box 330), error checking and correction can be performed upon the read data (box 335), and the data can be sent from the mass storage device (box 340).
  • FIG. 4 shows a method in accordance with an embodiment of the present invention.
  • a request to store data in non-volatile mass storage device is received (box 410).
  • a user editing a document in a word processing program can instruct the word processing program to save the document.
  • the word processing program can include an auto save feature that causes the document to be saved periodically.
  • an operating system can instruct that data stored in main memory (e.g., DRAM) be stored to a hard disk drive or other non-volatile memory
  • instructions adapted to be executed by a processor to perform a method are stored on a computer-readable medium.
  • the computer-readable medium can be a device that stores digital information.
  • a computer-readable medium includes a ROM as is known in the art for storing software and/or firmware (e.g., microcode).
  • the computer-readable medium can be accessed by a processor suitable for executing instructions adapted to be executed.
  • the term "adapted to be executed" is meant to encompass any instructions that are ready to be executed in their present form (e.g., machine code) by a processor, or require further manipulation (e.g., compilation, decryption, or provided with an access code, etc.) to be ready to be executed by a processor.
  • Methods and apparatus in accordance with embodiments of the present invention can advantageously cache data read from, or written to, a mass storage device in a nonvolatile cache.
  • the non-volatile cache can retain its data even when external power to the non-volatile cache and the mass storage device is turned off.
  • Embodiments of the present invention can reduce the access time for data read from, or written to, a mass storage device and thereby increase system performance of a system having a mass storage device.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un appareil et des procédés associés à un dispositif de stockage de masse non volatile comprenant une mémoire cache non volatile.
PCT/US2001/017845 2000-06-23 2001-06-01 Memoire cache non volatile integree a un dispositif de stockage de masse WO2002001364A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0228874A GB2380031B (en) 2000-06-23 2001-06-01 Non-volatile cache integrated with mass storage device
JP2002506433A JP2004502237A (ja) 2000-06-23 2001-06-01 大容量ストレージ装置に集積された不揮発性キャッシュ
DE10196383T DE10196383T1 (de) 2000-06-23 2001-06-01 In eine Massenspeichereinrichtung integrierter nicht-flüchtiger Cache
AU2001266657A AU2001266657A1 (en) 2000-06-23 2001-06-01 Non-volatile cache integrated with mass storage device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60201100A 2000-06-23 2000-06-23
US09/602,011 2000-06-23

Publications (2)

Publication Number Publication Date
WO2002001364A2 true WO2002001364A2 (fr) 2002-01-03
WO2002001364A3 WO2002001364A3 (fr) 2002-04-04

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JP (1) JP2004502237A (fr)
CN (1) CN1465009A (fr)
AU (1) AU2001266657A1 (fr)
DE (1) DE10196383T1 (fr)
GB (1) GB2380031B (fr)
TW (1) TW576966B (fr)
WO (1) WO2002001364A2 (fr)

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EP1710674A1 (fr) * 2003-12-25 2006-10-11 Kabushiki Kaisha Toshiba Dispositif de stockage et systeme de traitement d'informations
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JP4972064B2 (ja) * 2008-09-25 2012-07-11 シャープ株式会社 光ディスク駆動制御装置
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US7103724B2 (en) 2002-04-01 2006-09-05 Intel Corporation Method and apparatus to generate cache data
EP1710674A1 (fr) * 2003-12-25 2006-10-11 Kabushiki Kaisha Toshiba Dispositif de stockage et systeme de traitement d'informations
EP1710674A4 (fr) * 2003-12-25 2009-03-25 Toshiba Kk Dispositif de stockage et systeme de traitement d'informations
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CN1465009A (zh) 2003-12-31
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TW576966B (en) 2004-02-21
GB2380031B (en) 2004-09-29
GB2380031A (en) 2003-03-26
AU2001266657A1 (en) 2002-01-08
WO2002001364A3 (fr) 2002-04-04
GB0228874D0 (en) 2003-01-15

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