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WO2002078071A3 - Method of shrinking an integrated circuit gate - Google Patents

Method of shrinking an integrated circuit gate Download PDF

Info

Publication number
WO2002078071A3
WO2002078071A3 PCT/US2001/048596 US0148596W WO02078071A3 WO 2002078071 A3 WO2002078071 A3 WO 2002078071A3 US 0148596 W US0148596 W US 0148596W WO 02078071 A3 WO02078071 A3 WO 02078071A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
integrated circuit
patterned
shrinking
circuit gate
Prior art date
Application number
PCT/US2001/048596
Other languages
French (fr)
Other versions
WO2002078071A2 (en
Inventor
Angela T Hui
Kouros Grandehari
Bhanwar Singh
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2002241636A priority Critical patent/AU2002241636A1/en
Publication of WO2002078071A2 publication Critical patent/WO2002078071A2/en
Publication of WO2002078071A3 publication Critical patent/WO2002078071A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

An exemplary method of fabricating an integrated circuit includes patterning a first layer (28) having a first dimension where the first layer (28) is disposed over an etch stop layer (26) and a second layer (24); oxidizing the surface (30) of the patterned first layer (28); removing the oxidized surface (30) of the patterned first layer (28) resulting in a second dimension for the patterned first layer (28); and etching the etch stop layer (26) and the second layer (24) using the patterned first layer (28) having the second dimension as a hard mask.
PCT/US2001/048596 2001-03-27 2001-12-12 Method of shrinking an integrated circuit gate WO2002078071A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002241636A AU2002241636A1 (en) 2001-03-27 2001-12-12 Method of shrinking an integrated circuit gate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81836901A 2001-03-27 2001-03-27
US09/818,369 2001-03-27

Publications (2)

Publication Number Publication Date
WO2002078071A2 WO2002078071A2 (en) 2002-10-03
WO2002078071A3 true WO2002078071A3 (en) 2004-01-08

Family

ID=25225385

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/048596 WO2002078071A2 (en) 2001-03-27 2001-12-12 Method of shrinking an integrated circuit gate

Country Status (2)

Country Link
AU (1) AU2002241636A1 (en)
WO (1) WO2002078071A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895244A (en) * 1998-01-08 1999-04-20 Texas Instruments - Acer Incorporated Process to fabricate ultra-short channel nMOSFETs with self-aligned silicide contact
US6060377A (en) * 1999-05-07 2000-05-09 Advanced Micro Devices, Inc. Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895244A (en) * 1998-01-08 1999-04-20 Texas Instruments - Acer Incorporated Process to fabricate ultra-short channel nMOSFETs with self-aligned silicide contact
US6060377A (en) * 1999-05-07 2000-05-09 Advanced Micro Devices, Inc. Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations

Also Published As

Publication number Publication date
WO2002078071A2 (en) 2002-10-03
AU2002241636A1 (en) 2002-10-08

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