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WO2002041368A3 - Method of forming conductive interconnections wherein a barrier layer is removed by an etching process - Google Patents

Method of forming conductive interconnections wherein a barrier layer is removed by an etching process Download PDF

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Publication number
WO2002041368A3
WO2002041368A3 PCT/US2001/023578 US0123578W WO0241368A3 WO 2002041368 A3 WO2002041368 A3 WO 2002041368A3 US 0123578 W US0123578 W US 0123578W WO 0241368 A3 WO0241368 A3 WO 0241368A3
Authority
WO
WIPO (PCT)
Prior art keywords
barrier layer
layer
opening
etching process
forming conductive
Prior art date
Application number
PCT/US2001/023578
Other languages
French (fr)
Other versions
WO2002041368A2 (en
Inventor
Errol Todd Ryan
Paul R Besser
Frederick N Hause
Frank Mauersberger
William S Brennan
John A Iacoponi
Peter J Beckage
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2001279032A priority Critical patent/AU2001279032A1/en
Publication of WO2002041368A2 publication Critical patent/WO2002041368A2/en
Publication of WO2002041368A3 publication Critical patent/WO2002041368A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The present invention is directed to a method of removing barrier layers by performing an etching process instead of a CMP process. In one embodiment, the method comprises forming a layer of insulating material 20, forming an opening 22 in the layer of insulating material 20, and forming a barrier layer 26 above an upper surface 25 of the insulating layer 20 and in the opening 22. The method further comprises forming a conductive material above the upper surface 27 of the barrier layer 26 and in the opening 22, performing a CMP process to remove substantially all of the conductive material positioned above the upper surface 27 of the barrier layer 26, performing at least one etching process on the barrier layer 26 to remove substantially all of the barrier layer 26 positioned above the upper surface 25 of the insulating layer 20, and, in some cases, performing at least one chemical mechanical polishing operation to remove at least a portion of the conductive material positioned outside of the opening 22 and above the upper surface 25 of the insulating layer 20 to define a conductive interconnection positioned within the opening 22 in the insulating layer 20.
PCT/US2001/023578 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process WO2002041368A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001279032A AU2001279032A1 (en) 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71264300A 2000-11-14 2000-11-14
US09/712,643 2000-11-14

Publications (2)

Publication Number Publication Date
WO2002041368A2 WO2002041368A2 (en) 2002-05-23
WO2002041368A3 true WO2002041368A3 (en) 2002-08-29

Family

ID=24862964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/023578 WO2002041368A2 (en) 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Country Status (2)

Country Link
AU (1) AU2001279032A1 (en)
WO (1) WO2002041368A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0930647A1 (en) * 1998-01-20 1999-07-21 International Business Machines Corporation Method to selectively fill recesses with conductive metal
US6107193A (en) * 1997-12-19 2000-08-22 Mosel Vitelic Inc. Completely removal of TiN residue on dual damascence process
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107193A (en) * 1997-12-19 2000-08-22 Mosel Vitelic Inc. Completely removal of TiN residue on dual damascence process
EP0930647A1 (en) * 1998-01-20 1999-07-21 International Business Machines Corporation Method to selectively fill recesses with conductive metal
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

Also Published As

Publication number Publication date
WO2002041368A2 (en) 2002-05-23
AU2001279032A1 (en) 2002-05-27

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