+

WO2001035704A1 - Tableau de connexions multicouche a deux cotes et son procede de fabrication - Google Patents

Tableau de connexions multicouche a deux cotes et son procede de fabrication Download PDF

Info

Publication number
WO2001035704A1
WO2001035704A1 PCT/US2000/030015 US0030015W WO0135704A1 WO 2001035704 A1 WO2001035704 A1 WO 2001035704A1 US 0030015 W US0030015 W US 0030015W WO 0135704 A1 WO0135704 A1 WO 0135704A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
opening
wiring board
insulating layer
Prior art date
Application number
PCT/US2000/030015
Other languages
English (en)
Inventor
Tatsunori Koyanagi
Original Assignee
3M Innovative Properties Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Company filed Critical 3M Innovative Properties Company
Priority to KR1020027005812A priority Critical patent/KR20020049023A/ko
Priority to US10/088,982 priority patent/US6803528B1/en
Publication of WO2001035704A1 publication Critical patent/WO2001035704A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Definitions

  • the present invention relates to a multi-layer double-sided wiring board having wiring layers formed on both sides of an insulating layer using a two-layer tape technology that forms a conductive layer of copper or the like on an insulating layer of a polyimide film or the like without interposing an adhesive layer therebetween, and also having a blind via interconnecting the wiring layers and closed at one end with the conductive layer.
  • the invention also relates to a method of fabricating such a multi-layer double-sided wiring board.
  • a multi-layer double-sided wiring board having wiring layers formed on both sides of an insulating layer using a two-layer tape technology, and also having a blind via interconnecting the wiring layers, is fabricated in accordance with the following process.
  • a two-layer tape comprising a film made of an insulating material such as polyimide and a conductive layer formed by sputtering or plating on the upper surface of the film
  • an opening whose upper end is closed with the upper conductive layer is formed in the insulating layer by selectively etching the lower surface of the film.
  • a wiring pattern is formed on the upper surface by an additive process or a subtractive process.
  • a conductive layer is formed by sputtering or plating over the entire lower surface including the inside wall of the opening and the portion of the upper conductor which is exposed in the opening. In this way, the blind via is formed with the upper and lower conductive layers interconnected within the opening in a back-to-back configuration.
  • the bonding strength decreases.
  • it is practiced to deposit an interface layer containing a dissimilar metal such as Cr, Ni, or the like by sputtering on the film prior to the copper sputtering, thereby increasing the peel strength between the base and lead in the finished product.
  • Japanese Unexamined Patent Publication No. 5-327224 discloses that when sputtering copper, high-purity copper is used in order to prevent disconnection within the via hole.
  • a multi-layer double- sided wiring board which provides excellent adhesion between the conductive layer and the insulating layer because of the provision of an interface layer therebetween, and which exhibits excellent conductivity reliability because the upper and lower conductive layers are joined together within the blind via without interposing a dissimilar metal.
  • an object of the present invention to provide a multi-layer double-sided wiring board and a method of fabricating the same, wherein the above two problems, i.e., the adhesion between the lower conductive layer and the insulating layer and the reliability of conductivity between the upper and lower conductive layers in the blind via, are solved simultaneously.
  • a multi-layer double- sided wiring board comprising: an insulating layer having an opening formed therein; a first conductive layer formed on an upper surface of the insulating layer; a second conductive layer formed on a lower surface of the insulating layer and covering an inside wall of the opening and a portion of the first conductive layer which is exposed in the opening; and an interface layer interposed between the insulating layer and the first and second conductive layers, wherein the second conductive layer directly contacts the first conductive layer in the opening without interposing the interface layer therebetween.
  • the interposition of the interface layer provides good adhesion between the insulating layer and the second conductive layer, and at the same time, conductivity reliability is retained since the first and second conductive layers contact each other in the opening.
  • the second conductive layer directly contacts the insulating layer at the inside wall of the opening without interposing the interface layer therebetween. In this case, while the adhesion between the second conductive layer and the inside wall of the insulating layer is not sufficient, this portion acts as a stress reliever for the conductive layer and thus serves to secure the conductivity reliability of the conductive layer.
  • the interface layer contains at least one metallic element selected from the group consisting of nickel, cobalt, zinc, and chromium.
  • Also provided is a method of fabricating a multi-layer double-sided wiring board comprising the steps of: selectively removing a portion of an insulating layer on an upper surface of which is formed a conductive layer, and thereby forming in the insulating layer an opening whose upper end is closed with the conductive layer; forming an interface layer over an entire lower surface; selectively removing at least a portion of the interface layer which contacts the first conductive layer; and forming a conductive layer over the entire lower surface.
  • Also provided is a method of fabricating a multi-layer double-sided wiring board comprising the steps of: forming an opening pattern by selectively removing a portion of a conductive layer formed on a lower surface of an insulating layer with an interface layer interposed therebetween, the insulating layer also having a conductive layer formed on an upper surface thereof with an interface layer interposed therebetween; selectively removing a portion of the insulating layer as well as a portion of the interface layers by using the thus patterned lower conductive layer as a mask, and thereby forming in the insulating layer an opening whose upper end is closed with the upper conductive layer; and forming a conductive layer over the entire lower surface including a side wall of the opening and a portion of the upper conductive layer which is exposed in the opening.
  • FIG. 1 shows a cross section illustrating the vicinity of the blind via 18 in the previously described multi-layer double-sided wiring board in which the interface layer 14 is simply interposed between the insulating layer 10 and the lower conductive layer 12.
  • the reliability of conductivity significantly degrades because the interface layer 14 of a dissimilar metal is formed interposing between the upper conductive layer 16 and lower conductive layer 12 in the blind via 18 where they are interconnected.
  • Figure 2 shows a cross section illustrating the vicinity of a blind via in a multilayer double-sided wiring board according to a first embodiment of the present invention. Since the interface layer 14 is not formed interposing between the upper conductive layer 16 and lower conductive layer 12 in the blind via 18 where they are interconnected, the reliability of conductivity is retained.
  • Figure 3 shows a cross section illustrating the vicinity of a blind via in a multilayer double-sided wiring board according to a second embodiment of the present invention.
  • the interposing interface layer 14 is absent not only in the portion of the blind via 18 connecting to the upper conductor 16, but also in the side wall of the via hole.
  • this portion acts as a stress reliever for the entire structure of the conductive layer and thus serves to secure the conductivity reliability of the conductive layer. Results of reliability evaluation tests conducted on the respective samples are shown in Table 1. Table 1
  • both the first and second embodiments satisfy the required quality, but the second embodiment where the interface layer is not interposed at the side walls of the via hole exhibits a better quality. It will also be noted that the second embodiment is easier to fabricate than the first embodiment.
  • the thickness of the interface layer is 10 nm to 500 nm, and preferably 150 nm, and the material is a single-element or a composite material containing Co, Ni, Zi, or Cr, and a material containing Cr is particularly preferable.
  • the upper and lower conductive layers are 5 ⁇ m to 50 ⁇ m in thickness, and the material is preferably copper.
  • the thickness of the insulating layer is 10 ⁇ m to 100 ⁇ m, and preferably 50 ⁇ m, and polyimide is preferable as the material. Dry plating methods for the conductive layers include sputtering and vapor deposition.
  • the multi-layer double-sided wiring board having the blind via of the present invention is fabricated, for example, by one of the following two processes. The first process will be described first.
  • a lead preform is formed by forming a metal layer 16 only on the upper surface of the substrate in the position where the resist pattern does not exist.
  • An interface layer 14 and a metal thin-film layer 26 are formed in this order over the entire lower surface of the substrate ( Figure 4(d)).
  • a resist layer is formed on the lower surface of the substrate. (The upper surface is covered by a protective layer (resist).
  • a metal layer 30 is formed by sputtering over the entire lower surface without forming an interface layer therebetween.
  • the side wall of the via is thus made electrically conductive (for the subsequent plating step) ( Figure 5(b)).
  • a resist layer is formed on the lower surface of the substrate, and the resist layer is exposed to light through a photo mask and then developed to form a resist pattern (not shown).
  • a lead preform 32 is formed on the lower surface of the substrate in the position where the resist pattern of the resist layer does not exist ( Figure 5(c)). 14) The resist pattern on the lower surface of the substrate is removed, and a lead is formed by etching off the upper and lower surfaces of the substrate in the positions 34 where the lead preforms are not formed ( Figure 5(d)).
  • the second process uses as the starting material a polyimide tape coated with copper foil on both sides thereof ( Figure 6(a)).
  • This double-sided copper foil polyimide tape is fabricated by metalizing both surfaces of the polyimide 10 by vacuum evaporation such as sputtering or vaporization, followed by plating to give a certain degree of thickness to the copper foil.
  • interface layers 36 are formed to increase the bonding strength.
  • Photoresist is applied to the double-sided copper foil polyimide tape, and the photoresist is exposed and developed to form a via hole pattern. Using the developed photoresist as a mask, the copper foil on one side of the tape is etched ( Figure 6(b)). If necessary, a PI (polyimide) opening pattern may be formed at the same time.
  • PI polyimide
  • the polyimide layer 10 is etched by a laser or chemical etching (hydrazine, etc.). The copper foil on the opposite side is exposed through the via thus etched ( Figure 6(c)).
  • the polyimide inside the via is made electrically conductive.
  • Making the polyimide conductive is accomplished by copper sputtering 40 alone without forming an interface layer ( Figure 6(d)).
  • electrolytic copper plating is performed to give the necessary thickness to the copper on the polyimide inside the via.
  • photoresist layers are formed on the upper and lower surfaces of the substrate, and using glass masks on the upper and lower surfaces, the photoresist layers are exposed for development.
  • Lead preforms are formed on the upper and lower surfaces of the substrate in the positions where the resist patterns of the resist layers does not exist.
  • a lead is formed by etching off the upper and lower surfaces of the substrate in the positions where the lead preforms are not formed ( Figure 6(e)). 8) If necessary, a PI pattern is formed by photolithography plus chemical etching, die-punching laser processing, etc.. which is further followed by finish plating or solder resist coating.
  • the circuit patterning has been described by taking an additive process as an example, but instead, a subtractive process may be used.
  • Figure 1 is a cross-sectional view of a multi-layer double-sided wiring board where an interface layer is formed underlying the lower conductive layer.
  • Figure 2 is a cross-sectional view of a multi-layer double-sided wiring board according to a first embodiment of the present invention.
  • Figure 3 is a cross-sectional view of a multi-layer double-sided wiring board according to a second embodiment of the present invention.
  • Figure 4 is a diagram for explaining the first half of the process sequence in a first example of the fabrication process for the multi-layer double-sided wiring board of the present invention.
  • Figure 5 is a diagram for explaining the second half of the process sequence in the first example of the fabrication process for the multi-layer double-sided wiring board of the present invention.
  • Figure 6 is a diagram for explaining a second example of the fabrication process for the multi-layer double-sided wiring board of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un tableau de connexions comportant des couches multiples et deux côtés, permettant d'obtenir une excellente adhérence entre la couche conductrice (12) et la couche isolante (10) par la présence d'une couche d'interface et présentant une très bonne conductivité, étant donné que les couches conductrices supérieure et inférieure (16, 12) sont réunies à l'intérieur du trou borgne (18) sans intercalation de matériau différent.
PCT/US2000/030015 1999-11-05 2000-10-31 Tableau de connexions multicouche a deux cotes et son procede de fabrication WO2001035704A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020027005812A KR20020049023A (ko) 1999-11-05 2000-10-31 다중층 양면식 배선 기판 및 이를 제조하는 방법
US10/088,982 US6803528B1 (en) 1999-11-05 2000-10-31 Multi-layer double-sided wiring board and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31510699A JP2001144441A (ja) 1999-11-05 1999-11-05 多層両面配線基板とその製造方法
JP11/315106 1999-11-05

Publications (1)

Publication Number Publication Date
WO2001035704A1 true WO2001035704A1 (fr) 2001-05-17

Family

ID=18061501

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/030015 WO2001035704A1 (fr) 1999-11-05 2000-10-31 Tableau de connexions multicouche a deux cotes et son procede de fabrication

Country Status (3)

Country Link
JP (1) JP2001144441A (fr)
KR (1) KR20020049023A (fr)
WO (1) WO2001035704A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8119918B2 (en) 2005-09-14 2012-02-21 Nec Corporation Printed circuit board and semiconductor package
JP2008294415A (ja) * 2007-04-27 2008-12-04 Sanyo Electric Co Ltd 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器
JP5303364B2 (ja) * 2009-05-28 2013-10-02 日東電工株式会社 両面配線回路基板およびその製造方法
JP6819416B2 (ja) * 2017-03-31 2021-01-27 大日本印刷株式会社 貫通電極基板およびその製造方法
WO2024084994A1 (fr) * 2022-10-20 2024-04-25 住友電気工業株式会社 Carte de circuit imprimé

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
EP0255911A2 (fr) * 1986-08-05 1988-02-17 International Business Machines Corporation Structure de couches métal-diélectrique-métal avec des traversées de connexion à basse résistance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
EP0255911A2 (fr) * 1986-08-05 1988-02-17 International Business Machines Corporation Structure de couches métal-diélectrique-métal avec des traversées de connexion à basse résistance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
37306: "PROCESSES FOR MANUFACTURING MULTILAYER TAB", RESEARCH DISCLOSURE,GB,INDUSTRIAL OPPORTUNITIES LTD. HAVANT, no. 373, 1 May 1995 (1995-05-01), pages 303 - 307, XP000518622, ISSN: 0374-4353 *

Also Published As

Publication number Publication date
JP2001144441A (ja) 2001-05-25
KR20020049023A (ko) 2002-06-24

Similar Documents

Publication Publication Date Title
US6803528B1 (en) Multi-layer double-sided wiring board and method of fabricating the same
US6684497B2 (en) Manufacturing methods for printed circuit boards
KR20010050609A (ko) 박형 집적 레지스터/캐패시터/인덕터 패캐이지 및 제조방법
US4964947A (en) Method of manufacturing double-sided wiring substrate
US6284982B1 (en) Method and component for forming an embedded resistor in a multi-layer printed circuit
US7520053B2 (en) Method for manufacturing a bump-attached wiring circuit board
US6411194B2 (en) Production method of thin film resistance element formed on printed circuit board, and thin film resistance element employing the method
JP4141135B2 (ja) 多層配線基板の製造方法
EP0436385B1 (fr) Méthode de fabrication d'une Inductance à haute fréquence
WO1989010985A1 (fr) Procede de fabrication de circuits multi-couche avec regions de flexion dynamique, et circuits flexibles fabriques a l'aide de ce procede
EP0373208A1 (fr) Procede pour fabriquer des circuits multicouches avec des zones de flexion dynamique, et circuits flexibles ainsi fabriques
WO2001035704A1 (fr) Tableau de connexions multicouche a deux cotes et son procede de fabrication
JPH05335713A (ja) 片側閉塞微小スルホール付きプリント基板用積層板、およびそのプリント基板用積層板への導通メッキ方法
US20240015884A1 (en) Wiring circuit board and method for producing wiring circuit board
JPH02301187A (ja) 両面配線基板の製造方法
JPH05235510A (ja) 薄膜パターンの形成方法
JP3144596B2 (ja) 薄膜電子部品及びその製造方法
JP2530008B2 (ja) 配線基板の製造方法
JPH05152764A (ja) 多層配線板の製造法
JPH02228092A (ja) 両面配線基板の製造方法
CN119521570A (zh) 电路板的制作方法以及电路板
JP4857547B2 (ja) 部品を内蔵した多層配線基板の製造方法
JPH03225894A (ja) プリント配線板の製造方法
JPH04102341A (ja) Ｔａｂテープの製造方法
JPH09270329A (ja) 電子部品及びその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR SG US

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 10088982

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 1020027005812

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020027005812

Country of ref document: KR

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载