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WO2001024260A1 - Configuration tridimensionnelle peu couteuse de puces a bosses pour modules de puissance electroniques integres - Google Patents

Configuration tridimensionnelle peu couteuse de puces a bosses pour modules de puissance electroniques integres Download PDF

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Publication number
WO2001024260A1
WO2001024260A1 PCT/US2000/025708 US0025708W WO0124260A1 WO 2001024260 A1 WO2001024260 A1 WO 2001024260A1 US 0025708 W US0025708 W US 0025708W WO 0124260 A1 WO0124260 A1 WO 0124260A1
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WIPO (PCT)
Prior art keywords
solder
recited
module
substrate
further including
Prior art date
Application number
PCT/US2000/025708
Other languages
English (en)
Inventor
Xingsheng Liu
Guo-Quan Lu
Original Assignee
Virginia Tech Intellectual Properties, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/657,782 external-priority patent/US6349044B1/en
Application filed by Virginia Tech Intellectual Properties, Inc. filed Critical Virginia Tech Intellectual Properties, Inc.
Priority to AU75933/00A priority Critical patent/AU7593300A/en
Publication of WO2001024260A1 publication Critical patent/WO2001024260A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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    • H02M1/32—Means for protecting converters other than automatic disconnection
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/342—Active non-dissipative snubbers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention generally relates to packaging of semiconductor integrated circuits for medium-level power applications such as inverters for motor drives and convertors for processing equipment and, more specifically, to modular structures for power semiconductor devices and associated integrated circuits.
  • low power digital circuit packaging is principally concerned with reduction of signal propagation time (generally by minimization of signal path length) , noise immunity and heat dissipation while there is a trend toward reduction of voltages representing logic states.
  • power modules may include one or more large chips of varying sizes which carry high currents and may switch rapidly (although generally at lower frequency than digital logic circuits) or operate in an analog fashion with dramatically different effects on distribution of generated heat and thermal cycling and further including packaging with low-power control and protection circuits. Connections to power chips also must carry large currents.
  • the connections generate strong electromagnetic fields, resulting in proximity effects and uneven current distribution among bonding wires as well as excess parasitic inductance which can increase the voltages the devices must withstand as large currents are reduced at a rapid rate.
  • wire bonding has proven to be one of the weakest areas of power module packaging since high current requires thick 0.25 - 0.50 mm wires to be employed for wire bonds.
  • One of the main failure mechanisms in high power devices such as insulated gate bipolar transistors (IGBT) modules subject to thermal cycling is wire bond lift-off due to the large coefficient of thermal expansion (CTE) mismatch between metal (e.g. aluminum) wires and silicon chips.
  • Wire bonds may also be effectively damaged by the unavoidable deformation and working of the wire during the bonding process that may generate small dimensional differences that concentrate heat generation and mechanical stress. Motion of the wires to accommodate CTE mismatch during thermal cycling and due to proximity effects cumulatively contribute to fatigue of both the wire and the bond. Therefore, the mean time to failure of power modules is often foreshortened while increased service lifetimes are demanded (e.g. about thirty years) which cannot be achieved with current package technologies, especially including wire bonds.
  • an integrated power electronic module including a first multi-layer substrate, a second substrate having a power semiconductor device attached thereto with ball bonds, and an arrangement for assembling the first multi-layer substrate with the second substrate and the power semiconductor device such that the power semiconductor device is sandwiched between the first substrate and the second substrate.
  • a method of making a compliant solder bump structure comprising steps of screening a paste containing a first solder material onto a surface to form an inner solder bump, placing a ball of a second solder material on the inner solder bump to form a middle solder bump, and reflowing the first solder material.
  • Figure 1 is a cross-sectional view of a first embodiment of a package structure in accordance with the invention
  • Figure 2 is a cross-sectional view of a second embodiment of a package structure in accordance with the invention
  • Figures 3A and 3B illustrate acceptable and preferred solder bump structures, respectively, Figures 3C, 3D, 3E, 3F and 3G illustrate the process of forming the preferred solder bump of Figure 3B,
  • Figure 3H is a flow chart illustrating the process of Figures 3C - 3G
  • Figure 4 is an isometric and partially cutaway view of a generalized device including solder bumps for bonding in accordance with the invention
  • FIG. 5A and 5B are perspective views of an exemplary IGBT and integrated circuit device including solder bumps for bonding in accordance with the invention
  • Figure 6 is a flow diagram illustrating the process flow for manufacture of the package structures of Figures 1 and 2, and
  • Figures 7A, 7B and 7C graphically depict a comparison of electrical performance of the invention and prior known packaging techniques.
  • IPEM integrated power electronic module
  • the basic principle of the invention is to sandwich at least the power devices 14 between parallel compliant and/or flexible heat conductive plates (with suitable heat conductive encapsulation) which also serve as inter-chip wiring and the formation of connections with solder bumps. By doing so, wire bonds are eliminated with their associated parasitics and mechanical vulnerability and numerous additional paths for heat transfer and thermal control are provided. Internal stresses due to CTE mismatch are regulated by temperature spreading and improved heat dissipation as well as through the use of compliant plates and compliant connections provided by the encapsulated solder bumps and the regulation of stresses by distribution through the encapsulant. Reliability and long service life are also addressed by solder bump geometry including aspect ratio and shape.
  • FC flip-chip
  • CSP chip scale packaging
  • flip-chip is intended principally to connote that some assembly is performed to form a sub-assembly and the subassembly is inverted (relative to an arbitrary orientation convention or practice) for further processing and assembly.
  • chip scale packaging in the context of the present invention, is intended principally to connote that interconnection and protection structures are applied at the chip level.
  • the first embodiment of Figure 1 includes a first plate 11 including a heat conducting substrate such as Burquist board (a laminate comprising a relatively thick layer of aluminum 12, a thin layer of insulating polyimide or other dielectric and a layer 13 of copper of arbitrary thickness) , direct bond copper (DBC) on both sides of an aluminum nitride (AIN) substrate which has a CTE closely matched to silicon or other insulated metal substrate.
  • a heat conducting substrate such as Burquist board (a laminate comprising a relatively thick layer of aluminum 12, a thin layer of insulating polyimide or other dielectric and a layer 13 of copper of arbitrary thickness) , direct bond copper (DBC) on both sides of an aluminum nitride (AIN) substrate which has a CTE closely matched to silicon or other insulated metal substrate.
  • the metal layers should be sufficiently thick (and symmetrical) to provide adequate thermal and electrical conduction (while thin enough to avoid alteration of dimensional change with temperature of the assembly with aluminum nitride) and the
  • the copper layer 12 may thus be patterned as required to provide interconnections, shielding and the like.
  • the second plate comprises a layer of metal (e.g. copper) 16, an insulator layer 17 and a second metal (e.g. copper) layer 18. Both metal layers may be patterned as desired to form interconnections, shielding and the like, as well, and respective areas of metal layer 16 and metal layer 18 may be connected as desired by through hole metallizations or vias 17 ' .
  • the power devices are bonded to metal layer
  • solder balls 15 and underfill 22 comprising a low viscosity material tending to wick into small voids is applied and which can later be cured by heat treatment at a temperature below the melting point of solder to a solid form having a relatively low elastic modulus compared to other polymers and close to that of solder (e.g. in the range of about 3 - 20 Gpa) .
  • a reasonably close match of elastic modulus provides a quasi-continuum at the solder interface and suppresses the stress concentration associated with sharp angles between the solder and die.
  • the underfill material, after curing, should have a glass transition temperature well above the service temperature of the IPEM. Underfill materials having these properties and suitable for practice of the invention are commercially available.
  • the sub-assembly is "inverted" against patterned metal layer 13 such that the tallest of the power devices rest against surface 13 of the substrate 11 with voids filled with heat conductive viscous encapsulant which can be molded to conform to the shape of the void(s) .
  • Low-power sensor, control and protection devices 19 may be bonded with conventional solder bumps or other techniques such as ball bonds, solder preforms and the like, as desired or required, to the surface of patterned metal layer 18.
  • Power connections 13 ' may be made to the margin of metal layer 13 extending beyond or though cover 29 or in any other convenient manner.
  • Respective areas of metal layers 13 and 16 may be connected as desired by vias or passive devices (e.g. resistors, capacitors, etc.) 27 or the substrates or CSP packages of devices 28. Passive components/devices can also be connected only to patterned regions of either of the first or second substrates.
  • a heat spreader or heat sink 23 (such as a liquid cooled plate) can be attached to substrate 11 with adhesive 24 or any other suitable technique, if desired.
  • solder bump connections are substantially fully encapsulated, as will also be discussed in greater detail below, reliable connections are provided even at temperatures where the solder may be softened or molten.
  • Thermal conduction paths are provided in three dimensions from all surfaces of the power devices 28 to the heat conductive plates 11 and 16 - 18 which serve to minimize temperature gradients throughout the IPEM and to develop a substantially uniform temperature throughout the IPEM while maximizing the heat transfer surface area of the IPEM. Stress in the power devices is also relieved by the compliance of the encapsulant 21 and underfill 22 and/or the compliance of the substrate 17 and CTE of the power chips and the substrate 17 (and substrate 11) can be closely matched. Thus electrical, mechanical and thermal performance of the IPEM in accordance with the invention are all significantly improved in comparison with known prior power device packaging structures.
  • first and second embodiments are considered to be preferred where substantially passive cooling capacity is of overriding importance and lateral dimensions are not critical. It should be recognized, however, that combinations of features of the first and second embodiments may be used together to satisfy the requirements of particular applications as will be evident to those of ordinary skill in the art in view of this description of preferred embodiments of the invention and that the first and second embodiments can be employed interchangeably for a wide variety of applications. Likewise, the choice between the first and second embodiments may be dictated by the environment rather than the application or a combination of the application and the intended environment.
  • FIG. 2 The structure of Figure 2 is similar to that of Figure 1 except that metal layer 18 and underlying insulator 17 are omitted and low power sensor, control and/or protection circuits 19 can be mounted on patterned metal surfaces 13 and 16 in front of or behind the plane of the page.
  • the patterned metal surfaces 13 and 16 are supported on dielectric layers 25 and heat distribution is enhanced by the encapsulant and the metal layers 13, 16 while the dielectric layer 25 is relatively thin and actual thermal resistance is acceptably low since the thermal paths are shortened relative to those of Figure 1. Further, additional heat spreading is accomplished by the base of heat sinks 26 preferably applied to both sides of the package.
  • the structure is entirely symmetrical to further avoid the development of internal stresses.
  • the orientation of the power devices is unimportant in view of the heat conduction and compliance of the encapsulant.
  • all of the power device could be made or CSP packaging applied to develop a substantially uniform height for improved heat conduction to surface 13.
  • Power bus connections 27 can be made through the encapsulation at any point on the periphery of the device or even through the heat sinks 26 and dielectric 25, if desired.
  • solder ball form shown in Figure 3A is conventional in topology but not necessarily in scale.
  • the structure illustrated in Figures 3A and 3B include a passivation film on the surface of power device 28, as is customary.
  • An aluminum pad 31 is formed in an aperture in the passivation film 30 to permit contact to a conductive area of the power device 28.
  • Under-bu p metallurgy (UBM) 32 preferably including a titanium layer for adhesion and nickel and copper layers to make solderable contacts, is then applied over the aluminum contact pad. This metallization controls the shape of the ball formed when solder materials, generally applied by screening in the form of a paste or plating, is reflowed to form a protruding ball-shaped solder bump.
  • solder ball When a substrate (e.g. 16* corresponding to metal layer 16) is brought into contact with the solder bump and heated, the solder ball partially reflows to form a broadened and shortened conductor bonding UBM 32 and device 28 to the surface 16'.
  • a sharp corner remains at the interface of the solder ball and the bonding pads on the opposing surfaces.
  • the height and width (e.g. aspect ratio) of the solder bump is also not easily controllable and the inventors have found that these parameters are extremely important to reliability over large numbers of thermal cycles, particularly over large temperature excursions as are encountered in power modules .
  • the solder bump is formed as a triple stacked solder bump in accordance with a feature of the invention.
  • the inner bump 33 is Sn 96.5/Ag 3.5 alloy with a melting point of 221°C
  • the middle bump 34 is SN 10/Pb 90 alloy with a melting point of 268°C
  • the external bump 35 is eutectic solder (Sn 63/Pb 37) with a melting point of 183 °C an are sequentially applied while the temperature is appropriately regulated.
  • the overall height of the triple stacked solder bump is preferably about 10 - 40 mil and can be easily and readily regulated in accordance with the invention.
  • the triple stacked solder bumps are of increased compliance due to their metallurgy and shape (an "hourglass" form of increased height) and thus have an increased capacity to relieve stress caused by CTE mismatch. Additionally, the triple stacked solder bump is much more reliable over a much increased number of thermal cycles due to reduction of force concentration at the interface between the solder and the silicon die or the substrate.
  • the triple stacked solder bump in accordance with the invention includes three basic processes: stencil printing, solder ball placement and reflow, each of which is individually well- understood in the art.
  • a stencil or mask 36 is applied to the surface on which the triple stacked solder bumps are to be formed and on which structures 30, 31 and 32 are already in place.
  • the inner bump 33 is developed by screening (81, Figure 3H) solder paste through the stencil onto the UBM 32 with a nozzle, squeegee or the like 37.
  • the stencil 36 is then removed (82) and the pattern of solder paste thus transferred to the surface 80 is prebaked (82) to stabilize the solder paste forms as shown in Figure 3E.
  • the application of the middle bump is straight forward wherein a stencil or apertured plate 38 and corresponding to the pattern of stencil/mask 36 is applied above the inner bumps 33 and solder balls 34 of increased melting point relative to the inner bump solder material in the paste are inserted (84) into the apertures and pressed against the inner bumps.
  • the assembly is then heated (either before or after removal of stencil/apertured plate 38) to a temperature between the melting points of the inner bump and the solder balls 34 in order to reflow and reform (85) the inner bump and form bonds to both the UBM 32 and the solder ball 34 while solder ball 34 regulates the height of the triple stacked solder bump, as shown in Figure 3G.
  • the material for the outer bump 35 may be applied by screening or plating onto the solder ball/middle bump 34 or, preferably, by application of solder material by any method to the opposing surface to be bonded.
  • the region surrounding the solder bumps of Figures 3A and 3B is indicated as underfill. However, in accordance with a preferred form of the invention, a portion of the region can be filled with a molding resin 33, as shown in Figure 4, leaving only a relatively low profile portion of the solder bumps protruding above the surface. This feature provides additional close encapsulation of the solder bumps to improve electrical and mechanical properties thereof, particularly at high temperatures.
  • Chip scale packaging of the power devices can be limited to this feature or other features such as a thermally conductive layer or plate 34 and/or a protective plate or layer may be applied, as may be desired.
  • the only criterion for such additional features is that the heat transfer capabilities of the power device should not be significantly compromised or diminished.
  • An exemplary IGBT and an integrated circuit device formed in this manner are shown in Figures 5A and 5B, respectively.
  • the details of the chip manufacturing process are not important to the practice of the invention since the invention is applicable to any type of semiconductor device or integrated circuit formed with any chip design.
  • the chip manufacture should conclude with application of under-bump metal, as described above as depicted at 62.
  • solder materials for forming the solder bumps is applied and the solder reflowed to form the solder bumps in a manner appropriate to the type of solder bumps employed.
  • the completed chips can then be cleaned as shown at 64a and otherwise prepared for assembly.
  • the substrates are prepared by lamination and patterning as illustrated at 65.
  • solder can be applied to the substrates with a mask and a patterned layer of solder formed on the inner surface 16 ( Figures 1 and 2) of the substrate, as shown at 66 and 67, respectively.
  • Connections or passive components 27 ( Figure 1) such as metal posts, if needed, can also be formed or applied as part of this process.
  • the flip chip bonding of the chips to the second substrate is then performed as illustrated at 68.
  • underfill material is applied to fill interstices between the ball bonds. Curing of the underfill material can be performed at any time thereafter.
  • the control, sensor, protection and/or driver circuits can be added and the second substrate assembled to the first substrate. It should be noted that the order of these two steps is not important in the embodiment of Figure 1. In regard to the embodiment of Figure 2, it may be desirable to reverse the order of steps 69 and 70 in order to apply underfill to the low power circuits as well as the power chips.
  • FIG. 7A shows the performance of a flip-chip IPEM (FC-IPEM) or flip- chip on flex IPEM (FCOF_IPEM) depending on compliance or flexibility of the substrate 11 and/or 16 in accordance with the invention when compared to Figures 7B and 7C which represent performance of a comparable commercially available wire bond packaged IGBT device ( Figure 7B) and a comparable commercially available wire bond packaged power module (Figure 7C) , all switching 640 volts at 50 amperes.
  • the shape of the turn-on waveform is slightly improved, yielding somewhat enhanced switching speed.
  • the FC-IPEM/FCOF-IPEM in accordance with the invention shows an overshoot of 107 volts whereas the commercially available IGBT device exhibits an overshoot of 178 volts and the commercially available power module exhibits an overshoot of 205 volts.
  • the FC-IPEM/FCOF-IPEM of the invention exhibits an overshoot of about 16.5% whereas the wire bond packaged power module exhibits an overshoot of about 32%.
  • the overshoot (which is important since it can cause operating limits of the module to be exceeded; resulting in breakdown and possible destruction of the module as well as high losses) is nearly halved by the packaging in accordance with the invention.
  • this overshoot is a measure of the inductance contributions of both the power devices and the package and the reduction of overshoot by virtue of the invention is also a measure of the reduction in package resistance and inductance to negligible levels as a result of the invention.
  • high voltage rating devices which may be used where overshoot is likely to result in damage or destruction of the device are substantially more expensive and are associated with high conduction losses and low overall efficiency.
  • the invention provides a low-cost package for power semiconductor devices of all types which significantly improves the performance thereof by reducing resistive and inductive package parasitics to negligible levels while greatly enhancing reliability.
  • the process for forming the package is relatively simple and non-critical with large process windows that do not compromise manufacturing yield. Stacked solder balls of different materials provide a compliant connection of increased reliability and shape control.
  • the resistance and inductance of the package are reduced to negligible levels far below that of current power chips and thus the invention will support future performance improvements in foreseeable generations of power chips. Size reductions and increased control and protection arrangement complexity are accommodated by a compact package providing excellent thermal performance and mechanical support for chips and connections thereto.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Il est possible de ramener la résistance et l'inductance parasite provenant de l'interconnexion de puces semi-conductrices dans des modules de puissance à des niveaux négligeables grâce à l'emploi d'une robuste structure qui permet d'éviter complètement l'emploi de fils de connexions au profit de liaisons par bille et de procédés de fabrication avec puces à bosses, éventuellement avec un conditionnement de montage à puces en boîtiers et des bosses de soudure empilées en forme de sablier répondant à de strictes normes de conformité, de hauteur et de forme. La surmodulation de coupure se trouve réduite d'environ moitié, voire davantage, par rapport à celle d'un module de puissance comparable à fils de connexion. Les bosses de soudure en forme de sabliers garantissent un surcroît de conformité et de fiabilité pendant un nombre sensiblement plus élevé de cycles thermiques avec de vastes écarts de température.
PCT/US2000/025708 1999-09-24 2000-09-20 Configuration tridimensionnelle peu couteuse de puces a bosses pour modules de puissance electroniques integres WO2001024260A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU75933/00A AU7593300A (en) 1999-09-24 2000-09-20 Low cost 3d flip-chip packaging technology for integrated power electronics modules

Applications Claiming Priority (6)

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US15559999P 1999-09-24 1999-09-24
US15559899P 1999-09-24 1999-09-24
US60/155,598 1999-09-24
US60/155,599 1999-09-24
US09/657,782 US6349044B1 (en) 1999-09-09 2000-09-08 Zero voltage zero current three level dc-dc converter
US09/657,782 2000-09-13

Publications (1)

Publication Number Publication Date
WO2001024260A1 true WO2001024260A1 (fr) 2001-04-05

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DE10258565B3 (de) * 2002-12-14 2004-08-12 Semikron Elektronik Gmbh Schaltungsanordnung für Halbleiterbauelemente und Verfahren zur Herstellung
DE10329101A1 (de) * 2003-06-27 2005-01-27 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung
EP1548829A2 (fr) 2003-11-29 2005-06-29 Semikron Elektronik GmbH Patentabteilung Module à semi-conducteur de puissance et procédé pour sa fabrication
DE102004030042A1 (de) * 2004-06-22 2006-01-19 Infineon Technologies Ag Halbleiterbauelement
DE102004041088A1 (de) * 2004-08-24 2006-03-09 Infineon Technologies Ag Halbleiterbauteil in Flachleitertechnik mit einem Halbleiterchip
US7138708B2 (en) 1999-09-24 2006-11-21 Robert Bosch Gmbh Electronic system for fixing power and signal semiconductor chips
DE102007041921A1 (de) * 2007-09-04 2009-03-05 Siemens Ag Verfahren zur Herstellung und Kontaktierung von elektronischen Bauelementen mittels einer Substratplatte, insbesondere DCB-Keramik-Substratplatte
EP1407641A4 (fr) * 2001-06-28 2010-05-12 Skyworks Solutions Inc Structure et procede de fabrication d'un porte-puces sans conducteur
US8680666B2 (en) 2006-05-24 2014-03-25 International Rectifier Corporation Bond wireless power module with double-sided single device cooling and immersion bath cooling
CN105118810A (zh) * 2011-09-27 2015-12-02 台湾积体电路制造股份有限公司 三维集成电路的制造方法
EP3712934A1 (fr) * 2019-01-30 2020-09-23 Delta Electronics, Inc. Structure d'emballage et son procédé de formation
US11189555B2 (en) 2019-01-30 2021-11-30 Delta Electronics, Inc. Chip packaging with multilayer conductive circuit

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