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WO2001021294A2 - Evolution en fonction du trace du profil superficiel en metal de depot electrochimique - Google Patents

Evolution en fonction du trace du profil superficiel en metal de depot electrochimique Download PDF

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Publication number
WO2001021294A2
WO2001021294A2 PCT/US2000/040985 US0040985W WO0121294A2 WO 2001021294 A2 WO2001021294 A2 WO 2001021294A2 US 0040985 W US0040985 W US 0040985W WO 0121294 A2 WO0121294 A2 WO 0121294A2
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WIPO (PCT)
Prior art keywords
power
workpiece
time period
electroplating
reverse
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PCT/US2000/040985
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English (en)
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WO2001021294A3 (fr
Inventor
Thomas L. Ritzdorf
Dakin J. Fulton
Linlin Chen
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Semitool, Inc.
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Priority to EP00975648A priority Critical patent/EP1225972A4/fr
Publication of WO2001021294A2 publication Critical patent/WO2001021294A2/fr
Publication of WO2001021294A3 publication Critical patent/WO2001021294A3/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

  • the present invention relates to electrochemical deposition of metals on workpieces that define recessed microstructures.
  • FIGURE la provides a schematic illustration of the surface of a workpiece 10 including an insulator layer 12 into which recessed structures 14 have been formed.
  • a barrier layer 16 such as titanium nitride or tantalum nitride, is typically applied to the insulator to prevent migration of a subsequently applied metal (in the case of copper) into the insulator.
  • a seed layer 18 of metal onto the barrier layer is often deposited by a chemical vapor deposition technique, or alternately by a physical vapor deposition technique. Additional metal 20 is then applied to the seed layer using electrochemical deposition to fill the recessed microstructures, as well as the surrounding surface (the "field") with a conformal metal coating.
  • the deposited metal is removed from the field, such as through use of a chemical- mechanical polishing technique (CMP) or other planarization step, leaving the metal-filled trenches, vias or other field recessed microstructures (FIGURE lb).
  • CMP chemical- mechanical polishing technique
  • a difficulty that has been experienced in electrochemical deposition of metals onto substrates is the tendency of the metal to preferentially deposit onto the surrounding field surface rather than on the bottom and sides of the microrecessed structure, due to greater mass transfer outside of the recessed structure. This can result in undesirable voids or seams being formed in the metal that fills the recessed structure, undesirably increasing the resistivity of the filled structure.
  • Techniques have thus been developed for manipulating the deposition of metal so that the metal is preferentially deposited in the recessed microstructures during electroplating, through the incorporation of organic additives in the electroplating bath.
  • ECD electrochemical deposition
  • organic additives utilized to completely fill submicron recessed features typically have the role of either suppressing or enhancing metal deposition, based on the local additive concentration.
  • ECD processes as the standard deposition method for filling etched features to produce inlaid interconnects is due in large part to the fact that ECD is the only method to date capable of depositing preferentially inside the features, a characteristic that has been called "superfilling.” Andricacos, P.C. et al., ULSI Fabrication I and Interconnect and Contact Metallization: Materials, Processes, and Reliability, ECS Proc. 98-6.
  • CMP may differentially polish areas of the substrate due to the raised bumps, as further complicated by different grain structures for the bumps and surrounding areas.
  • FIGURE 2 which has been referred to as a "momentum plating" effect, is very interesting, in that initial concave features have been turned into convex topography. While this behavior may seem counterintuitive, it is theorized (without limitation) to be a relatively straightforward result of the additives that have been used to produce the super-conformal deposition profile, which is desired in the filling of deep sub-micron inlaid features.
  • the ability to fill deep sub-micron, high aspect ratio features used in inlaid copper interconnect technology is largely determined by the presence of organic additives to modify the electrolytic deposition process. Although there are a large number of names that have been used to describe these organic additives, they can be generally classified in two groups.
  • FIGURE 3 This effect, which results from the organic additives used in the copper plating bath, can be utilized to develop what is referred to as a "bottom-up" deposition profile (FIGURE 3).
  • This super-conformal deposition allows high aspect ratio, or even re-entrant, trenches to be filled without a seam.
  • FIGURES 3 and 4 demonstrate such a "bottom-up" fill sequence for vias and trenches, respectively, by use of conventional ECD copper plating techniques in a copper sulfate bath including accelerator and suppressor additives.
  • the trenches were preferentially filled during the initial deposition (FIGURE 4a) and the preferential deposition in the vicinity of the inlaid feature does not stop once the copper surface has become planarized (FIGURES 4b and 4c). It is almost as if the deposition process exhibits a "momentum" that carries this increased deposition rate over the nominal surface to produce a convex feature where there was initially a concave one. This effect is believed to be unique to electrodeposition in the presence of organic additives. Some clue as to the mechanism behind this effect can be derived from the fact that the bump height generated over a set of features is pattern dependent and exhibits a behavior similar to the pattern-dependent "loading" effect seen in plasma RIE processes.
  • the pattern dependence of the bump height formed during conventional plating in a copper sulfate bath using accelerator and suppressor additives can be seen in FIGURE 5, and represents the difference in copper thickness between the area immediately above a set of etched trenches and the field copper thickness, as measured using a stylus profilometer.
  • the bump height is strongly dependent on the dimensions associated with the underlying features as well as with the recipe used to plate the copper film.
  • the bump height was reduced roughly from 2 ⁇ to l ⁇ when the pitch was increased from l ⁇ to 2 ⁇ . This indicates that there is an interaction between the bump height and the feature and pitch widths.
  • the bump heights as a function of trench and pitch widths which was obtained from a second set of plating process parameters (Si) with the same organic additives, are also included in FIGURE 5.
  • the mechanism is as discussed in the preceding paragraph, one should expect to see the bumps eliminated by simply pausing the deposition at or near the point of planarizing the features for a time sufficient to allow diffusion to create a uniform surface concentration of additives, then proceeding with the deposition.
  • the inventors perform this experiment, there is surprisingly little or no effect on the bump height above the trenches found, as described below with respect to the present invention.
  • the inventors have found that in developing the present invention, that the wafer (workpiece) can be completely removed from the plating solution, rinsed and dried, then returned to the reactor for completion of deposition, with no obvious reduction ofthe bumps. This indicates that a property of the deposited film itself contributes to the profile evolution.
  • the inventors postulate, without limitation by theory, that it is the incorporation of the additives in the copper film as it is being deposited that causes the effect to be so persistent.
  • FIGURES 6a and 6b The incorporation of the additives into the film as it deposits is represented in FIGURES 6a and 6b, with the exception that this mechanism does not rely on the dynamic concentration gradients to produce the effect discussed herein.
  • the additive species may remain at or near the surface and continue to accelerate or suppress the local deposition rate, or an affinity of accelerator in the solution for the accelerator incorporated into the film could produce a similar effect.
  • the inventors theorize that the accelerator, in particular, is carried at the surface of the depositing film, where it continues to aid in the deposition of copper in the areas where it has the greatest concentration (i.e. immediately over the features).
  • Byproducts of the accelerators may also be incorporated into the substrate and cause this effect.
  • Another possible mechanism for bottom-up deposition and bump formation may be related to the interaction of chloride included in conventional copper sulfate plating baths and suppressor.
  • the chloride concentration is in the ppm level, and a concentration gradient can be easily formed inside small features.
  • the suppressor needs to interact with chloride to provide suppressing effect: J.J. Kelly and A.C. West, J Electrochem. Soc, 145(10), p. 3472(1998) and 145(10), p. 3477(1998). Therefore, the concentration gradient of chloride could lead to enhanced deposition rate in the feature. If the interaction rate between the suppressor and chloride is slower than the generation of fresh copper surface, the copper deposit on top ofthe feature continues to grow to form the bumps.
  • FIGURE 7 compares the effect of a leveling agent on bump formation and gap fill. In the absence of leveling agent, good gap fill was achieved for both large and small features as shown in FIGURES 7a and 7b.
  • FIGURE 7c and FIGURE 7d After adding leveling agent, although the bump was reduced (FIGURE 7c and FIGURE 7d), tiny seam voids were observed in small trenches (0.18 ⁇ 4.9: 1AR) in FIGURE 7c. This implies that a degradation in gap- fill was caused by the presence of the leveling agent in the plating solution. Furthermore, the presence of an additional organic leveling agent significantly complicates the additive package, making it difficult for on-line analysis and control of individual components.
  • the present invention provides a process for depositing a metal structure on a surface of a workpiece defining a plurality of recessed microstructures.
  • a surface of the workpiece is exposed to an electroplating bath.
  • the bath includes a source of metal ions to be deposited on the surface, and an organic additive that causes the metal ions to be preferentially deposited within the recessed microstructures relative to the remainder of the surface.
  • Forward electroplating power is supplied between the exposed surface of the workpiece and an anode disposed in electrical contact with the electroplating bath for a first time period, so that the metal ions are deposited on the surface.
  • the electroplating power supplied between the anode and the exposed surface of the workpiece is reversed during at least a portion of a second time period, to control the deposition of future metal ions over the recessed microstructures relative to the surrounding surface.
  • the process is used for electrochemical deposition of copper or other metals into recessed features of substrates used in the manufacture of integrated semiconductor devices.
  • the forward electroplating power is provided during the first time period at a first level, so that the metal ions are deposited to nominally fill the recessed microstructures. Then, during the second time period, the electroplating power is reversed and supplied at a second level to limit the deposition of further metal ions over the filled recessed microstructures relative to the remainder of the surface, ameliorating the development of an overburden of metal over the recessed microstructures.
  • a process for depositing a metal structure on a surface of a workpiece defining a plurality of recessed microstructures.
  • the process entails exposing the surface of the workpiece to an electroplating bath including a source of metal ions to be deposited on the surface, and then supplying forward electroplating power between the exposed surface of the workpiece and an anode disposed in electrical contact with the electroplating bath for a first period of time, and under a first set of plating process parameters, such that metal ions are preferentially deposited within the recessed microstructures relative to the surrounding surface.
  • electroplating power is supplied between the anode and the exposed surface of the workpiece during a second time period in a series of forward power pulses interspersed with reverse power pulses, to control the deposition of further metal ions over the recessed microstructures relative to the remainder ofthe surface.
  • reverse electroplating power is supplied for a sustained third period of time, either before or after the second period of time.
  • the present invention also is directed to the workpieces to which metal structures have been applied in accordance with the processes of the present invention.
  • an electroplating apparatus for applying a metal structure to a surface of a workpiece, the workpiece defining a plurality of recessed microstructures.
  • the apparatus includes a reactor for receiving the surface of the workpiece and exposing the surface to an electroplating bath.
  • the electroplating bath includes a source of metal ions and an organic additive that causes the metal ions to be preferentially deposited within the recessed microstructures relative to the remainder of the surface.
  • the apparatus further includes an anode in electrical contact with the electroplating bath, and a power supply for supplying electroplating power between the surface of the workpiece and the anode to electroplate the metal ions onto the surface.
  • the power supply is capable of supplying both forward and reverse power.
  • a controller is included in the apparatus for controlling the power supply, to supply forward electroplating power for a first time period so that the metal ions are deposited on the surface, and for supplying reverse electroplating power for at least a portion of a second time period to control the deposition of further metal ions over the recessed microstructures relative to the remainder of the surface.
  • the provision of electroplating power can be supplied in a sustained fashion, or in a series of reverse power pulses interspersed with forward power pulses.
  • the present invention thus provides processes and apparatus that enable the use of organic additives or other process conditions for the electrochemical deposition of metal to completely fill recessed micro features in a substrate, while avoiding the development of an overburden of metal above the recessed features relative to the surrounding field area.
  • the present invention results in the substantial amelioration of such undesirable overburden or bumps being formed, and inhibits or substantially reduces post-plating "momentum" buildup of overburden bumps over the recessed features.
  • FIGURES la and lb provide schematic illustrations of the surface of a substrate on which metal has been electrochemically deposited
  • FIGURE 2 illustrates SEM cross-sectional views of four substrates including recessed microfeatures of differing sizes conventionally ECD plated with copper using organic additives, and illustrating the overburden bumps formed;
  • FIGURE 3 provides a series of SEM cross sections of recessed vias illustrating bottom-up plating using ECD copper plating solutions including organic additives;
  • FIGURE 4 provides a series of SEM cross sections illustrating bottom-up plating and bump formation in a series of recessed trenches, using ECD copper plating solutions including organic additives
  • FIGURE 5 provides a graphical representation of the bump heights formed using conventional ECD copper plating solutions including organic additives to fill trenches of various dimensions and pitch;
  • FIGURES 6a and 6b provide schematic representations of the adsorption of organic additives onto a metal layer being deposited on a substrate including a recessed feature;
  • FIGURES 7a through 7d provide FIB cross-sectional views of ECD copper overburden formed over recessed features using conventional ECD copper plating solutions including organic additives, for various feature sizes, in which the plating bath did not include leveling agents (FIGURES 7a and 7b) and the same plating baths that included leveling agents (FIGURES 7c and 7d);
  • FIGURES 8a through 8d illustrate FIB cross-sectional views of the overburden formed over recessed microstructures using reverse current pulsing (Pulsing Schedule PR2, described below) in accordance with a preferred embodiment of the present invention, for features of various sizes and using plating baths and conditions that otherwise correspond to those used to produce the plated substrates illustrated in FIGURE 2;
  • FIGURE 9 provides FIB cross sections illustrating bump formation over recessed features in an ECD copper sulfate bath including organic additives, without the use of reverse power, illustrating the differences in bump formation at the edge (top view) and center (bottom view) of a semiconductor wafer;
  • FIGURE 10 provides a schematic block diagram representation of an apparatus constructed in accordance with the present invention suitable for carrying out the processes in the present invention
  • FIGURE 11 provides a longitudinal cross-sectional view of a plating reactor suitable for use in the apparatus of FIGURE 10;
  • FIGURE 12 provides a graphical representation illustrating bump heights formed as a result of line width and pitch utilizing different plating process parameters in accordance with the present invention
  • FIGURE 13 provides a graphical representation of the average bump height in angstroms relative to different plating process parameters in accordance with the present invention
  • FIGURE 14 provides FIB cross-sectional views of the plating bump formed above recessed features using a base line set of process parameters without current reversal;
  • FIGURES 15, 16, and 17 provide FIB cross-sectional views of the plating bumps formed above recessed features using different reverse plating power parameters in accordance with the present invention
  • FIGURES 18 and 19 provide FIB cross-sectional views of the plating bumps formed over recessed trenches of various dimensions, with each figure illustrating use of a substrate labeled as: PI, corresponding to the baseline conditions illustrated in FIGURE 14; P2, corresponding to the process parameters in accordance with the present invention illustrated in FIGURE 15; and P3, corresponding to the process parameters in accordance with the present invention illustrated in FIGURE 17;
  • PI corresponding to the baseline conditions illustrated in FIGURE 14
  • P2 corresponding to the process parameters in accordance with the present invention illustrated in FIGURE 15
  • P3 corresponding to the process parameters in accordance with the present invention illustrated in FIGURE 17;
  • FIGURE 20 provides a graphical representation of bump height for various trench and pitch dimensions using plating process conditions PI , P2 and P3 as described above for FIGURES 18 and 19; and FIGURES 21, 22. 23, 24, and 25 illustrate FIB cross-sections of plating bumps formed of recessed features in accordance with various process parameters of the present invention.
  • the present invention provides processes and methods for electrochemical deposition of metals onto workpieces including recessed microstructures, using plating baths including organic additives and/or process conditions which result in preferential deposition of the metal within the recessed microstructures relative to the surrounding field surface.
  • the present invention provides methods and apparatus for controlling or limiting the build up of an over-burden bump of deposited metal above the recessed microstructure relative to the metal deposited on the surrounding field area.
  • metals susceptible to processes of the present invention may include copper alloys, e.g., copper zinc, nickel, zinc, and potentially other metals such as chromium, tin, gold, silver, lead, cadmium, platinum, palladium, iridium, ruthenium and various solder compositions, by way of nonlimiting example.
  • the substrates that are plated in the examples of the present invention set forth herein are semiconductor wafers used in the manufacture of integrated chips. Copper is deposited onto a prepared, patterned water as the substrate. Typically, in the case of copper, the substrate will have been prepared by deposition of a barrier layer and then a metallic seed layer. However, other semiconductor substrates that are prepared such that copper will plate the substrate during an electrochemical deposition are also within the present invention. Further, substrates other than semiconductor wafers are also within the present invention, including micromechanical devices that include recessed microfeatures.
  • the metal that is to be plated onto the workpieces in accordance with the present invention is present in a plating solution as the primary species of metal ions to be deposited on the workpiece.
  • Metal ions are deposited under process conditions that preferentially deposit metal ions within the recessed features relative to the surrounding field surface, so as to insure complete fill of the recessed features.
  • Such solutions typically include organic additives that either encourage deposition within the recessed features (i.e., accelerators), or that suppress deposition of metal ions onto the surrounding field surface (i.e., suppressors).
  • the term organic additives is intended to encompass accelerators, also known as brighteners or enhancers; suppressors; and also levelers.
  • Accelerators also referred to herein as accelerator agents, are typically small molecules which are believed to be adsorbed within the interior of recessed features (without being limited by theory), to accelerate the deposition of metal ions locally within the feature.
  • Suitable accelerators for use in the solutions of the present invention include water soluble salts of organic acids including mercapto or thiol functional groups, as well as other compounds that include the chemical structure S-R j -S, wherein Rj is an alkyl or aryl moiety.
  • Such accelerators which are suitable for use in the present invention include those disclosed in U.S. Patent Nos.
  • organic additives also includes suppressor agents, which are typically large molecules that adsorb preferentially to the substrate surface in the field area relative to the recessed features, and that are less adsorbed within the recessed features.
  • suppressors include polyethylene glycols and polyoxyethylene glycols having molecular weights of approximately 3000- 8000. Suitable suppressor agents are commercially available from Shipley Company Inc., Newton, Massachusetts; Enthone-OMI, New Haven, Connecticut; Technic; MacDermit; and Altotech.
  • organic additives as used herein also includes levelers or leveling agents, which are introduced into the plating solution to result in a higher degree of planarization of an electrochemically deposited metal, and in particular are often used in conjunction with suppressors and/or accelerators to counteract to an extent the tendency to build up overburdens over the recessed features.
  • levelers include compounds including the chemical structure N-Rj-S, wherein R j is an alkyl or aryl group, such as are disclosed in U.S. Patent Nos. 5,223,1 18, 4,555.315, 4,376,685, and 3,770,598.
  • suitable levelers for use in the present invention include those disclosed in U.S. Patent No.
  • the present invention provides process plating parameters, also referred to herein as recipes, that are used to either eliminate, limit or control the formation of momentum plating overburden bumps over recessed features during ECD of a metal onto a substrate.
  • the plating process parameters include the application of a reverse plating power between the surface of a substrate that is received within an electroplating bath and an anode that is also in electrical contact with the electroplating bath.
  • reverse power is used to refer to the application of a reverse current, that would have a tendency if continued to strip metal ions from the substrate
  • forward power is used to refer to the application of a forward current between the anode and the substrate to cause metal ions to be deposited from the plating bath and/or anode onto the substrate.
  • the plating recipe includes the application of a net forward plating power during a first time period, at a level which causes the deposition of metal onto the substrate and within the recessed features, with the metal being preferentially deposited within the recessed features due to the presence of organic additives in the electroplating bath.
  • Plating process parameters during this first time period are conventional and well known in the art.
  • forward plating power is suitably applied at a level of 1.0 amps for 30 seconds to deposit approximately 0.035 ⁇ of copper on a 200mm wafer.
  • This application of forward plating power is then followed by application of reverse plating power using a selected waveform, at a level and for a sufficient second period of time so as to limit, and preferentially substantially reduce or eliminate, the formation of an overburden plating bump over the recessed feature.
  • the formation of an overburden plating bump is prevented from forming during subsequent electroplating and after electroplating is complete.
  • the reverse plating power should be applied with a sufficient absolute magnitude of reverse current, for a sufficient period of time, so as to substantially desorb the organic additives from the deposited metal on the substrate. After plating is complete in accordance with the process of the present invention, the phenomenon of continued "momentum" plating or build-up of bumps over the recess features is substantially eliminated.
  • the reverse plating power is supplied during the second time period in a pulsed fashion, including a series of short reverse pulses interspersed with forward reverse pulses.
  • each reverse pulse is preferably greater than or equal to one millisecond, more preferably greater than or equal to 10 milliseconds, and most preferably as 25 milliseconds.
  • the forward pulses that are interspersed between the reverse pulses are preferably equal to or greater than the duration of the reverse pulses, more preferably are greater than reverse pulses, and most preferably are approximately 60 milliseconds or longer in length.
  • the pulsed application of the reverse plating power is carried out with short breaks in application of current in between the reverse and forward pulses.
  • the absolute magnitude of the reverse pulses will vary depending on the ability to desorb the organic additives, but is preferably equal or greater to 0.05 volts.
  • One suitable pulsed reverse power sequence for use during the second time period of the present invention includes the application of (a) forward plating power at 6-12 amps for 50-150 milliseconds, followed by (b) 0-20 milliseconds of off power, followed by (c) 10 to 50 milliseconds of reverse power at 2 to 10 amps, followed by (d) 0- 20 milliseconds of off power.
  • This PRS sequence is repeated multiple times until the total time period desired for application of pulsed reverse power is achieved.
  • the total time period for application of pulsed reverse power is preferably greater than or equal to 10 seconds, more preferably greater than 60 seconds, most preferably at 70-74 seconds.
  • the present invention also encompasses the application of reverse plating power in a sustained fashion for a predetermined second period of time.
  • sustained, steady reverse power is applied in this fashion for greater than or equal to five seconds, most preferably for 10-20 seconds.
  • the absolute magnitude of the sustained reverse power will vary depending on the ability to desorb the organic additives, but preferably is at least 0.05 volts.
  • a sustained reverse power alone to limit the development of momentum plating appears feasible with control of other plating parameters, and is believed to be potentially workable.
  • a pulsed reverse power sequence (such as PRS, for example) be applied during the second time period, either alone, or in conjunction with a sustained reverse power application applied during a third time period either before or after the application of pulsed reverse power.
  • the preferred embodiments of the present application thus utilize initial net forward plating power to initiate deposition and at least partially fill the recessed micro features followed by: (a) the application of pulsed reverse power; (b) the application of net sustained reverse power followed by the application of pulsed reverse power, optionally with the application of forward plating power therebetween; (c) the application of pulsed reverse power followed by the application of sustained reverse power, optionally with the application of forward plating power therebetween; and (d) combinations of the above with single or multiple applications of pulsed reverse power and/or sustained net reverse power.
  • Each period of forward power application may be predominantly forward, with short applications of reverse power application, and visa versa.
  • first time period is used for initial forward plating power application, this may actually include applications of power in multiple time periods at multiple levels. The same alternative arrangements apply for other time periods set forth herein.
  • the application of reverse power may be used alone to ameliorate the effect of organic additives in producing momentum plating, or may be used in conjunction with other techniques known or developed in the future for amelioration of momentum plating bumps.
  • the application of reverse power may be used in conjunction with the incorporation of leveler agents into the plating bath.
  • the process of the present invention is preferably utilized to prevent the development of an overburden bump.
  • net forward plating power is applied to nominally fill the recessed features, and then reverse plating power is applied, preferably in a pulsed fashion, to desorb the organic additives or otherwise prevent the formation of subsequent momentum plating bumps through other mechanisms.
  • the reverse plating power application may be made after an initial forward plating power application which partially fills the recessed features, with additional forward plating power being applied after the application of the reverse plating power to complete the fill of the recessed features.
  • forward plating power is initially applied at a low current level, followed by application of a pulsed reverse plating power sequence, followed by application of forward plating power for a third period of time at a current level which is higher than that applied in the first period of time to complete fill of a recessed features.
  • a pulsed reverse plating power sequence is set forth in Table I.
  • the reference to PR2 is to the following reverse/forward pulse sequences: (a) 9.0 amps forward power for 95 milliseconds, followed by (b) 5 milliseconds of off power, and then (c) 25 milliseconds reversepower at 4.6 amps, followed by (d) 5 milliseconds of off power.
  • the bump reduction recipe by changing the waveform of the PR (pulse reverse) step, the length of the PR step and/or injecting short reverse current steps into the plating recipe.
  • the preferred current pulse reverse step (PR2) used for bump reduction may be improved by either modifying the current levels or the timing.
  • An initial low current step is preferred to maintain good fill, and a final high current DC plating step helps to smooth the surface of the deposited copper, but the invention is not so limited.
  • PR2 pulse reverse step
  • FIGURES 8A-8D illustrate the reduction of momentum plating bumps in accordance with this preferred recipe, using a plating bath and conditions that are otherwise the same as those illustrated in FIGURE 2, for various dimensioned trenches.
  • Table III provides a recipe optimized for electroplating copper from a copper sulfate bath onto a 200mm wafer, to a deposited conformal copper thickness of 1.0 ⁇ m at a plating rate of 3400 AMP/mm. Table III. Alternate Pulse Reverse Recipe
  • the process recipe of Table III has been used by the inventors to yield a wafer having a plating uniformity cross wafer of 3 ⁇ , less than or equal to 6% average, and a wafer to wafer plating uniformity of 3 ⁇ , less than or equal to 3% average. Void free fills were experienced, in gaps of less than or equal to 0.25 ⁇ m depth and, less than or equal to 1.2 ⁇ m depth, with a 4: 1 aspect ratio. The resulting copper film was found to have a specific resistivity of less than or equal to 1.80 ⁇ ohm. cm. Fill impurities were less than or equal to 150 ppms total.
  • This aqueous solution includes a source of metal ions in the form of copper sulfate, an acid in the form of sulfuric acid, and a source of chloride in the form of hydrogen chloride.
  • organic additives are included to ensure fill of recess features, in the form of both suppressors and accelerators. Suppressors added are available from
  • Solutions useful in the present invention include a metal source, which preferably is a source of copper, most preferably copper sulfate.
  • a metal source which preferably is a source of copper, most preferably copper sulfate.
  • other sources of copper are within the scope of the present invention, such as copper gluconate, sodium copper cyanide, copper sulfonate, copper chloride, copper citrate, copper fluoroborate or copper pyrophosphate.
  • sulfuric acid is utilized to yield an acidic bath
  • other acids such as methyl sulfonic acid, fluoroboric acid, pyrophosphate and citric acid are within the scope of the present invention, and the present invention may also be suitably adapted for use with alkaline plating baths such as those disclosed in International PCT Application No. WO 99/47731 (PCT/US99/06306), the disclosure of which is hereby expressly incorporated by reference.
  • chloride sources may be utilized, and other organic additives may be utilized in lieu of the additives present in the above plating bath solution, such as those disclosed herein above, and ethylene diamine tetra acetic acid (EDTA).
  • EDTA ethylene diamine tetra acetic acid
  • the present invention may be suitably carried out in commercially available electroplating apparatus, which are arranged and have controllers that are then modified to be programmed in accordance with the present invention.
  • One suitable electroplating apparatus for use in the present invention is the LT210TM ECD system available from Kalispell. Montana, and as further described in International PCT Application No. WO 98/0291 1 (PCT/US97/12332), the disclosure of which is hereby expressly incorporated by reference.
  • Other commercially available ECD systems such as the EquinoxTM model plating tool, available from Semitool, Inc., are also suitable for use in practicing the present invention.
  • the plating system 40 includes a plurality of plating apparatus or workstations.
  • Workpieces to be plated such as semiconductor wafers, are initially prepared for ECD processing at one or more pre-processing stations 42.
  • preprocessing may entail deposition of a barrier layer (e.g., titanium nitride or tantalum nitride), followed by deposition of a seed layer of metal on the barrier layer, such as by physical vapor deposition or alternately chemical vapor deposition.
  • This seed layer optionally may be an ultra thin seed layer, which is then enhanced at a first ECD station 44, at which additional metal is deposited to provide a conformal seed layer of metal.
  • This enhancement may suitably occur in an alkaline plating bath solution, as disclosed in International Application No. WO 99/47731 (PCT/US99/06306), the disclaimer of which is hereby incorporated by reference.
  • the workpiece with completed seed layer is then passed to a second ECD station 46, in which one or more of the deposition processes of the present invention are carried out.
  • the station 46 includes a reactor, to be described subsequently, in which a surface of the workpiece is received and exposed to a plating bath solution, which is preferably an acidic plating bath solution such as a copper sulfate solution when plating copper, for example. Suitable plating bath solutions are described herein below.
  • Plating power is supplied to the ECD station 46 by a power supply 48 in accordance with the power schedules and recipes described herein above.
  • Power supply 48 may also supply power to other stations, or multiple power supplies may be utilized.
  • This power supply 48 connects electrically between the surface of the workpiece and an anode that is included within the ECD station 46, and that is in contact with the electroplating bath.
  • the power supply 48 is capable of selectively supplying either a forward plating power or a reverse plating power, with both forward and reverse voltage and current control capabilities.
  • the supply of forward and reverse plating power to the reactor within the ECD station 46 is preferentially automatically controlled by a programmable controller 50, which includes a central processing unit that operates in accordance with program code to cause the power supply 48 to supply forward, reverse or no power, at desired levels and for desired time periods in accordance with the present invention.
  • the controller 50 includes a data input device (not shown), such as a keypad, touch screen, other user interface, or a floppy or CD disk drive.
  • the system 40 also includes a rinse station 52, in which the workpiece from the ECD station 46 is received and rinsed.
  • the system may also include further stations (not shown) for additional processing steps, as dictated by the workpiece being plated. Passage of the workpiece through the various stations may be automated through the use of a conveyor system (not shown).
  • the ECD station 46 includes a reactor vessel in which the electroplating bath is held and which receives at least one surface of the workpiece on which the metal is to be deposited.
  • a suitable reactor is disclosed in the aforementioned International Application WO 98/02911.
  • An alternate reactor vessel, also suitable for use in the present invention, is disclosed in International Application WO 00/03067 (PCT/US99/15430), the disclosure of which is hereby expressly incorporated by reference.
  • One suitable reactor constructed in accordance with WO 00/03067 for use in the processing station 46 of the present invention is illustrated in FIGURE 11.
  • the reactor 60 includes a processing head 62 and an electroplating bowl assembly 64.
  • the electroplating bowl assembly 64 includes a cup assembly 70 that is disposed within a reservoir container 72.
  • the cup assembly 70 includes a fluid chamber 72 portion that holds the electroplating bath fluid.
  • the cup assembly also includes a depending annular skirt 74 which extends below the cup bottom 76, and which includes apertures opening therethrough for fluid communication of the plating bath solution, and for release of any gasses that might collect as the chamber of the reservoir assembly is filled with plating solution.
  • the cup is preferentially made from a material that is inert to plating solutions, such as polypropylene.
  • a lower opening in the bottom wall of the cup assembly 70 is connected to a polypropylene (or other material) riser tube 78, which preferably is adjustable in height relative to the cup assembly by a threaded connection.
  • a first end of the riser tube 78 is secured to the rear portion of an anode shield 80, which supports an anode 82.
  • a fluid inlet line 84 is disposed within the riser tube 78. Both the riser tube 78 and the fluid inlet line 84 are secured to the processing bowl assembly 64 by a fitting 86.
  • the fitting 86 can accommodate height adjustment of both the riser tube 78 and the inlet line 84. As such, this connection provides for vertical adjustment of the anode 82 position.
  • the inlet line 84 is preferably made from a conductive material, such as titanium, and is used to conduct electrical current to the anode 82 from the power supply 48, as well as to supply fluid to the cup assembly 70.
  • Electroplating solution is provided to the cup assembly 70 through the fluid inlet line 84 and proceeds therefrom through a plurality of fluid inlet openings 88.
  • the plating solution then fills the chamber 72 through opening 88, as supplied by a plating fluid pump (not shown) or other suitable supply.
  • the upper edge of the cup sidewall 90 forms a weir, which limits the level of electroplating solution within the cup. This level is chosen so that only the bottom surface of a wafer W (or other workpiece) is contacted by the electroplating solution. Excess solution pours over this top edge into an overflow chamber 92.
  • the outflow liquid from the chamber 72 is preferably returned to a suitable reservoir, where it can be treated with additional plating chemicals to adjust the levels ofthe constituents and then recycled to the plating chamber 72.
  • the anode 82 is a consumable anode used in connection with the plating of copper or other metals onto the workpiece.
  • the specific anode may alternatively be an inert anode, with the anode used in reactor 60 varying depending upon the specifics of the plating liquid and process being used.
  • FIGURE 1 1 also employs a diffuser plate 93 that is disposed above the anode 82, providing an even distribution of the flow of fluid across the surface of the wafer W. Fluid passages are provided over all or a portion of the diffuser plate 93, to allow fluid communication therethrough.
  • the height of the diffuser plate within the cup assembly may be adjustable by using a height adjustment mechanism 94.
  • the anode shield 80 is secured to the underside of the anode 82 using anode shield fasteners 96, to prevent direct impingement by the plating solution as the solution passes into the processing chamber 72.
  • the anode shield 80 and anode shield fasteners 96 are preferably made from a dielectric material, such as polyvinylidene fluoride or polypropylene.
  • the anode shield serves to electrically isolate and physically protect the backside ofthe anode.
  • the processing head 62 holds a wafer W (or other workpiece) within the upper region of the processing chamber 72. In a preferred embodiment, the head 62 is constructed to rotate the wafer W within the chamber 72 about on axis R.
  • the processing head 62 includes a rotor assembly 98 having a plurality of wafer engaging contact fingers 100 that hold the wafer against features of the rotor.
  • the fingers 100 are preferably adapted to conduct current between the wafer and the electrical power supply 48.
  • the processing head 62 is supported by a head operator (not shown) that is adjustable to adjust the height of the processing head.
  • the head operator also has a head connection shaft 102 that is operable to pivot about a horizontal pivot axis. Pivotal action of the processing head using the operator allows the processing head to be placed in an open or face-up position (not shown) for loading and unloading of the wafer W.
  • FIGURE 1 1 illustrates the processing head pivoted into a face-down position in preparation for processing. However, this flipping of the wafer is not necessary for carrying out the present invention. D. Other Process Parameters
  • Another method of the present invention for modifying the final surface topography is to modify deposition parameters other than or in addition to current density and waveform; such as plating solution fluid flow, and wafer rotation velocity.
  • these parameters may be adjusted at any time during the deposition process, it is usually preferred to utilize parameters that have been optimized for feature fill capability and electromigration resistance until the small features are filled, then switch to a set of parameters that are optimized for the minimization of these surface features.
  • FIGURE 9 An example of the capability of modifying the surface topography through the use of process parameters while maintaining a consistent bath composition is seen in FIGURE 9.
  • the data represented in this FIGURE were produced by modifying waveform and current density as described above, and fluid flow, using the same copper plating chemistry as used to produce the wafer illustrated in FIGURE 2.
  • the process parameters investigated had a large effect on the surface topography.
  • the electrochemical deposition used in the examples that follow was performed in a Semitool ECD reactor, identical to that on an LT210c copper ECD system for copper interconnect manufacturing, and including a power supply having both forward and reverse voltage and current control. All wafers were 200 mm silicon wafers with trench and via features etched in silicon dioxide, and with barrier and copper seed layers deposited over these features to provide electrical conductivity.
  • the copper plating additives used in this study were commercially available and/or experimental additives available from Enthone-OMI, and Shipley Company. Typical acid copper plating solutions as set forth on Table IV, which contain copper sulfate, sulfuric acid and hydrochloric acid, were used for all the examples.
  • Example I In a first series of experiments performed to investigate the elimination of bump formation, a profilometer was used to measure bump height over several feature sizes and densities that were plated under different conditions, as set forth in Tables V-XIII, referred to as recipes A-I.
  • the pulse reverse waveforms referenced in the tables are defined in Table XIV.
  • the bump heights produced from each of these recipes A-I are summarized in FIGURES 12 and 13.
  • the data in FIGURE 13 represents the bump height averaged over all the different feature sizes with each plating recipe.
  • FIGURE 12 provides the bump height over each specific feature size and pitch.
  • the bump height is expressed in angstroms above the field as measured with a prolifometer.
  • An extended dwell step after the fill step had only a minimal effect (Recipes H and I).
  • PR2 95 msec forward/5 msec off at 9.0 amps 25 msec reverse/5 msec off at 4.6 amps
  • Example II In the second experiment four different recipes were compared using FIB cross sections, and using the same wafers, equipment and chemistry as in Example I. Each recipe is outlined in Tables XV-XVIII, identified as baseline (no reverse current) and Recipes 1-3, respectively. It is noted that Recipe A from Example 1 is the same as Recipe 3 from Example II. The resulting wafers are shown in FIGURES 14, 15. 16. and 17, corresponding to the baseline. Recipe 1 , Recipe 2, and Recipe 3, respectively. In the baseline DC recipe (FIGURE 14) the bumps were much larger than the other recipes (see FIGURES 15-17). The best results were attained with recipe 3 (recipe A). Additional cross sectional views ofthe wafers resulting from this experiment are shown in FIGURES 18 and 19.
  • Wafers labeled as "PI” in these figures correspond to the baseline recipe; wafers labeled as “P2” correspond to Recipe 1; and wafers labeled as "P3” correspond to recipe 3.
  • FIGURE 20 provides bump heights as a function of feature size for these same three recipes.
  • Example III In the third experiment, five additional recipes were compared using FIB cross sections, and using the same wafers, equipment and chemistry as in Example I. Each recipe is outlined in Tables XIX-XXIII, identified as wafers 14- 18, respectively. Images ofthe resulting wafers 14-18 are illustrated in FIGURES 21-25, respectively.

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Abstract

Un procédé pour déposer une structure de métal telle que des interconnexions de cuivre sur une surface d'une pièce telle qu'une tranche de semi-conducteur, la surface de la pièce définissant une pluralité de microstructures en creux. La surface de la pièce est exposée à un bain de galvanoplastie incluant des ions de cuivre à faire déposer sur la surface et un additif organique qui influence les ions de métal devant se déposer de préférence dans les microstructures en creux plutôt que sur reste de la surface. On fait alors passer le courant de galvanoplastie entre la surface exposée de la pièce et l'anode pendant une première période de façon que les ions de cuivre se déposent sur la surface et remplissent nominalement les microstructures en creux. On inverse alors le courant de galvanoplastie entre l'anode et la surface exposée de la pièce pendant au moins une partir d'une seconde période de façon à limiter le dépôt d'autre cuivre sur les structures en creux nominalement remplies, plutôt que sur le reste de la surface, de façon à améliorer le développement d'une surcharge du métal en bosses dans la foulée de l'électrodéposition au-dessus des microstructures en creux. Selon un mode préféré de réalisation, le courant de galvanoplastie inversé est fourni sous forme d'une suite d'impulsions électriques inverses s'intercalant entre des impulsions dans le sens direct. Outre les impulsions en courant inversé, on peut également appliquer un courant en sens inverse pendant une période entretenue. L'invention concerne également un appareil permettant la mise en oeuvre du procédé par utilisation d'un courant inverse de façon à améliorer la formation de bosse de plaquage par inertie.
PCT/US2000/040985 1999-09-24 2000-09-25 Evolution en fonction du trace du profil superficiel en metal de depot electrochimique WO2001021294A2 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10223957A1 (de) * 2002-05-31 2003-12-11 Advanced Micro Devices Inc Ein verbessertes Verfahren zum Elektroplattieren von Kupfer auf einer strukturierten dielektrischen Schicht
WO2006021507A1 (fr) * 2004-08-26 2006-03-02 Siemens Aktiengesellschaft Surface a microstructure diminuant l'adherence et procede de fabrication associe
EP1475463A3 (fr) * 2002-12-20 2006-04-12 Shipley Company, L.L.C. Composition et méthode pour placage électrolytique utilisant de courant pulsé inversé
DE10314502B4 (de) * 2003-03-31 2008-06-12 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum elektrolytischen Beschichten einer Halbleiterstruktur

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770598A (en) * 1972-01-21 1973-11-06 Oxy Metal Finishing Corp Electrodeposition of copper from acid baths
US4396467A (en) * 1980-10-27 1983-08-02 General Electric Company Periodic reverse current pulsing to form uniformly sized feed through conductors
GB8801827D0 (en) * 1988-01-27 1988-02-24 Jct Controls Ltd Improvements in electrochemical processes
US5223118A (en) * 1991-03-08 1993-06-29 Shipley Company Inc. Method for analyzing organic additives in an electroplating bath
US5972192A (en) * 1997-07-23 1999-10-26 Advanced Micro Devices, Inc. Pulse electroplating copper or copper alloys

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10223957A1 (de) * 2002-05-31 2003-12-11 Advanced Micro Devices Inc Ein verbessertes Verfahren zum Elektroplattieren von Kupfer auf einer strukturierten dielektrischen Schicht
DE10223957B4 (de) * 2002-05-31 2006-12-21 Advanced Micro Devices, Inc., Sunnyvale Ein verbessertes Verfahren zum Elektroplattieren von Kupfer auf einer strukturierten dielektrischen Schicht
EP1475463A3 (fr) * 2002-12-20 2006-04-12 Shipley Company, L.L.C. Composition et méthode pour placage électrolytique utilisant de courant pulsé inversé
CN1540040B (zh) * 2002-12-20 2012-04-04 希普雷公司 反向脉冲电镀组合物和方法
DE10314502B4 (de) * 2003-03-31 2008-06-12 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum elektrolytischen Beschichten einer Halbleiterstruktur
WO2006021507A1 (fr) * 2004-08-26 2006-03-02 Siemens Aktiengesellschaft Surface a microstructure diminuant l'adherence et procede de fabrication associe

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