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WO2001011681A1 - Dispositif mosfet comprenant un bouclier de grille-drain evide et procede correspondant - Google Patents

Dispositif mosfet comprenant un bouclier de grille-drain evide et procede correspondant Download PDF

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Publication number
WO2001011681A1
WO2001011681A1 PCT/US1999/018288 US9918288W WO0111681A1 WO 2001011681 A1 WO2001011681 A1 WO 2001011681A1 US 9918288 W US9918288 W US 9918288W WO 0111681 A1 WO0111681 A1 WO 0111681A1
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WO
WIPO (PCT)
Prior art keywords
stress relief
layer
dielectric layer
drain
gate
Prior art date
Application number
PCT/US1999/018288
Other languages
English (en)
Inventor
François HEBERT
Szehim Ng
Original Assignee
Ultrarf, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ultrarf, Inc. filed Critical Ultrarf, Inc.
Priority to PCT/US1999/018288 priority Critical patent/WO2001011681A1/fr
Publication of WO2001011681A1 publication Critical patent/WO2001011681A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates generally to MISFET (MOSFET) devices having source and drain regions connected by a gate-controlled channel, and more particularly the invention relates to a MOSFET device having a reduced drain-gate feedback capacitance provided by a recessed shield between the gate and drain electrodes.
  • MISFET MISFET
  • the MOSFET device has many electrical applications including use as a RF/microwave amplifier.
  • the gate to drain feedback capacitance (Cgd or Crss) must be minimized in order to maximize RF gain and minimize signal distortion.
  • Adler et al. 5,252,848 discloses a MOSFET structure in which a shield is provided over the gate electrode and which terminates over the drain electrode.
  • the shield comprises a polysilicon layer with resistance of 100 ohms/square or less formed over a nitride film over a stress relief oxide formed directly over the gate.
  • the structure is effective, but the fabrication of the device is complex due to the two polysilicon layers which are required.
  • Weitzel U.S. Patent No. 5,119,149 discloses a gallium arsenide MESFET structure in which a shield conductor is placed between the gate and drain electrodes without overlapping the gate. The gate to drain capacitance is not minimized since the metal electrode is placed over the passivation dielectric material for the gate structure.
  • the present invention is directed to a fabrication method and resulting MOSFET device which does not require complex or costly processing and which reduces the gate-drain feedback capacitance without any increase in the input capacitance of the device.
  • a recess is formed on the surface of a MOSFET device between the gate electrode and the drain which is close to the drain surface 5 without shorting to it.
  • a shield electrode is then formed in the recess to enhance the shielding of the feedback capacitance from the drain to the gate.
  • a stress relief dielectric layer is formed over the source region, the gate electrode, and the drain region of a MOSFET device, and then an inter level dielectric is formed over the stress relief o dielectric, the inter level dielectric having a faster etch rate than the stress relief layer.
  • the inter level dielectric is then removed from over a portion of the stress relief layer between the gate electrode and the drain electrode, and a shield electrode is then formed on the exposed portion of the stress relief layer, thereby recessing the shield below the inter level dielectric which overlies the gate electrode.
  • the inter level dielectric and the underlying stress relief dielectric layer are both removed from a surface portion of the drain region, and a passivation dielectric layer is then deposited over the stress relief layer and the exposed surface portion of the drain region.
  • a shield electrode is then formed on the passivation layer over the previously exposed portion of the drain region to o provide a recessed shield electrode between the gate electrode and other drain.
  • a MOSFET device in which a shield electrode is placed between the gate electrode and the drain electrode, but which does not overlap the gate electrode.
  • a selective etch process is used to create a recess 5 for the shield electrode. Since the shield electrode does not overlap the gate or source region, there is no increase in input capacitance of the device.
  • FIG. 1 A- IE are section views illustrating steps in fabricating a MOSFET device having recessed gate-drain shield in accordance with one embodiment of the invention.
  • Figs. 2A and 2B are section views illustrating alternative steps in the process of Figs. 1A-1E.
  • Figs. 3A-3C illustrate steps in fabricating a MOSFET device having a recessed gate-drain shield in accordance with another embodiment of the invention.
  • Figs. 1A- IE are section views illustrating process steps in fabricating a lateral DMOS transistor in accordance with one embodiment of the invention.
  • a semiconductor body includes a P+ substrate 10 and a P- epitaxial layer 12 formed thereon.
  • An N-well 14 is formed in the surface of the epitaxial layer 12, and a P-channel implant 16 is formed in a surface portion of the N-well 14.
  • a gate oxide 18 extends from a field oxide 20 across the surface of the N-well with a gate electrode 22 formed on the surface of gate oxide 18.
  • An optional deep sinker can be formed for a grounded source LDMOS device.
  • the N-well 14 of the drain can be formed before the field oxidation or after field oxidation, but must be formed prior to buried shield plate formation.
  • the gate 22 is preferably an N+ doped polycide structure.
  • Fig. IB a plasma enhanced CVD oxide layer 24, which has a slower etch rate than thermal oxide, is deposited, and then the device is heated for the P-channel diffusion and the PECVD oxide densification.
  • an N+ source/drain mask is provided and the source 26 and drain 28 are then formed by implant of a dopant such as arsenic.
  • a thick inter level dielectric (ILD) 30 is then formed over the plasma enhanced CVD oxide 24.
  • ILD dielectric 30 is typically a doped oxide such as BPSG to allow for reflow of the doped oxide.
  • the device is then heated for a reflow of the doped oxide and the final N+ drive and anneal.
  • a photoresist layer 32 is used to mask the device and then a wet etch or partial dry etch plus wet etch is applied to remove the ILD layer 30 from over dielectric 24 between gate 22 and N+ drain 28.
  • the etch step stops at the plasma enhanced CVD oxide layer 24 which has a slower etch rate than the reflowed BPSG layer 30.
  • a contact mask is used to etch down to the silicon surface, and then a metal deposition and metal mask and etch are used to form the drain-gate shield electrode 34, a source electrode 36, and a drain electrode 38.
  • the shield electrode 34 does not overlap the recess, but is confined to a limited area between gate 22 and drain 28.
  • the stress relief layer 24 over the gate electrode can comprise a low pressure chemical vapor deposited nitride or oxynitride layer.
  • a sandwich structure of low pressure chemical vapor deposit (LPCVD) oxide can be provided under the PECVD oxide as a stress relief layer.
  • the sandwich structure can include the LPCVD oxide under the LPCVD nitride as a stress relief layer.
  • Figs. 2A and 2B are section views illustrating alterative process steps to the method illustrated in Figs. 1 A- IE.
  • the photoreist layer 32 is removed to limit the etched surface area to above the N- well 14 without exposing the stress relief layer 24 above the gate 22.
  • the shield electrode 34 can overlap the recess and the inter layer dielectric 30 for enhanced shielding.
  • Figs. 3A-3C illustrate another embodiment of the invention which entails a modification of the process steps 2A and 2B.
  • layer 24 is removed by etching thereby exposing the surface of the N-well 14.
  • dielectric 40 is deposited over the surface of ILD layer 30 and in the recess over the N- well surface, the dielectric 40 comprising an oxide, oxynitride, or nitride.
  • the thickness of the deposit dielectric 40 can be optimized for a desired gate-drain capacitance.
  • the shield 34 is deposited in the recess etched over the drain region with the shield metal overlapping the recess and with the dielectric thickness between the shield and drain optimized for desired characteristics.
  • the resulting MOSFET structure includes a shield between the gate and drain which does not overlap the gate and thereby minimizing any increase of the input capacitance of the device.
  • the recess which receives the shield can be etched to a depth close to the drain-silicon surface without shorting to further reduce the gate-drain feedback capacitance.
  • the shield can be connected to a bias voltage or to the source electrode 36 in a grounded source MOSFET device. While the invention has been described with reference to specific embodiments in fabricating a lateral DMOS transistor, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications of the process and applications in MOSFET structures will be apparent to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Cette invention se rapporte à un procédé servant à fabriquer un transistor MOSFET et à la structure qui en résulte, laquelle comprend un bouclier de capacitance drain-grille (34) formé dans un évidement entre une électrode de grille (22) et la région de drain (28). Ce bouclier (34) ne recouvre pas la grille (22) et minimise par conséquent l'effet sur la capacitance d'entrée du transistor. Ce procédé de fabrication ne nécessite aucun traitement complexe ou coûteux, dès lors qu'un seul masque supplémentaire non critique est requis avec une attaque sélective destinée à former l'évidement.
PCT/US1999/018288 1999-08-11 1999-08-11 Dispositif mosfet comprenant un bouclier de grille-drain evide et procede correspondant WO2001011681A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1999/018288 WO2001011681A1 (fr) 1999-08-11 1999-08-11 Dispositif mosfet comprenant un bouclier de grille-drain evide et procede correspondant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1999/018288 WO2001011681A1 (fr) 1999-08-11 1999-08-11 Dispositif mosfet comprenant un bouclier de grille-drain evide et procede correspondant

Publications (1)

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WO2001011681A1 true WO2001011681A1 (fr) 2001-02-15

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1717850A1 (fr) * 2005-04-29 2006-11-02 STMicroelectronics S.r.l. Méthode de fabrication d'un transistor de puissance MOS latéral
EP1890336B1 (fr) * 2006-08-18 2011-11-02 austriamicrosystems AG Dispositif à transistor MOS à haute tension et sa méthode de fabrication
CN109065610A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种屏蔽栅器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043790A (en) * 1990-04-05 1991-08-27 Ramtron Corporation Sealed self aligned contacts using two nitrides process
US5162249A (en) * 1989-04-03 1992-11-10 Hyundai Electronics Industries Co., Ltd. Method of making semiconductor memory device having a double stacked capacitor
US5216281A (en) * 1990-04-05 1993-06-01 Ramtron Corporation Self sealed aligned contact incorporating a dopant source
US5821139A (en) * 1996-10-07 1998-10-13 Vanguard International Semiconductor Corporation Method for manufacturing a DRAM with increased electrode surface area

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162249A (en) * 1989-04-03 1992-11-10 Hyundai Electronics Industries Co., Ltd. Method of making semiconductor memory device having a double stacked capacitor
US5043790A (en) * 1990-04-05 1991-08-27 Ramtron Corporation Sealed self aligned contacts using two nitrides process
US5216281A (en) * 1990-04-05 1993-06-01 Ramtron Corporation Self sealed aligned contact incorporating a dopant source
US5821139A (en) * 1996-10-07 1998-10-13 Vanguard International Semiconductor Corporation Method for manufacturing a DRAM with increased electrode surface area

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1717850A1 (fr) * 2005-04-29 2006-11-02 STMicroelectronics S.r.l. Méthode de fabrication d'un transistor de puissance MOS latéral
US7446003B2 (en) 2005-04-29 2008-11-04 Stmicroelectronics S.R.L. Manufacturing process for lateral power MOS transistors
EP1890336B1 (fr) * 2006-08-18 2011-11-02 austriamicrosystems AG Dispositif à transistor MOS à haute tension et sa méthode de fabrication
CN109065610A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种屏蔽栅器件
CN109065610B (zh) * 2018-08-21 2021-07-27 电子科技大学 一种屏蔽栅器件

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