WO2001010067A1

WO2001010067A1 - Frame synchronous acquisition device and method

Info

Publication number: WO2001010067A1
Application number: PCT/JP1999/004150
Authority: WO
Inventors: Yasuyuki Nagashima; Masayuki Doi
Original assignee: Mitsubishi Denki Kabushiki Kaisha
Priority date: 1999-08-02
Filing date: 1999-08-02
Publication date: 2001-02-08

Abstract

A digital radio communication system frame synchronous acquisition device and a method thereof using a TDMA communication system. A sampling unit (2) uses a sampling frequency higher than the symbol frequency of a receiving signal (101) to sample the signal (101) for conversion into a digital signal (102), a correlation calculation unit (4) calculates a correlation value (103) between a signal (102) and a reference pattern (104), a timing detection unit (6) detects the timing deviation value (105) of a maximum correlation value for a reference frame synchronous timing signal (1), a number counter (7) counts the number of detected deviation values (105) according to a deviation value (105), a most frequent value selection unit (8) outputs, when the number of detections of the deviation value (105) has reached a preset number of times, a timing deviation value largest in number as the most frequent timing deviation value (106) which is a timing deviation value for frame synchronous timing and a receiving device cancels this deviation value (106).

Description

Description Frame synchronization acquisition device and frame synchronization acquisition method

The present invention relates to a frame synchronization acquisition device for acquiring a frame synchronization timing in a digital wireless communication system using a time division multiple access (TDMA) communication system in mobile satellite communication, GSM (European Digital Mobile Telephone System) and the like. And the frame synchronization acquisition method. Background art

Conventionally, in a digital wireless communication system using the TDMA communication method, a frame synchronization timing in a received signal is detected, and the reference frame synchronization timing on the receiving side is synchronized with the detected frame synchronization timing (hereinafter, referred to as “ With “frame synchronization”, accurate received data can be obtained. In this case, if the frame synchronization is lost, it is not possible to obtain accurate received data, and it is necessary to synchronize the frame again, so that the acquisition of the received data is delayed, and the use of a limited channel is restricted. However, it also has an adverse effect on the entire communication system and hinders good communication. For this reason, frame synchronization must be as fast, accurate and precise as possible.

That is, in a digital radio communication system, when a communication terminal determines a reception frequency, it receives a broadcast burst at this reception frequency to acquire line information for establishing radio communication. First, it is necessary to synchronize the evening of the broadcast burst. The broadcast burst includes a synchronization code which is a bit sequence having high autocorrelation characteristics, and the timing is captured by detecting the synchronization code. Some wireless communication systems provide a synchronization burst dedicated to synchronization including the synchronization word itself. There is no essential difference in the frame synchronization process in both cases where the synchronization code is included and when the synchronization burst dedicated to synchronization is used.

FIG. 7 is a block diagram showing a configuration of a conventional frame synchronization acquisition device used in a digital radio communication system. In FIG. 7, a sampling section 2 samples a received signal 101 using a sampling clock generated by a sampling clock generating section 3 and converts it into a digital signal 102.

The correlation calculation section 4 calculates a correlation value 103 between the reference pattern 104 held in the reference pattern holding section 5 and the digital signal 102. The timing detection unit 6 detects the timing at which the correlation value 103 has the maximum value, and outputs a deviation from the timing indicated by the reference frame synchronization timing signal 1 as a timing deviation value 105. The receiving device of the digital wireless communication system takes the frame synchronization timing of the received signal 101 by correcting the reference frame synchronization timing signal 1 so as to cancel the timing deviation value 105. As a method of calculating the correlation by the correlation calculating unit 4, for example, a comparison is made between the digitized signal 102 and the reference pattern 104 on a bit-by-bit basis, and the bits that do not match in the bit length of the synchronization code are There is a method in which the synchronization word is detected when the count value does not exceed a predetermined threshold value. Although this correlation calculation method can realize the correlation calculation unit 4 with a simple circuit configuration, bit errors are likely to occur because the synchronization mode length is short or the environment of the wireless communication line is poor. In such a case, detection of erroneous frame synchronization timing is likely to occur, or the synchronization code cannot be detected at the timing when the synchronization code exists.

As another correlation calculation method, there is a correlation calculation method by soft decision. In this case, digital signal 102 is not a bit sequence but a reception level value of reception signal 101 or a complex reception signal. When the soft decision is performed by digital processing, these signals are quantized by a plurality of bits. For example, an 8-bit value is represented by a value with a resolution of 256, and a 9-bit value is represented by a value with a resolution of 512. this These signals are called soft decision data, and the relationship between the soft decision data and the bit sequence is determined by a predetermined mapping rule. For example, if the soft decision data is a positive value, the bit

It becomes “0”, and if the soft decision value is a negative value, it is determined to be bit “1”. Correlation values are sequentially obtained by performing convolution addition of a predetermined determination range to be soft-decided and a reference pattern among the soft-decision data. Then, the determination range having the highest correlation value is determined to be the synchronization mode. In order to reduce the false detection rate of the frame synchronization timing, a threshold value is set. It may be.

As described above, the timing detecting section 6 compares the detection timing of the synchronization mode determined in this way with the reference frame synchronization timing independently held by the receiving device, and calculates a timing deviation. Then, the receiving apparatus corrects the reference frame synchronization timing and cancels the timing deviation so as to synchronize with the reception.

Incidentally, the synchronization word is not always detected at the correct timing, but may be detected at a timing different from the frame synchronization timing of the original received signal. For this reason, in general, when capturing the frame synchronization timing of a received signal, not only the detection result of one synchronization command but also the detection result of a plurality of synchronization commands may be used.

For example, FIG. 8 is a block diagram showing the configuration of a conventional frame synchronization capturing device that detects frame synchronization timing by using the detection results of a plurality of synchronization words (Japanese Patent Laid-Open No. 6-29661). No. 51). In FIG. 8, the A / D converter 202 samples the received signal 101 with the sampling clock in the symbol unit generated by the sampling clock generator 203, and bitizes the received signal i01. Is converted to the sequence 1 1 2.

The synchronization word detecting section 204 calculates a correlation value 113 between the bit sequence 112 and the reference pattern 104 and outputs the correlation value 113 to the timing detecting section 206. Timing detector 2 06 detects the timing at which the correlation value 1 13 shows the maximum value, similarly to the evening timing detection unit 6, and calculates the timing deviation value indicating the deviation from the timing indicated by the reference frame synchronization timing signal 1 with respect to this timing. It accumulates a predetermined number of times, and outputs the timing deviation value with the largest accumulation number as the normal timing deviation value 105.

However, with the frame synchronization acquisition device shown in Fig. 8, the sampling clock is the same as the symbol clock, and the resolution is in units of one bit.Therefore, it is possible to estimate the frame synchronization timing finer than in units of one bit. There was a problem that it was not possible.

For example, in a low-Earth-orbit satellite communication system, the frame synchronization timing fluctuates rapidly, and in such a system, it becomes difficult to quickly capture the frame synchronization timing with a timing estimation with a resolution of about 1 bit. However, smooth frame synchronization cannot be ensured. Therefore, the accuracy of frame synchronization in such a system requires a fine timing estimation of a fraction of a bit length.

Accordingly, the present invention provides a frame synchronization acquisition method that can quickly capture frame synchronization and improve the reliability of frame synchronization even in a wireless communication system in which the frame synchronization timing may fluctuate rapidly. The purpose is to obtain a device and a frame synchronization acquisition method. Disclosure of the invention

A frame synchronization capturing apparatus according to the present invention includes: a sampling unit that samples the reception signal at a sampling frequency having a frequency higher than a symbol frequency of the reception signal; and a reference pattern corresponding to a synchronization code in the reception signal. A reference pattern output unit that outputs a reference signal; a received signal sampled by the sampling unit; A reference means output from the evening output means, a correlation means for calculating a correlation value with the turn, and a reference frame synchronization timing on the receiving side. A timing detecting unit that detects a timing deviation value of a timing at which a correlation value becomes maximum by the correlating unit; and a statistical processing unit that statistically processes and outputs the timing deviation value detected by the timing detecting unit. The frame synchronization timing is captured based on the timing deviation value output from the statistical processing means.

According to the present invention, the sampling means samples the received signal at a sampling frequency having a frequency higher than the symbol frequency of the received signal, and the correlation means outputs the received signal sampled by the sampling means and a reference pattern output. Calculating a correlation value with the reference pattern output from the means, the timing detecting means detects a timing deviation value of a timing at which the correlation value by the correlating means is maximum with respect to a reference frame synchronization timing on the receiving side, The statistical processing means statistically processes and outputs the timing deviation value detected by the timing detecting means, and captures the frame synchronization timing based on the timing deviation value output from the statistical processing means. Erroneous frame synchronization timing The sampling probability is high, and the sampling means is sampling at a sampling frequency that is higher than the symbol frequency of the received signal. As a result, it is possible to capture frame synchronization as fine as a fraction of a bit long, and to quickly and reliably capture frame synchronization even in a propagation environment with large frame synchronization timing fluctuations.

Further, in the frame synchronization capturing apparatus according to the present invention, in the above invention, the statistical processing unit includes a counting unit that counts the number of detection timings in accordance with the timing deviation value detected by the timing detection unit; And a mode selecting means for selecting and outputting a timing deviation value having the highest frequency of detection timing based on the counting result by the counting means.

According to this invention, the counting means counts the number of detection timings corresponding to the timing deviation value detected by the timing detection means, and the mode selection means Based on the counting result by the counting means, the timing deviation value having the highest frequency of detection timing is selected and output, whereby the statistical processing by the statistical processing means is concretely realized, and an erroneous frame is output. The probability of determining the synchronization timing can be kept low, and highly accurate frame synchronization acquisition can be realized.

Further, in the frame synchronization capturing apparatus according to the present invention, in the above invention, the statistical processing means calculates an average value of the timing deviation values detected by the timing detecting means, and statistically processes the average value. It is characterized by having an averaging means for outputting as a timing deviation value.

According to the present invention, the averaging means calculates the average value of the evening deviation detected by the timing detecting means, and outputs the average value as the statistically processed timing deviation. Therefore, the probability of determining the frame synchronization timing can be kept low, and highly accurate frame synchronization acquisition can be realized.

Also, the frame synchronization acquisition method according to the present invention includes a sampling step of sampling the reception signal at a sampling frequency having a frequency higher than a symbol frequency of the reception signal; A correlation step of calculating a correlation value with a reference pattern corresponding to a synchronization code in a received signal; and detecting a timing deviation value of a timing at which a correlation value by the correlation step becomes maximum with respect to a reference frame synchronization timing on the reception side. And a statistical processing step of statistically processing and outputting the timing deviation value detected in the timing detection step, and performing frame synchronization based on the timing deviation value output from the statistical processing step. It is characterized by capturing timing.

According to the present invention, in the sampling step, the reception signal is sampled at a sampling frequency having a frequency higher than the symbol frequency of the reception signal, and in the correlation step, the reception signal sampled in the sampling step is compared with the reception signal. Calculate correlation value with reference pattern corresponding to synchronization code in received signal In the timing detection step, a timing deviation value of a timing at which the correlation value in the correlation step becomes maximum with respect to the reference frame synchronization timing on the receiving side is detected, and the timing deviation value is detected in the statistical processing step in the timing detection step. Since the timing deviation value is statistically processed and output, and the frame synchronization timing is captured based on the timing deviation value output from the statistical processing step, the probability of being determined as an incorrect frame synchronization timing is obtained. This makes it possible to achieve high-accuracy frame synchronization acquisition, and at the sampling step, sampling is performed at a sampling frequency having a frequency higher than the symbol frequency of the received signal. Frame synchronization capture of a fraction of a bit long It becomes possible, even if with a large propagation environment of the frame synchronization timing variations, rapid and reliable frame one 厶同 phase capture becomes possible.

Further, in the frame synchronization capturing method according to the present invention, in the above invention, the statistical processing step includes a counting step of counting the number of detection timings in accordance with the timing deviation value detected in the timing detection step, And a mode selection step for selecting and outputting a timing deviation value with the highest frequency of detection timing based on the counting result of the counting step.

According to the present invention, in the statistical processing step, first, a counting step is performed, and the number of detection timings is counted corresponding to the timing deviation value detected in the timing detecting step. Since the timing deviation value with the highest frequency of detection timing is selected and output based on the counting result of the process, the probability of determining as an incorrect frame synchronization timing can be reduced. A highly accurate frame synchronization acquisition can be realized.

Further, in the frame synchronization acquisition method according to the present invention, in the above invention, in the statistical processing step, an average value of timing deviation values detected in the timing detection step is calculated, and the average value is statistically processed. It is output as a timing deviation value.

According to this invention, the statistical processing step is detected by the timing detecting step. Since the average value of the calculated timing deviation values is calculated and the average value is output as the statistically processed timing deviation value, the probability of determining the frame synchronization timing as an erroneous frame synchronization can be reduced. It is possible to achieve highly accurate frame synchronization acquisition. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a frame synchronization capturing apparatus according to Embodiment 1 of the present invention, and FIG. 2 shows a specific example of an operation of the frame synchronization capturing apparatus shown in FIG. FIG. 3 is a flow chart showing a procedure for generating an evening deviation value for frame synchronization timing in the frame synchronization acquisition apparatus shown in FIG. 1, and FIG. FIG. 5 is a block diagram illustrating a configuration of a frame synchronization capturing apparatus according to Embodiment 2 of the present invention. FIG. 5 is an explanatory diagram illustrating a specific example of the operation of the frame synchronization capturing apparatus illustrated in FIG. FIG. 4 is a flowchart showing a procedure for generating a timing deviation value for frame synchronization timing in the frame synchronization capturing apparatus shown in FIG. 4, and FIG. 7 is a block diagram showing a configuration of a conventional frame synchronization capturing apparatus. A diagram, FIG. 8 is a block diagram showing a configuration of a plurality of synchronization word detection result conventional frame acquisition device for detecting a frame synchronization timing using. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of a frame synchronization capturing apparatus and a frame synchronization capturing method according to the present invention will be described in detail with reference to the accompanying drawings.

First, Embodiment U of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a frame synchronization capturing apparatus according to Embodiment 1 of the present invention.

In FIG. 1, a sampling unit 2 samples a received signal 101 with a sampling clock generated by a sampling clock generating unit 3 and having a clock frequency higher than the symbol clock of the received signal 101. And then mouth The received signal 101 is converted to a digital signal 102. For example, the sampling unit 2 performs sampling using a sampling clock having a frequency four times the symbol clock. The received signal 101 is a baseband signal obtained by subjecting a received signal of a radio frequency received via an antenna (not shown) to predetermined band limitation, amplification, frequency conversion, and the like. The digital signal 102 is separated into an in-phase component and a quadrature component signal obtained by orthogonally transforming the received signal 102.

The correlation calculation unit 4 stores the reference pattern 104 held in the reference pattern holding unit 5 that holds the reference pattern corresponding to the synchronization word in the received signal 101 in advance and the digital signal output from the sampling unit 2. Calculates and outputs the correlation value 103 with 102.

Further, the timing detection unit 6 detects the timing of the maximum correlation value out of the correlation values 103 output from the correlation calculation unit 4, and generates a reference frame synchronization timing signal 1 generated by a receiver (not shown). The timing deviation value 105 between the reference frame synchronization timing shown and the timing of the maximum correlation value is obtained. This timing deviation value 105 is the timing deviation value of the maximum correlation value based on the reference frame synchronization timing.

The number counter 7 counts the number of timing deviation values corresponding to the timing deviation value 105 each time the timing deviation value 105 is output from the timing detection unit 6.

When the number of output times of the timing deviation value 105 becomes a predetermined number, the mode value selection unit 8 sets the timing deviation value 1 having the largest number among the timing deviation values counted in the number count 7. 0 5 is output as the most frequent timing deviation value 106.

Since the timing deviation value 105 from the timing detector 6 is sequentially output at a timing corresponding to the synchronization timing in the frame, the number of frames to be detected must be determined in order to obtain highly accurate frame synchronization timing. If the number should be increased, or if the number of frames used for synchronization acquisition increases, the synchronization acquisition time becomes longer. Therefore, the decision is made in consideration of the effect on the system to which this frame synchronization acquisition device is applied. this The predetermined number of the above-described timing deviation values 105 is determined in accordance with the determined number of frames.

Here, the first embodiment will be specifically described with reference to FIG. In FIG. 2, a synchronization command 22 is inserted into a synchronization burst 21 in a frame of the received signal I01. The correlation calculator 4 calculates a correlation value 103 between the digital signal 102 corresponding to the received signal 101 and the reference pattern 104. Here, correlation value 103 is output as an autocorrelation value using an M-sequence reference pattern having the same pattern as synchronization code 22. Correlation value 103 is the case where large autocorrelation values P 1 and P 2 are output at other times due to the influence of power noise having the largest autocorrelation value P at the detection timing of synchronization word 22. There is. In Fig. 2, the autocorrelation values Pl and P2 show smaller values than the autocorrelation value P. The force autocorrelation values P1 and P2 show larger values than the autocorrelation value P. In this case, the timing at the time of the self-correlation values P 1 and P 2 is detected as the maximum correlation value.

In FIG. 2, when the reference frame synchronization timing signal 1 is used as a reference, the normal timing deviation value 105 corresponding to the synchronization mode 22 is “−3”. On the other hand, the timing deviation value 105 at the time of the autocorrelation value P1 erroneously detected due to the influence of noise or the like is “1 13”, and the timing deviation value 10 at the time of the autocorrelation value P2 is 10 5 is "+5". Here, the timing deviation value when the predetermined number of times is 5, 105 forces, the number counter 7 in the order of “−3”, “1-13”, “−3”, “+5”, “−3” Output from the frequency distribution, since the timing deviation value 105 is the largest number of occurrences when the force is "1-3", the mode selector 8 sets the timing deviation value to "1-3". The value 105 is selected, and the selected timing deviation 105 is output as the average evening deviation 106.

The mode timing deviation value 106 output from the mode selection unit 8 in this manner is subsequently used as information for capturing the frame synchronization timing by the receiving device, and the mode timing deviation value 10 6 By canceling step 6, frame synchronization acquisition with high reliability can be performed. Here, the generation processing of the timing deviation value for the frame synchronization timing in the first embodiment will be described with reference to the flowchart shown in FIG. In FIG. 3, first, the sampling section 2 samples the received signal 101 using a sampling clock having a frequency higher than the symbol clock frequency of the received signal 101, and calculates a correlation as a digital signal 102. Output to section 4 (step S11).

Thereafter, the correlation calculator 4 outputs a correlation value 103 between the input digital signal 102 and the reference pattern 104 to the evening-imaging detector 6 (step S12). After that, the timing detection unit 6 detects the maximum correlation value from the input correlation values 103, and counts the timing deviation value 105 of the maximum correlation value timing with respect to the reference frame synchronization timing to the number counter 7. The number counter 7 counts the number of input timing deviation values 105 in correspondence with each timing deviation value (step S 13).

Thereafter, the mode selection unit 8 determines whether or not the predetermined number of timing deviation values 105 has been input to the number counter 7 (step S 14), and if the predetermined number has not been reached (step S 14). , NO), the process proceeds to step S11 and the above-described processing is repeated. When the number of times reaches a predetermined number (step S14, YES), the number counter 7 The timing deviation value 106 is obtained, and the timing deviation value 106 is output as a timing deviation value for frame synchronization timing (step S15). After that, the process proceeds to step S11, and the above-described processing is performed. repeat. According to the first embodiment, the timing of the maximum correlation value is detected by the timing detection unit 6, and the number of the timing deviation values is counted and counted according to the timing deviation value of the detected timing. Since the timing deviation value having the largest value is output as the timing deviation value for frame synchronization timing, the probability of determination as an incorrect frame synchronization timing can be suppressed to a low level, and high accuracy t and frame synchronization acquisition can be achieved. And the sampling section 2 has a sampling clock frequency having a frequency higher than the symbol clock frequency. Since the received signal 101 is sampled by the wave number, it is possible to capture the frame synchronization as fine as a fraction of a bit length, and even if the fluctuation of the frame synchronization timing has a large propagation environment. Thus, quick and reliable acquisition of frame synchronization becomes possible.

Next, a second embodiment will be described. In the first embodiment, the number count 7 counts the number of timing deviation values 105 corresponding to the timing deviation value 105, and the timing deviation value 105 having the largest count value is used as the frame synchronization timing. In the second embodiment, the average value of the timing deviation values 105 detected by the timing detection unit 6 is obtained, and this average value is used as the frame synchronization timing. It is output as a timing deviation value.

FIG. 4 is a block diagram showing a configuration of a frame synchronization capturing apparatus according to Embodiment 2 of the present invention. The frame synchronization acquisition device shown in FIG. 4 is different from the frame synchronization acquisition device shown in FIG. 1 in that the averaging unit 11 is replaced with the configuration of the counting unit 7 and the mode selection unit 8. The other configuration is the same as the configuration shown in FIG. 1, and the same components are denoted by the same reference numerals.

In FIG. 4, sampling section 2 samples reception signal 101 by a sampling clock generated by sampling clock generation section 3 and having a clock frequency higher than the symbol clock of reception signal 101. Then, the received signal 101, which is an analog signal, is converted into a digitized signal 102.

The correlation calculation unit 4 calculates and outputs a correlation value 103 between the reference pattern 104 corresponding to the synchronization word in the received signal 101 and the digital signal 102 output from the sampling unit 2.

The timing detection unit 6 detects the timing of the largest correlation value out of the correlation values 103 output from the correlation calculation unit 4, and generates a reference frame generated by a receiver (not shown). The timing deviation value 105 between the synchronization timing and the timing of the maximum correlation value is obtained and output to the averaging unit 11. The averaging unit 11 takes the average value of the predetermined number of timing deviation values 105 output from the timing detection unit 6, and uses this average evening deviation value 105 as the timing for frame synchronization timing. Output as the average timing deviation value 107, which is the deviation value.

Since the timing deviation value 105 from the timing detection unit 6 is sequentially output at a timing corresponding to the synchronization mode in the frame, the number of frames to be detected must be large in order to obtain highly accurate frame synchronization timing. However, if the number of frames used for synchronization acquisition increases, the synchronization acquisition time will be prolonged. Therefore, the decision is made in consideration of the effect on the system to which this frame acquisition device is applied. The predetermined number of the timing deviation values 105 described above is determined corresponding to the number of frames determined by this determination.

Here, the second embodiment will be specifically described with reference to FIG. In FIG. 5, a synchronization mode 22 is inserted into a synchronization burst 21 in a frame of the received signal 101. The correlation calculation unit 4 calculates a correlation value 103 between the digital signal 102 corresponding to the received signal 101 and the reference pattern 104. Here, the correlation value 103 is output as an autocorrelation value using an M-sequence reference pattern having the same pattern as the synchronization word 22. Although the correlation value 103 has the largest autocorrelation value P at the time of detection of the synchronization word 22, it outputs large autocorrelation values P 1 and P 2 at other times due to noise and the like. May be. In Fig. 2, the autocorrelation values PI and P2 show a small value compared to the autocorrelation value P.The autocorrelation values P1 and P2 show a large value compared to the autocorrelation value P. In this case, the timing at the self-correlation values P 1 and P 2 is detected as the maximum correlation value.

In FIG. 5, when the reference frame synchronization timing signal 1 is used as a reference, the normal timing deviation value 105 corresponding to the synchronization code 22 becomes “13”. On the other hand, the timing deviation value 105 at the time of the autocorrelation value P1 erroneously detected due to the influence of noise or the like is “1 13”, and the timing deviation value 105 at the time of the autocorrelation value P2 is 105. Becomes “+5”. Here, the averaging unit 1 1 calculates the timing deviation value 1 0 5 is held a predetermined number of times, here n times the timing deviation value 105, and when the nth evening deviation value 105 is input, the averaging value is calculated and this addition averaging is performed. The average timing deviation value 107, which is the timing deviation value, is output as the timing deviation value for frame synchronization evening.

In this case, since the maximum correlation value rarely occurs at the time of the autocorrelation values PI and P2, the timing deviation value almost corresponding to the time of the autocorrelation value P is output as the average timing deviation value 107. . The averaging unit 11 performs the calculated averaging. However, the averaging unit 11 is not limited to this, and may perform other averaging processing such as a square addition average, a geometric mean, and a logarithmic average.

The average timing deviation value 107 output from the averaging unit i 1 in this way is then used as information for capturing the frame synchronization timing by the receiving device, and this mode timing deviation value i 07 By canceling, frame synchronization acquisition with high reliability can be performed.

Here, the generation processing of the timing deviation value for the frame synchronization timing according to the second embodiment will be described with reference to the flowchart shown in FIG. In FIG. 6, first, the sampling unit 2 samples the received signal 101 using a sampling clock having a frequency higher than the symbol clock frequency of the received signal 101, and calculates a correlation as a digital signal 102. Output to section 4 (step S21).

Thereafter, the correlation calculator 4 outputs a correlation value i 03 between the input digital signal 102 and the reference pattern 104 to the timing detector 6 (step S 22). After that, the timing detection unit 6 detects the maximum correlation value from the input correlation values 103 and averages the timing deviation value 105 of the maximum correlation value timing with respect to the reference frame synchronization timing. Then, the averaging unit 11 holds the number and value of the input timing deviation values 105 (step S23).

Thereafter, the averaging unit 11 determines whether or not the input timing deviation value 105 has been input a predetermined number of times (step S24). In step S24, NO), the process proceeds to step S21, and the above processing is repeated. When the predetermined number of times has been reached (step S24, YES), the input timing deviation value 1 After calculating the average value of 0 5, this average value is output as an average timing deviation value 107 which is a timing deviation value for frame synchronization timing (step S 25). The above processing is repeated.

According to the second embodiment, the timing detector 6 detects the timing of the maximum correlation value, calculates the average value of the timing deviation values of the detected timings, and calculates the average value as the frame synchronization timing. Is output as a timing deviation value for use, the probability of determination as an erroneous frame synchronization timing can be suppressed low, and highly accurate frame synchronization acquisition can be realized. Since the received signal i 0 i is sampled at a sampling clock frequency having a higher frequency than the symbol clock frequency, it is possible to capture frame synchronization as fine as a fraction of a bit long, and to obtain frame synchronization timing. Fast and reliable frame synchronization even when the It becomes possible. Industrial applicability

INDUSTRIAL APPLICABILITY The frame synchronization capturing apparatus and the frame synchronization capturing method according to the present invention are useful in the field of digital wireless communication using a time division multiple access (TDMA) communication method in mobile satellite communication, GSM (European Digital Mobile Telephone System) and the like. Yes, even in a wireless communication system in which the frame synchronization timing may fluctuate rapidly, a frame synchronization acquisition apparatus and a frame synchronization acquisition method for quickly acquiring frame synchronization and improving the reliability of frame synchronization Suitable for.

Claims

The scope of the claims

1. sampling means for sampling the reception signal at a sampling frequency having a frequency higher than the symbol frequency of the reception signal;

Reference pattern output means for outputting a reference pattern corresponding to the synchronization code in the received signal,

A correlation unit for calculating a correlation value between the reception signal sampled by the sampling unit and the reference pattern output from the reference pattern output unit; and a maximum correlation value by the correlation unit with respect to a reference frame synchronization timing on the receiving side. Timing detection means for detecting a timing deviation value of the timing to be, statistical processing means for statistically processing and outputting the timing deviation value detected by the timing detection means,

With

A frame synchronization capturing apparatus, wherein frame synchronization timing is captured based on a timing deviation value output from the statistical processing means.

2. The statistical processing means includes:

Counting means for counting the number of detection timings in accordance with the timing deviation value detected by the timing detection means;

Mode selection means for selecting and outputting a timing deviation value with the highest occurrence frequency of the number of detection timings based on the counting result by the counting means,

2. The frame synchronization acquisition device according to claim 1, comprising:

3. The statistical processing means includes an averaging means for calculating an average value of the timing deviation values detected by the timing detection means and outputting the average value as a statistically processed timing deviation value. 3. The frame synchronization acquisition device according to claim 1, wherein

4. A sampling frequency having a higher frequency than the symbol frequency of the received signal (a sampling step for sampling the received signal,

A correlation step of calculating a correlation value between the reception signal sampled in the sampling step and a reference pattern corresponding to a synchronization word in the reception signal; and a correlation value in the correlation step with respect to a reference frame synchronization timing on a receiving side. A timing detection step of detecting an evening deviation value of the timing at which the maximum is obtained;

Including

A frame synchronization capturing method, wherein frame synchronization timing is captured based on the timing deviation value output from the statistical processing step.

5. The statistical processing step includes:

A counting step of counting the number of detection timings corresponding to the timing deviation value detected by the timing detection step,

A mode selection step of selecting and outputting a timing deviation value with the highest occurrence frequency of the number of detection timings based on the counting result in the counting step,

5. The frame synchronization acquisition method according to claim 4, wherein the frame synchronization acquisition method includes:

6. The statistical processing step includes calculating an average value of the timing deviation values detected by the timing detection step, and outputting the average value as a statistically processed timing deviation value. The frame synchronization acquisition method according to item 4.