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WO2001003188A1 - Procede de fixation de circuit integre et dispositif correspondant - Google Patents

Procede de fixation de circuit integre et dispositif correspondant Download PDF

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Publication number
WO2001003188A1
WO2001003188A1 PCT/US1999/022438 US9922438W WO0103188A1 WO 2001003188 A1 WO2001003188 A1 WO 2001003188A1 US 9922438 W US9922438 W US 9922438W WO 0103188 A1 WO0103188 A1 WO 0103188A1
Authority
WO
WIPO (PCT)
Prior art keywords
superstrate
substrate
integrated circuit
radio frequency
retention aperture
Prior art date
Application number
PCT/US1999/022438
Other languages
English (en)
Inventor
Michael John Brady
Dah-Weih Duan
Original Assignee
Intermec Ip Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intermec Ip Corp. filed Critical Intermec Ip Corp.
Priority to AU62705/99A priority Critical patent/AU6270599A/en
Publication of WO2001003188A1 publication Critical patent/WO2001003188A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07786—Antenna details the antenna being of the HF type, such as a dipole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01087—Francium [Fr]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates generally to radio frequency identification (RFID) systems, and more specifically to RFID systems having an improved form factor.
  • RFID radio frequency identification
  • An RFID transponder In the automatic data identification industry, the use of RFID transponders (also known as RFID tags) has grown in prominence as a way to track data regarding an object to which an RFID transponder is affixed.
  • An RFID transponder generally includes a semiconductor memory in which information may be stored.
  • An RFID interrogator containing a transmitter- receiver unit is used to query an RFID transponder that may be at a distance from the interrogator.
  • the RFID transponder detects the interrogating signal and transmits a response signal containing encoded data back to the interrogator.
  • RFID systems are used in applications such as inventory management, security access, personnel identification, factory automation, automotive toll debiting, and vehicle identification, to name just a few.
  • the RFID transponders may have a memory capacity of several kilobytes or more, which is substantially greater than the maximum amount of data that may be contained in a bar code symbol.
  • the RFID transponder memory may be re-written with new or additional data, which would not be possible with a printed bar code symbol.
  • RFID transponders may be readable at a distance without requiring a direct line-of-sight view by the interrogator, unlike bar code symbols that must be within a direct line-of-sight and which may be entirely unreadable if the symbol is obscured or damaged.
  • An additional advantage of RFID systems is that several RFID transponders may be read by the interrogator at one time.
  • an RFID tag or transponder may comprise a semiconductor chip and an antenna mounted to a substrate. This substrate may be enclosed (e.g., encapsulated, laminated, etc.) so that it is protected from the environment. It is known in the art to provide an RFID tag having a thin form factor, such as disclosed in U.S. Patent No. 5,528,222 issued to Moskowitz et al.
  • a prior art RFID tag 100 may include an RF circuit chip 102 which is mounted in a flexible substrate 104. The chip 102 has electrical contacts 112 that are bonded at bond points 114 to an antenna 106 contained on the substrate 104.
  • a window 108 is formed in the substrate 104 allowing the insertion of the chip 102 therein so that the thickness of the substrate 104 is not added to the thickness of the chip 102.
  • the window 108 allows coating of the chip 102 with an encapsulant 110.
  • the encapsulant 110 protects the chip 102 and the associated bonding structure 112, 114 from environmental exposure.
  • the RFID tag 100 is sealed by thin flexible laminations 116 comprising an inner coating of hot melt adhesive 118 (such as ethyl-vinyl- acetate (EVA), phenolic butyral, or silicone adhesive) and an outer coating of tough polymeric material 120 (such as polyester, polyimide, or polyethylene).
  • the antenna 106 (such as a resonant dipole, loop or folded dipole) is integrally formed on the substrate 104.
  • the antenna 106 may comprise thin (e.g., 25 to 35 microns) copper lines which are etched onto a copper/organic laminate substrate or plated onto an organic substrate with a thickness (s).
  • Typical materials used are polyester or polyimide for the organic substrate 104 and electroplated or rolled annealed copper for the antenna 106.
  • the copper may further include gold and nickel plating to facilitate bonding.
  • the chip 102 has a thickness (w), which may range from approximately 174 to 400 microns.
  • semiconductors are manufactured on thick wafers, e.g., up to 1 mm thick. The semiconductor may be made thinner by polishing or back grinding the wafer after manufacture.
  • the substrate 104 has a thickness (v) of approximately 225 microns or less
  • the bonding structure 112, 114 has a thickness (m) of approximately 50 microns
  • the laminating materials 116 have a thickness (u, q) of approximately 50 to 125 microns per side
  • the encapsulate 110 above the antenna 106 and the substrate 104 has a thickness (r) of approximately 50 microns.
  • the total thickness (t) of the prior art RFID tag 100 ranges from approximately 500 to 750 microns.
  • a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon, and a superstrate layer disposed above the substrate layer and having an integrated circuit retention aperture.
  • the superstrate layer is laminated to the substrate layer and substantially covers the electrically conductive material on the substrate layer.
  • An integrated circuit is substantially retained within the integrated circuit retention aperture and is operatively connected to the electrically conductive material.
  • the substrate and superstrate layers may each be comprised of an organic material.
  • the electrically conductive material comprises a metal patterned to provide an antenna.
  • An encapsulant material is disposed within the integrated circuit retention aperture to substantially enclose the integrated circuit therein.
  • a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon and an integrated circuit retention aperture, a first superstrate layer disposed above the substrate layer and also having a integrated circuit retention aperture, and a second superstrate layer disposed below the substrate layer.
  • the integrated circuit retention aperture of the substrate layer is disposed in substantial registration with the integrated circuit retention aperture of the first superstrate layer.
  • the first and second superstrate layers are laminated together to provide a seal around the substrate layer.
  • An integrated circuit is substantially retained within the integrated circuit retention apertures and is operatively connected to the electrically conductive material.
  • An encapsulant is disposed within the integrated circuit apertures substantially enclosing the integrated circuit therein.
  • the substrate layer may be comprised of a glass fabric impregnated with resin, and the superstrate layers may each be comprised of an organic material.
  • a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon and an integrated circuit retention aperture, and a superstrate layer disposed below the substrate layer.
  • the substrate and superstrate layers are laminated together.
  • An integrated circuit is substantially retained within the integrated circuit retention aperture and is operatively connected to the electrically conductive material.
  • An encapsulant is disposed within the integrated circuit aperture substantially enclosing the integrated circuit therein.
  • the conductive material disposed on the substrate layer may be coated with an insulating material, such as a solder mask.
  • the substrate layer may be comprised of a glass fabric impregnated with resin, and the superstrate layer may be comprised of an organic material.
  • FIG. 1 is a cross-sectional side elevational view showing a typical prior art thin RFID tag
  • FIG. 2 is an isometric exploded view of an RFID tag including a perforated substrate according to a first embodiment of the present invention
  • FIG. 3 is a cross-sectional side elevation view of the RFID tag of FIG. 2;
  • FIG. 4 is an isometric exploded view of an RFID tag including a chip- in-cavity structure according to a second embodiment of the present invention
  • FIG. 5 is a cross-sectional side elevational view of the RFID tag of FIG. 4;
  • FIG. 6 is an isometric exploded view of an RFID tag including a chip- in-cavity structure according to a third embodiment of the present invention
  • FIG. 7 is a cross-sectional side elevational view of the RFID tag of
  • FIG. 6 The first figure.
  • FIG. 8 is a highly diagrammatic, isometric view of an exemplary process of the present invention.
  • the present invention satisfies the critical need for an RFID tag having a reduced form factor.
  • the RFID tag 10 includes a substrate 12 and an upper superstrate 18 each comprised of an organic material such as polyimide or polyester.
  • the substrate 12 includes an antenna 14 laminated thereon using a material having sufficiently high electrical conductivity, such as a metallic material comprising copper (Cu) or aluminum (Al).
  • the antenna 14 may be patterned on the substrate 12 utilizing a photolithographic, ion etching, chemical etching, or vapor deposition process.
  • the upper superstrate 18 includes an aperture 20 having a size and shape adapted to accommodate an integrated circuit 16 (described below).
  • the upper superstrate 18 is then laminated on top of the substrate 12.
  • any exposed metallic material may be selectively plated with, for example, electroless nickel (Ni) or gold (Au) in order to provide metallurgy, where needed, to facilitate electrical coupling between the antenna 14 and the integrated circuit 16 using known techniques, such as wire-bonding, tape automated bonding (TAB), or solder reflow.
  • the antenna 14 is comprised of copper (Cu)
  • the copper traces may also be plated before the upper superstrate 18 is applied to the substrate 12.
  • the antenna 14 illustrated in FIG. 2 may be recognized as being a dipole antenna, it should be appreciated that other known types of antenna may be patterned on the substrate 12, such as a loop or folded dipole.
  • the integrated circuit 16 is operatively attached to the antenna 14, such as using bonds 22 (see, for example United States Patent No. 5,528,222, incorporated by reference herein).
  • An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22.
  • the aperture 20 in the upper superstrate 18 is slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 3).
  • the upper superstrate 18 serves as a mask for the substrate 12 in the process of selective plating onto the substrate 12 and/or shaping the encapsulating material 24.
  • the upper superstrate 18 serves to enhance protection of the RFID tag 10 from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24.
  • FIGS. 4 and 5 illustrate an RFID tag 10' having chip-in-cavity (CIC) packaging constructed in accordance with a second embodiment of the present invention.
  • the RFID tag 10' includes a substrate 32 comprised of either a flexible material such as described above, or a less flexible material such as a glass fabric impregnated with a resin (usually epoxy) generally used in the fabrication of printed circuit boards (e.g., FR-4) or ceramic.
  • the substrate 32 includes an antenna 14 laminated thereon in the same manner as described above.
  • An upper superstrate 18 and a lower superstrate 28 are each comprised of organic materials, such as described above.
  • the upper superstrate 18 includes an aperture 20 having a size and shape adapted to accommodate an integrated circuit 16, as also described above.
  • the substrate 32 further includes an aperture 26 similar in shape and orientation as the aperture 20 of the upper superstrate 18, but slightly larger in dimensions.
  • the aperture 26 of the substrate 32 is disposed in substantial alignment with the aperture 20 of the upper superstrate 18.
  • the RFID tag 10' further includes a lower superstrate 28 disposed below the substrate 32.
  • the upper superstrate 18 and lower superstrate 28 are laminated together to hermetically seal the substrate 32 therein.
  • An edge seal 30 is defined around the periphery of the upper and lower superstrates 18, 28 where the superstrate layers come into contact with each other (see FIG. 5).
  • any exposed metallic material may be selectively plated with, for example, electroless nickel (Ni) or gold (Au) in order to provide metallurgy to permit coupling of the antenna 14 with the integrated circuit 16, such as using wire-bonding, tape automated bonding (TAB), or solder reflow techniques.
  • the antenna 14 is comprised of copper (Cu)
  • the copper traces may also be plated before the upper and lower superstrates 18, 28 are applied to the substrate 32.
  • FIG. 4 illustrates the antenna 14 as being a dipole antenna, but it should be appreciated that any known type of antenna may be advantageously utilized.
  • the integrated circuit 16 is placed on the lower superstrate 28 and is operatively attached to the antenna 14, such as using bonds 22.
  • An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22.
  • the apertures 20, 26 are slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 5).
  • the upper superstrate 18 serves as a mask for the substrate 32 in selectively plating onto the substrate and/or shaping the encapsulating material 24.
  • the upper and lower superstrates 18, 28 serve to enhance protection of the RFID tag 10' from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24.
  • FIGS. 6 and 7 illustrate an RFID tag 10" having chip-in-cavity (CIC) packaging constructed in accordance with a third embodiment of the present invention.
  • the RFID tag 10" includes a substrate 32 comprised of either a flexible material such as described above, or a less flexible material such as a glass fabric impregnated with a resin (usually epoxy) generally used in the fabrication of printed circuit boards (e.g., FR-4) or ceramic.
  • the substrate 32 includes an antenna 14 laminated thereon in the same manner as described above.
  • a lower superstrate 28 is comprised of organic materials, such as described above.
  • the substrate 32 includes an aperture 26 having a size and shape adapted to accommodate an integrated circuit 16, as also described above.
  • an upper superstrate is not included in this embodiment.
  • the antenna 14 is coated with an insulating material, such as a solder mask comprised of polymer materials.
  • the substrate 32 and the lower superstrate 28 are then laminated together.
  • Any unmasked metallic material may be selectively plated with electroless nickel (Ni) or gold (Au) in order to provide metallurgy to permit coupling of the antenna 14 with the integrated circuit 16, such as using wire-bonding, tape automated bonding (TAB), or solder reflow techniques.
  • the antenna 14 is comprised of copper (Cu), the copper traces may also be plated.
  • FIG. 6 illustrates the antenna 14 as being a dipole antenna, but it should be appreciated that any known type of antenna may be advantageously utilized.
  • the integrated circuit 16 is placed on the lower superstrate 28 and is operatively attached to the antenna 14, such as using bonds 22.
  • An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22.
  • the aperture 26 is slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 7).
  • the lower superstrate 28 serves to enhance protection of the RFID tag 10" from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24.
  • ESD electrostatic discharge
  • FIGS. 8 illustrates a process for fabricating RFID tags 10' in accordance with the embodiment of the present invention described above with respect to FIGS. 4 and 5.
  • the exemplary process is used to fabricate a reel 40 of finished RFID tags 10', which may be indexed with indexing sprocket holes. For specific applications, such as insertion into labels, such a process is advantageous in a high speed automated processing system.
  • FIGS. 4 and 5 it should be appreciated that a similar process may be used to fabricate RFID tags 10 as illustrated in FIGS. 2 and 3, and RFID tags 10" as illustrated in FIGS. 6 and 7.
  • a similar process can be used to fabricate RFID tags 10, 10', 10" in finished formats other than reels, such as sheets, panels, etc.
  • the upper and lower superstrates 18, 28 and substrate 32 are laminated together to provide a continuous web (such as a 35 mm film strip format or the like), with sprocket holes defined along outer edges of the web.
  • the substrate 32 includes an antenna 14 formed from electrically conductive materials and an aperture 26, and the upper superstrate 18 includes an aperture 20 disposed in substantial alignment with the aperture 26.
  • the lower superstrate 28 may be provided first as a base layer, with the substrate 32 deposited onto the lower superstrate. The antenna 14 may then be patterned onto the exposed substrate 32.
  • the upper superstrate 18 is deposited onto the substrate 32, and the three successive layers are laminated together to form a single web of material.
  • An integrated circuit 16 may then be placed (via suitable automation apparatus 34) within the apertures 20, 26 and electrically connected to the antenna 14.
  • An encapsulant 24 may then be applied (via suitable automation apparatus 36), which flows around the integrated circuit 16.
  • suitable automation apparatus 36 Upon curing of the encapsulant 24, the continuous reel 40 may be segmented into individual RFID tag products.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Details Of Aerials (AREA)

Abstract

L'invention concerne un répondeur RF (10) comprenant un substrat (12) sur lequel est disposé un matériau conducteur, et une couche sus-jacente (18) à ouverture de maintien de circuit intégré. La couche sus-jacente, laminée sur le substrat, couvre sensiblement le matériau conducteur sur le substrat. Un circuit intégré (16), sensiblement maintenu dans l'ouverture susmentionnée, est relié opérationnel au matériau conducteur (16). Le substrat et la couche sus-jacente peuvent être en matériau organique. Le matériau conducteur comprend un matériau en métal structuré pour présenter une antenne (14). Un matériau d'encapsulation est placé dans l'ouverture susmentionnée, entourant sensiblement le circuit intégré. Selon une variante, une couche sus-jacente additionnelle est établie sur un côté opposé du substrat par rapport à la première couche sus-jacente. En outre, le substrat comprend une seconde ouverture de maintien de circuit intégré, et le circuit intégré est maintenu dans les deux ouvertures considérées. Selon une autre variante, le substrat est laminé sur le côté opposé du substrat seulement, et l'ouverture susmentionnée est pratiquée dans le substrat. Dans chacune de ces variantes, on est en présence d'un boîtier à puce en cavité dont le facteur de forme est relativement peu important.
PCT/US1999/022438 1999-07-01 1999-09-28 Procede de fixation de circuit integre et dispositif correspondant WO2001003188A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU62705/99A AU6270599A (en) 1999-07-01 1999-09-28 Integrated circuit attachment process and apparatus

Applications Claiming Priority (2)

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US34588699A 1999-07-01 1999-07-01
US09/345,886 1999-07-01

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003023705A1 (fr) * 2001-09-13 2003-03-20 Alcoa Closure Systems International, Inc. Procede de fabrication d'un systeme de fermeture contenant des informations interactives
FR2832588A1 (fr) * 2001-11-20 2003-05-23 Gemplus Card Int Ruban conducteur lamine de raccordement a une interface d'entrees/sorties
US6782601B2 (en) 2001-09-13 2004-08-31 Alcoa Closure Systems International Method of making interactive information closure
FR2853115A1 (fr) * 2003-03-28 2004-10-01 A S K Procede de fabrication d'antenne de carte a puce sur un support thermoplastique et carte a puce obtenue par ledit procede
EP1522950A3 (fr) * 2003-10-08 2005-06-01 Toshiba Tec Kabushiki Kaisha Module d'étiquette à radiofréquence, article avec un module d'étiquette à radiofréquence et lecteur correspondant
FR2869707A1 (fr) * 2004-04-29 2005-11-04 Henri Havot Antenne et etiquette electronique comprenant ladite antenne
WO2006084984A1 (fr) * 2005-02-11 2006-08-17 Smart Packaging Solutions (Sps) Procede de fabrication d’un dispositif micro-electronique a fonctionnement sans contact, notamment pour passeport electronique
WO2007001442A3 (fr) * 2004-11-23 2007-05-18 Alien Technology Corp Protection de dispositifs d'identification par radiofrequence contre les decharges statiques
EP1814067A1 (fr) * 2006-01-31 2007-08-01 Fujitsu Limited Procédé de bobinage d'une série d'étiquettes RFID et rouleau d'étiquettes RFID
EP1830311A3 (fr) * 2006-03-01 2008-10-22 Nippon Sheet Glass Co., Ltd. Étiquette IC
WO2012136905A1 (fr) * 2011-04-05 2012-10-11 Smart Packaging Solutions (Sps) Procédé de fabrication d'inserts pour passeport électronique

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EP0595549A2 (fr) * 1992-10-26 1994-05-04 Hughes Microelectronics Europa Limited Etiquette-adresse à radiofréquence
WO1994018700A1 (fr) * 1993-02-11 1994-08-18 Indala Corporation Procede de production d'un repeteur de frequences radioelectriques a boitier moule etanche a l'environnement
US5528222A (en) * 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
DE19648308A1 (de) * 1995-11-21 1997-05-22 Murata Manufacturing Co Funkkommunikationsmodul
FR2745119A1 (fr) * 1996-02-16 1997-08-22 Thomson Csf Boitier d'encapsulation de circuit integre pour applications hyperfrequences et son procede de fabrication

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Publication number Priority date Publication date Assignee Title
EP0595549A2 (fr) * 1992-10-26 1994-05-04 Hughes Microelectronics Europa Limited Etiquette-adresse à radiofréquence
WO1994018700A1 (fr) * 1993-02-11 1994-08-18 Indala Corporation Procede de production d'un repeteur de frequences radioelectriques a boitier moule etanche a l'environnement
US5528222A (en) * 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
DE19648308A1 (de) * 1995-11-21 1997-05-22 Murata Manufacturing Co Funkkommunikationsmodul
FR2745119A1 (fr) * 1996-02-16 1997-08-22 Thomson Csf Boitier d'encapsulation de circuit integre pour applications hyperfrequences et son procede de fabrication

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6782601B2 (en) 2001-09-13 2004-08-31 Alcoa Closure Systems International Method of making interactive information closure
WO2003023705A1 (fr) * 2001-09-13 2003-03-20 Alcoa Closure Systems International, Inc. Procede de fabrication d'un systeme de fermeture contenant des informations interactives
FR2832588A1 (fr) * 2001-11-20 2003-05-23 Gemplus Card Int Ruban conducteur lamine de raccordement a une interface d'entrees/sorties
US7597266B2 (en) 2003-03-28 2009-10-06 Ask S.A. Method for making a smart card antenna on a thermoplastic support and resulting smartcard
FR2853115A1 (fr) * 2003-03-28 2004-10-01 A S K Procede de fabrication d'antenne de carte a puce sur un support thermoplastique et carte a puce obtenue par ledit procede
WO2004088582A3 (fr) * 2003-03-28 2005-05-19 Ask Sa Procede de fabrication d’antenne de carte a puce sur un support thermoplastique et carte a puce ainsi obtenue
KR101033013B1 (ko) * 2003-03-28 2011-05-09 애스크 에스에이 열가소성 물질 지지부 및 그 결과로 발생하는스마트카드상에 스마트카드 안테나를 만드는 방법
CN1768349B (zh) * 2003-03-28 2010-04-28 Ask股份有限公司 用来制造在热塑性支撑件上的智能卡天线的方法和生成的智能卡
EP1522950A3 (fr) * 2003-10-08 2005-06-01 Toshiba Tec Kabushiki Kaisha Module d'étiquette à radiofréquence, article avec un module d'étiquette à radiofréquence et lecteur correspondant
FR2869707A1 (fr) * 2004-04-29 2005-11-04 Henri Havot Antenne et etiquette electronique comprenant ladite antenne
WO2007001442A3 (fr) * 2004-11-23 2007-05-18 Alien Technology Corp Protection de dispositifs d'identification par radiofrequence contre les decharges statiques
US7342490B2 (en) 2004-11-23 2008-03-11 Alien Technology Corporation Radio frequency identification static discharge protection
FR2882174A1 (fr) * 2005-02-11 2006-08-18 Smart Packaging Solutions Sps Procede de fabrication d'un dispositif microelectronique a fonctionnement sans contact notamment pour passeport electronique
WO2006084984A1 (fr) * 2005-02-11 2006-08-17 Smart Packaging Solutions (Sps) Procede de fabrication d’un dispositif micro-electronique a fonctionnement sans contact, notamment pour passeport electronique
US7992790B2 (en) 2005-02-11 2011-08-09 Smart Packaging Solutions (Sps) Method of producing a contactless microelectronic device, such as for an electronic passport
EP1814067A1 (fr) * 2006-01-31 2007-08-01 Fujitsu Limited Procédé de bobinage d'une série d'étiquettes RFID et rouleau d'étiquettes RFID
EP1830311A3 (fr) * 2006-03-01 2008-10-22 Nippon Sheet Glass Co., Ltd. Étiquette IC
WO2012136905A1 (fr) * 2011-04-05 2012-10-11 Smart Packaging Solutions (Sps) Procédé de fabrication d'inserts pour passeport électronique
FR2973915A1 (fr) * 2011-04-05 2012-10-12 Smart Packaging Solutions Sps Procede de fabrication d'inserts pour passeport electronique
US9256821B2 (en) 2011-04-05 2016-02-09 Smart Packaging Solutions (Sps) Method for manufacturing inserts for electronic passports

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