+

WO2001093499A1 - Fonction d'autotest non intrusive dans le niveau 2 d'utopie du bus - Google Patents

Fonction d'autotest non intrusive dans le niveau 2 d'utopie du bus Download PDF

Info

Publication number
WO2001093499A1
WO2001093499A1 PCT/IB2001/000950 IB0100950W WO0193499A1 WO 2001093499 A1 WO2001093499 A1 WO 2001093499A1 IB 0100950 W IB0100950 W IB 0100950W WO 0193499 A1 WO0193499 A1 WO 0193499A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
atm
bus
self test
layer
Prior art date
Application number
PCT/IB2001/000950
Other languages
English (en)
Other versions
WO2001093499A8 (fr
Inventor
Jacob Fainguelernt
Original Assignee
Adc Telecommunications Israel Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Adc Telecommunications Israel Ltd. filed Critical Adc Telecommunications Israel Ltd.
Priority to AU2001260529A priority Critical patent/AU2001260529A1/en
Publication of WO2001093499A1 publication Critical patent/WO2001093499A1/fr
Publication of WO2001093499A8 publication Critical patent/WO2001093499A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5628—Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Definitions

  • the present invention relates generally to the field of telecommunications and, in particular, to systems and methods for non intrusive self test capability in the UTOPIA level Two bus.
  • Asynchronous Transfer Mode is the transfer mode of choice for broadband integrated services digital networks (B-ISDN).
  • B-ISDNs are envisioned to be the communication framework for integrating multiple services as video, audio and data.
  • each one of the services is delivered over a dedicated network and its infrastructure.
  • the use of ATM enables these services to be integrated in a single unified network deployed over the existing infrastructures.
  • the ATM technology is based on transferring the various kinds of data in small packets of a fixed size, called cells. The small, constant cell size allows ATM equipment to transmit video, audio, and computer data over the same network, and assure that no single type of data hogs the line. ATM switches and multiplexers are necessary for routing the cells to their appropriate destination.
  • FIG. 1 shows the general architecture of an ATM switch/multiplexer 100.
  • This kind of equipment is composed of two basic types of functional blocks; the ATM common module 101 and the physical ports 103-1, 103-2, . . ., 103-N.
  • the ATM common module 101 routes cells between the various physical ports, and performs signaling functions.
  • the physical ports 103-1, 103-2, . . ., 103-N convert signals from the physical layer into ATM cells and vice-versa.
  • Ports 103-1, 103-2, . . ., 103-N perform functions of the ATM physical layer (PHY), and the ATM common module 101 performs functions of the ATM layer and the ATM signaling adaptation layer (SAAL).
  • a standard bus 202 defined by the ATM Forum as the
  • UTOPIA Universal Test & Physical Operations Interface for ATM
  • UTOPIA level 2 version enables a "multi-physical" configuration where a single ATM layer device 201 (UTOPIA master) can be connected through this bus 202 to multiple physical layer devices 203-1, 203-2, . . ., 203-N (UTOPIA slaves).
  • Prior art Figure 3 illustrates an ATM system 300 in which the ATM and
  • SAAL functionality is implemented in a common pack 301 that is connected to multiple interface packs 303-1, 303-2, . . ., 303-N, each one having the physical layer functionality.
  • the data from the common pack to the interface packs and vice- versa, is transported through the system backplane.
  • the UTOPIA level 2 bus cannot be implemented in a backplane.
  • the UTOPIA bus in the common pack 302, and the UTOPIA buses in the interface packs, shown generally as 305 are interconnected through special drivers (in both packs), e.g. Driver 1, Driver 2, . . ., Driver N..
  • UTOPIA level 2 bus supports an embedded parity check, which is not sufficient for and end to end internal system self-test.
  • This test demands, instead, the implementation of internal loops.
  • the straightforward implementation of a loopback consists on operating one of the physical ports in a loopback mode. This implementation is intrusive since during the test the port is halted. In other words, the port being tested has to be taken out of service while the self test is perfo ⁇ ned.
  • an ATM switch/multiplexer system for non-intrusive self-test capability in a UTOPIA level 2 bus includes an ATM layer device.
  • a number of physical layer devices are included.
  • a bus couples the ATM layer device to the number of physical layer devices.
  • a dedicated self test circuit couples to the bus.
  • the dedicated self test circuit is adapted to loop back cells from the ATM layer device in a self test function. That is the self test circuit is adapted to send received ATM cells back to the ATM layer device, through a dedicated virtual circuit, in order to perform a self test function without requiring additional wires or bandwidth.
  • the ATM layer device includes a UTOPIA master and the physical layer devices are UTOPIA slaves.
  • the number of physical layer devices include physical ports adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer.
  • the dedicated self test circuit has a lower priority between the ATM device layer number of physical devices in order to perform a non intrusive self test function.
  • Figure 1 is a block diagram that illustrates a conventional ATM switch/multiplexer circuit.
  • Figure 2 is another representation of a conventional ATM switch/multiplexer circuit.
  • Figure 3 is another representation of a conventional ATM switch/multiplexer circuit.
  • FIG. 4 is a block circuit diagram that illustrates an embodiment of an ATM switch/multiplexer system for non-intrusive self-test capability in a UTOPIA level 2 bus according to the teachings of the present invention.
  • Figure 5 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system according to the teachings of the present invention.
  • Figure 6 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system according to the teachings of the present invention.
  • FIG 4 is a block circuit diagram that illustrates an ATM switch/multiplexer system 400 for non-intrusive self-test capability in a UTOPIA level 2 bus, according to the teachings of the present invention.
  • the ATM switch/multiplexer system includes an ATM layer device 401.
  • a number of physical layer devices 403-1, 403-2, . . ., 403-N are included.
  • a bus 402 couples the ATM layer device 401 to the number of physical layer devices 403-1, 403-2, . . ., 403-N.
  • the bus 402 includes a UTOPIA level 2 bus 402.
  • a dedicated self test circuit 405 is coupled to the bus 402.
  • the dedicated self test circuit 405 includes external logic either in the form of a programmable device or discrete components which is coupled to the bus 402. Self test circuit 405 communicates with the ATM layer device 401 over a dedicated virtual connection.
  • the ATM layer device 401 includes a UTOPIA master and the number of physical layer devices 403-1, 403-2, . . ., 403-N are UTOPIA slaves.
  • the UTOPIA master is adapted to perform ATM and ATM signaling adaptation layer (SAAL) functions.
  • SAAL ATM signaling adaptation layer
  • the ATM layer device 401 and the number of physical layer devices 403-1, 403-2, . . ., 403-N are located in a single circuit pack. The number of physical layer devices 403-1, 403-2, .
  • the ATM layer device 401 includes a common module or pack adapted for routing ATM cells between the number of physical layer devices.
  • system 400 provides a non-intrusive self-test functionality.
  • the dedicated virtual connection 405 is adapted to send received ATM cells back to the ATM layer device 401 in order to perform a self test function. If the ATM cells returned to the ATM layer device 401 do not match those which were sent out or the cells are not received, the ATM layer device 401 recognizes that there is a problem with system 400.
  • the self test circuit 405 actually imitates a given physical layer device address 403-1, 403-2, . . ., 403-N.
  • the diagnostics of the self test function are performed in the ATM layer device 401.
  • the dedicated self test circuit 405 through its dedicated virtual connection has a lower priority between the common pack and the number of physical devices in order to perform a non intrusive self test function without requiring additional wires or bandwidth.
  • FIG. 5 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system 500, according to the teachings of the present invention.
  • the ATM switch/multiplexer system 500 similarly provides for non- intrusive self-test capability in a Utopia level 2 bus.
  • the system 500 includes an ATM layer device 501, or common layer circuit pack 501, and a number of interface layer circuit packs 503-1, 503-2, . . ., 503-N.
  • the common layer circuit pack 501 includes an internal bus 502.
  • the internal bus 502 includes a UTOPIA level 2 bus.
  • each port has includes an internal bus, shown generally as 505, coupling between a driver, 511-1, 511-2, . . ., 511-N, and a physical layer device, e.g. 507-1, 507-2, . . ., 507-N.
  • the bus includes a UTOPIA level 2 bus 505.
  • each of the number of ports, Port #1, Port #2, . . ., Port #N includes a dedicated self test circuit 509-1, 509-2, . . ., 509-N.
  • a number of drivers 511-1, 511-2, . . ., 511-N interconnect, or couple, the buses 505 in the number of ports, Port #1 , Port #2, . . ., Port #N, to the bus 502 in the ATM layer device 501, or common layer circuit pack 501.
  • Each dedicated self test circuit 509- 1, 509-2, . . ., 509-N communicates with common layer circuit pack 501 over a dedicated virtual connection.
  • the common layer circuit pack is adapted to perform the functions of the ATM layer and the SAAL.
  • each dedicated self test circuit 509-1, 509-2, . . ., 509-N includes a programmable device.
  • the number of physical ports, Port #1, Port #2, . . ., Port #N, including the number of physical layer devices are adapted for converting signals from the physical layer devices, e.g. 507-1, 507-2, . . ., 507 -N, into ATM cells and converting ATM cells into signals for the physical layer devices 507-1, 507-2, . . ., 507-N.
  • each dedicated self test circuit 509-1, 509-2, . . ., 509-N coupled to the bus 505 in the number of interface layer circuit packs 503-1, 503-2, . . ., 503-N is generic and independent from a functionality for the number of drivers 511-1, 511-2, . . ., 511-N.
  • each dedicated virtual connection 509-1, 509-2, . . ., 509-N is adapted to send received ATM cells back to the common layer circuit pack 501 in order to perform a self test function without requiring additional wires or bandwidth.
  • system 500 provides a non-intrusive self-test functionality.
  • Each dedicated self-test circuit 509-1, 509-2, . . ., 509- ⁇ through its dedicated virtual connection has a lower priority between the common layer circuit pack 501 and the physical devices 507-1, 507-2, . . ., 507-N in the number of ports Port #1, Port #2, . . ., Port #N in order to perform a non intrusive self test function.
  • Figure 6 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system 600, according to the teachings of the present invention.
  • the ATM switch/multiplexer system embodiment 600 shown in Figure 6, similarly provides for non-intrusive self-test capability in a Utopia level 2 bus.
  • Port #N includes programmable device such as an Application Specific Integrated Circuit (ASIC) or a field programmable gate array (FPGA).
  • ASIC Application Specific Integrated Circuit
  • FPGA field programmable gate array
  • the physical layer devices 607-1, 607-2, . . ., 607 -N are included as part of the ASIC or the FPGA.
  • each dedicated self test circuit 609-1, 609-2, . . ., 609-N is a functional block of the ASIC or FPGA.
  • each dedicated self test circuit 609-1, 609-2, . . ., 609-N is coupled to the internal bus 605 within the ASIC or FPGA to perform the self test function in conjunction with ATM layer device 601.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne des systèmes et des procédés pour assurer une fonction d'autotest non intrusive au niveau 2 d'UTOPIE du bus dans le cadre de l'architecture multiplexeur/sélecteur MTA. Ces systèmes et ces procédés utilisent les caractéristiques du mode de transport MTA et de l'interface du bus de niveau 2 d'UTOPIE. Ce système comporte une architecture multiplexeur/sélecteur MTA qui contient un dispositif à couche MTA et un certain nombre de dispositifs à couches physiques. Un bus couple ce dispositif à couche MTA aux dispositifs à couches physiques. Un circuit d'autotest est couplé au bus qui peut renvoyer les cellules MTA reçues au bloc de circuits à couche commune et ce, afin de réaliser une fonction d'autotest sans que des fils supplémentaires ou une bande passante soient nécessaires.
PCT/IB2001/000950 2000-05-31 2001-05-30 Fonction d'autotest non intrusive dans le niveau 2 d'utopie du bus WO2001093499A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001260529A AU2001260529A1 (en) 2000-05-31 2001-05-30 Non intrusive self test capability in the utopia level two bus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58457700A 2000-05-31 2000-05-31
US09/584,577 2000-05-31

Publications (2)

Publication Number Publication Date
WO2001093499A1 true WO2001093499A1 (fr) 2001-12-06
WO2001093499A8 WO2001093499A8 (fr) 2002-02-28

Family

ID=24337922

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2001/000950 WO2001093499A1 (fr) 2000-05-31 2001-05-30 Fonction d'autotest non intrusive dans le niveau 2 d'utopie du bus

Country Status (2)

Country Link
AU (1) AU2001260529A1 (fr)
WO (1) WO2001093499A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6957369B2 (en) 2002-05-30 2005-10-18 Corrigent Systems Ltd. Hidden failure detection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0772369A2 (fr) * 1995-11-06 1997-05-07 Sun Microsystems, Inc. Partitionnement de bloc d'interface de cellules pour outil de segmentation et de réassemblage
US5802073A (en) * 1994-09-23 1998-09-01 Vlsi Technology, Inc. Built-in self test functional system block for UTOPIA interface
WO1999037117A1 (fr) * 1998-01-20 1999-07-22 Telefonaktiebolaget Lm Ericsson (Publ) Circuit multi-service de telecommunication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802073A (en) * 1994-09-23 1998-09-01 Vlsi Technology, Inc. Built-in self test functional system block for UTOPIA interface
EP0772369A2 (fr) * 1995-11-06 1997-05-07 Sun Microsystems, Inc. Partitionnement de bloc d'interface de cellules pour outil de segmentation et de réassemblage
WO1999037117A1 (fr) * 1998-01-20 1999-07-22 Telefonaktiebolaget Lm Ericsson (Publ) Circuit multi-service de telecommunication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6957369B2 (en) 2002-05-30 2005-10-18 Corrigent Systems Ltd. Hidden failure detection

Also Published As

Publication number Publication date
AU2001260529A1 (en) 2001-12-11
WO2001093499A8 (fr) 2002-02-28

Similar Documents

Publication Publication Date Title
US5970072A (en) System and apparatus for telecommunications bus control
EP1045557B1 (fr) Système de commutation ATM
US6229822B1 (en) Communications system for receiving and transmitting data cells
EP0858240B1 (fr) Dispositif de composition et multiplexage de cellules, et dispositif de démultiplexage
US5457678A (en) Method and circuit arrangement for the transmission of message packets according to the asynchronous transfer mode in a communication network
US20020009089A1 (en) Method and apparatus for establishing frame synchronization in a communication system using an UTOPIA-LVDS bridge
JPH09508778A (ja) 電気通信信号を簡素化するためのグルーミング装置
JP3516490B2 (ja) 回線インタフェース装置
JPH05507605A (ja) Ａｔｍスイッチ用コネクションレス交換方法
US20020031141A1 (en) Method of detecting back pressure in a communication system using an utopia-LVDS bridge
US6175567B1 (en) Method and system for multiplexing/demultiplexing asynchronous transfer mode interprocessor communication (ATM IPC) cell in exchange
US6931022B1 (en) Background test system for time division multiplexing switching systems
US6044088A (en) System and circuit for telecommunications data conversion
US20020031132A1 (en) UTOPIA-LVDS bridge
WO2001093499A1 (fr) Fonction d'autotest non intrusive dans le niveau 2 d'utopie du bus
US6700872B1 (en) Method and system for testing a utopia network element
US6070213A (en) Telecommunications terminal
WO2001084784A2 (fr) Systeme de tampon mta
Cisco Network Interface (Trunk) Cards
Cisco Network Interface (Trunk) Cards
US20020031133A1 (en) Embedded communication protocol using a UTOPIA-LVDS bridge
JP2002506587A (ja) Ａｔｍノードにおける信号メッセージの処理
KR100284004B1 (ko) 수요밀집형 광가입자 전송장치에 있어서의 호스트 디지털 터미널
US6252875B1 (en) Multi-cast ABR service system and method
KR100237403B1 (ko) Atm 교환기 ds1e 가입자 정합장치

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: C1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: C1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

CFP Corrected version of a pamphlet front page
CR1 Correction of entry in section i
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载