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WO2001084553A3 - Three-dimensional memory array and method of fabrication - Google Patents

Three-dimensional memory array and method of fabrication Download PDF

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Publication number
WO2001084553A3
WO2001084553A3 PCT/US2001/013575 US0113575W WO0184553A3 WO 2001084553 A3 WO2001084553 A3 WO 2001084553A3 US 0113575 W US0113575 W US 0113575W WO 0184553 A3 WO0184553 A3 WO 0184553A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory array
rail
fabrication
dimensional memory
stack
Prior art date
Application number
PCT/US2001/013575
Other languages
French (fr)
Other versions
WO2001084553A2 (en
Inventor
N Johan Knall
Mark Johnson
Original Assignee
Matrix Semiconductor Inc
N Johan Knall
Mark Johnson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/814,727 external-priority patent/US6420215B1/en
Application filed by Matrix Semiconductor Inc, N Johan Knall, Mark Johnson filed Critical Matrix Semiconductor Inc
Priority to EP01937191A priority Critical patent/EP1284017A4/en
Priority to AU2001262953A priority patent/AU2001262953A1/en
Publication of WO2001084553A2 publication Critical patent/WO2001084553A2/en
Publication of WO2001084553A3 publication Critical patent/WO2001084553A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment

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  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include conductor (40) and semiconductor layers (38, 39 and 41). The layers are generally separated by an insulating layer used to form antifuses (42). In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack. Methods for fabricating a multi-level memory array are also provided.
PCT/US2001/013575 2000-04-28 2001-04-25 Three-dimensional memory array and method of fabrication WO2001084553A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01937191A EP1284017A4 (en) 2000-04-28 2001-04-25 THREE DIMENSIONAL MEMORY MATRIX AND METHOD OF MANUFACTURE
AU2001262953A AU2001262953A1 (en) 2000-04-28 2001-04-25 Three-dimensional memory array and method of fabrication

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US56062600A 2000-04-28 2000-04-28
US09/560,626 2000-04-28
US09/814,727 2001-03-21
US09/814,727 US6420215B1 (en) 2000-04-28 2001-03-21 Three-dimensional memory array and method of fabrication

Publications (2)

Publication Number Publication Date
WO2001084553A2 WO2001084553A2 (en) 2001-11-08
WO2001084553A3 true WO2001084553A3 (en) 2002-06-06

Family

ID=24238610

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013575 WO2001084553A2 (en) 2000-04-28 2001-04-25 Three-dimensional memory array and method of fabrication

Country Status (5)

Country Link
US (3) US6653712B2 (en)
EP (1) EP1284017A4 (en)
AU (1) AU2001262953A1 (en)
TW (1) TW507368B (en)
WO (1) WO2001084553A2 (en)

Families Citing this family (185)

* Cited by examiner, † Cited by third party
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