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WO2001077819A3 - Method for making efficient service calls to a hardware coprocessor - Google Patents

Method for making efficient service calls to a hardware coprocessor Download PDF

Info

Publication number
WO2001077819A3
WO2001077819A3 PCT/US2001/011212 US0111212W WO0177819A3 WO 2001077819 A3 WO2001077819 A3 WO 2001077819A3 US 0111212 W US0111212 W US 0111212W WO 0177819 A3 WO0177819 A3 WO 0177819A3
Authority
WO
WIPO (PCT)
Prior art keywords
coprocessor
service port
status
service
different
Prior art date
Application number
PCT/US2001/011212
Other languages
French (fr)
Other versions
WO2001077819A2 (en
Inventor
John E Derrick
Robert G Mcdonald
Barry D Williamson
Original Assignee
Chicory Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chicory Systems Inc filed Critical Chicory Systems Inc
Priority to AU5319901A priority Critical patent/AU5319901A/en
Publication of WO2001077819A2 publication Critical patent/WO2001077819A2/en
Publication of WO2001077819A3 publication Critical patent/WO2001077819A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30174Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Advance Control (AREA)

Abstract

A coprocessor has a service port architecture which may support multiple service ports, each of which may be assigned to a different process. Operations supported by the coprocessor may be requested using commands to the service port, and status may be checked using status commands to the service port. Since different processes may be assigned to different service ports, the coprocessor may be able to determine, while performing an operation for a process, that a different process is requesting an operation. In one embodiment, the coprocessor may interrupt the in-progress operation to perform the newly requested operation. When status is requested for the interrupted operation, the coprocessor may return a failure status code indicating the interrupted operation was interrupted. In one embodiment, when the coprocessor initiates an operation for a service port, the coprocessor establishes a reservation for that service port. If a reservation for a service port is inactive when a status command is received on that service port, then the coprocessor may indicate that the operation failed (was unsuccessful) due to interruption by another operation from a different service port. In one embodiment, the coprocessor may support the locking of one or more resources which may store the output of an operation. If another operation would use the resources locked to a service port, that operation may be terminated with a failure status indicating that the resources used are locked to another service port.
PCT/US2001/011212 2000-04-05 2001-04-05 Method for making efficient service calls to a hardware coprocessor WO2001077819A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU5319901A AU5319901A (en) 2000-04-05 2001-04-05 Method for making efficient service calls to a hardware coprocessor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54359800A 2000-04-05 2000-04-05
US09/543,598 2000-04-05

Publications (2)

Publication Number Publication Date
WO2001077819A2 WO2001077819A2 (en) 2001-10-18
WO2001077819A3 true WO2001077819A3 (en) 2002-07-04

Family

ID=24168702

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/011212 WO2001077819A2 (en) 2000-04-05 2001-04-05 Method for making efficient service calls to a hardware coprocessor

Country Status (2)

Country Link
AU (1) AU5319901A (en)
WO (1) WO2001077819A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7234144B2 (en) 2002-01-04 2007-06-19 Microsoft Corporation Methods and system for managing computational resources of a coprocessor in a computing system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998021655A1 (en) * 1996-11-13 1998-05-22 Paran, Arik Real time program language accelerator
US5790881A (en) * 1995-02-07 1998-08-04 Sigma Designs, Inc. Computer system including coprocessor devices simulating memory interfaces
US6075546A (en) * 1997-11-10 2000-06-13 Silicon Grahphics, Inc. Packetized command interface to graphics processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790881A (en) * 1995-02-07 1998-08-04 Sigma Designs, Inc. Computer system including coprocessor devices simulating memory interfaces
WO1998021655A1 (en) * 1996-11-13 1998-05-22 Paran, Arik Real time program language accelerator
US6075546A (en) * 1997-11-10 2000-06-13 Silicon Grahphics, Inc. Packetized command interface to graphics processor

Also Published As

Publication number Publication date
AU5319901A (en) 2001-10-23
WO2001077819A2 (en) 2001-10-18

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