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WO2001071427A1 - Procede photolithographique pour semi-conducteurs - Google Patents

Procede photolithographique pour semi-conducteurs Download PDF

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Publication number
WO2001071427A1
WO2001071427A1 PCT/IB2001/000410 IB0100410W WO0171427A1 WO 2001071427 A1 WO2001071427 A1 WO 2001071427A1 IB 0100410 W IB0100410 W IB 0100410W WO 0171427 A1 WO0171427 A1 WO 0171427A1
Authority
WO
WIPO (PCT)
Prior art keywords
resist
semiconductor
reticle
resist layer
light
Prior art date
Application number
PCT/IB2001/000410
Other languages
English (en)
Inventor
Alain Bernard Charles
John George Maltabes
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Publication of WO2001071427A1 publication Critical patent/WO2001071427A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof

Definitions

  • the present invention relates to a method for forming structures on a semiconductor wafer by photo-lithographic steps and by ion implant steps.
  • the general method for doping a semiconductor is based on preparing a mask by photo-lithographic steps and subsequently implanting ions in the semiconductor so as to determine its conductivity which depends on the doping profile and the doping level .
  • Fig. 1 shows the principal light path in a photo- lithographic apparatus to which the invention is applicable.
  • Fig. 2 is a perspective view of the main parts of the apparatus in Fig. 1.
  • Fig. 3 shows the effect of a partially blocked light path in the resist before, during and after developing and cleansing.
  • the principle of the invention is based on generating a different remaining resist thickness after the lithographic step at different locations within the image field of the optical image system.
  • the modulation of the remaining resist thickness will allow to modulate either the implant depth or the implant dose, or both in the following implant step.
  • the method for forming structures on a semiconductor wafer by photo-lithographic steps and by ion implant steps comprises the steps of: deposition of a resist layer on a surface of said semiconductor wafer, exposing said resist layer to light of a predetermined wavelength through a reticle and an optical system so as to form an image of said reticle on said semiconduc- tor surface, developing and cleansing said surface of said semiconductor wafer so as to remove at least partly said resist layer depending on whether or not said resist layer had been exposed, implantation of ions so as to determine the conductivity of said semiconductor in said cleansed areas of said semi- conductor surface, wherein fine structures are deposited in predetermined areas and in a predetermined distribution on said reticle before exposing said resist to said light, said fine structures having at least one dimension being smaller than the resolution of said optical system.
  • a low contrast resist is used in order to have a broader scope for the sub-resolution dimension of the fine structures.
  • an optical system of low resolution may be used.
  • FIG. 1 a schematic view of the light path in a prior art photo-lithographic apparatus is shown.
  • Light is emitted by a light source 1, which is preferably a laser or a mercury lamp emitting light of a predetermined wavelength between 300 nm and 450 nm.
  • the light from the light source 1 is directed to a reticle 4 by several optical elements 3 such as mirrors and lenses on a path 2.
  • the reticle 4 contains the structure of which an image is to be formed on the surface of a semiconductor wafer 7. To that order a resist layer (not shown) is depos- ited on the surface of said semiconductor wafer 7.
  • Said resist layer is exposed to the light from said light source 1 which passes the reticle 4 and an optical system of a collimator lens 5 and a projection objective 6 before it reaches the surface of the semiconductor wafer 7.
  • an image of the re- ticle is formed on the resist layer on the semiconductor surface.
  • the image may be a l:l-image or a 10:l-image or of any other ratio.
  • Both semiconductor wafer 7 and reticle 4 are moved with respect to the light beam 2 so as to be able to expose the whole resist on the surface of the semiconductor. Therefore the wafer 7 is mounted on a support 8 which itself is linked to a movable xy-table.
  • the details of the optical system and the mounted wafer 7 are shown in Fig. 2.
  • the wafer 7 comprises several chips 11. In Fig. 2 some of the chips 11 are already exposed (white squares) and some of the chips 11 are still to be exposed (black squares) .
  • the support 8 for the wafer 7 is fixed to the movable xy-table 12 which is driven by steppers (not shown) .
  • the light from the light source 1 is collimated and focused on the wafer 7 by a collimator lens 5 and a projection objective 6.
  • said surface of said semiconductor wafer 7 is developed and cleansed so as to remove at least partly said resist layer.
  • Which part of the resist layer is removed from the semiconductor surface depends on whether the light from the light source 1 has passed the reticle 4 or has been blocked by a structure on the reticle 4. Further, it depends on the type of resist 4. If a positive resist is used the exposed resist is removed after developing, if a negative resist is used the non-exposed resist is removed from the semi- conductor surface after developing.
  • the desired areas are defined for subsequent ion implant steps. Wherever the resist has been removed ions can penetrate into the semiconductor and thus the conductivity of the semiconductor can be determined in the corresponding areas by choosing the appropriate dose and profile (depth in the semiconductor) .
  • the dose of the ion implanta- tion is the same over the whole wafer.
  • the modulation of the resist thickness can be obtained by modulating the light transmittance of the reticle 4 at different locations.
  • adding material on the reticle 4 in order to modify to mask transmittance locally would lead to expensive mask fabrication. Therefore it is taken advantage of running the optical system at a low resolution, since implant layers are usually non critical layers in terms of resolution.
  • a fine structure e.g. a chrome pattern is generated on the mask.
  • the fine structure provides substantially a two-dimensional pattern on the reticle 4. One of its two dimensions is chosen so as to be below the actual lens resolution, e.g. a sub-resolution square of chrome (like a checker) or pattern. Since these patterns are not resolved by the lens, they act actually as transmittance modulation patterns for the stepper.
  • Such a fine structure 10 is shown along with a "normal" structure 9 in Fig. 1.
  • the fine structures 10 are deposited in predetermined areas besides the "normal" structures 9. Addi- tionally, they are distributed with a predetermined density on said reticle 4 between the normal size structures on the reticle 4 before exposing said resist 14 to the light from the light source 1.
  • at least one dimension of said fine structures 10 must be smaller than the resolution of said optical system of mirrors 3, collimator lens 5, and objective 6.
  • a low contrast photo-resist material is used which leads to a more or less pronounced resist scumming, depending on the transmittance modulation.
  • Low contrast resists are resists for which the remaining resist thickness versus the exposure dose decreased slowly from 100% (no exposure) to 0%, (once the exposure threshold is passed), as opposed to high contrast resist for which the change occurs with a step function. Because contrast depends on the pattern size and because of the low contrast material the mask transmittance modulation patterns allows controlling and adjusting the remaining resist thickness at different locations within the exposed image field, and thus later the implant dose and depth may be locally tuned.
  • collimator lens 5 For extending the scope of possible small dimensions of the fine structure even further a low resolution optical system of mirrors 3, collimator lens 5, and objective 6 is used.
  • Fig. 3A to 3C The effect of the modulated resist thickness is shown in Fig. 3A to 3C. Due to the varying transmittance of the optical system exposure light 13 has a locally varying intensity. This is indicated in Fig. 3A by arrows of different length; longer arrows mean light with a higher intensity and vice versa.
  • the light 13 reaches the resist 14 which is deposited on a first semiconductor layer 15.
  • the first semiconductor layer 15 itself is above a second semiconductor layer 16 in this embodiment. Since the light 13 has different intensities according to the location on the semiconductor surface the resist layer 14 is removed in the course of developing and cleansing steps leaving a remaining layer of varying thickness on the semiconductor surface and with a modulated structure over the whole surface, e.g. comprising bubbles 17 (Fig. 3B) .
  • the ions in a ion implantation step can penetrate deeper into the semiconductor.
  • the areas with thinner remaining resist layer on the surface differ from neighboring areas with thicker remaining resist layers as to their electrical characteristics.
  • the areas of the second semiconductor layer 15 may be retained with the higher ion density (Fig. 3C) .

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

La présente invention se rapporte à un procédé de formation de structures sur un dispositif semi-conducteur (7) au moyen d'étapes photolithographiques et d'étapes d'implantation ioniques consistant: à déposer une couche de photorésine (14) sur une surface de ladite plaquette semi-conductrice (7), à exposer ladite couche de photorésine à une lumière d'une longueur d'onde prédéterminée au moyen d'un réticule (4) et d'un système optique (3, 4, 5) de manière à former une image dudit réticule sur ladite surface semi-conductrice, à développer et à nettoyer ladite surface de plaquette semi-conductrice (7) afin de retirer au moins partiellement la couche de photorésine (14) suivant que ladite couche a été exposée ou non, à implanter les ions de manière à déterminer la conductivité dudit semi-conducteur dans les zones nettoyées de la surface semi-conductrice. Afin de permettre des changements de profondeur d'implantation et de quantité des éléments implantés en différents emplacements sur le circuit intégré en une seule étape lithographique, des structures fines (10) sont déposées dans des zones préétablies et suivant une répartition préétablie sur ledit réticule (4) avant d'exposer la photorésine (14) à la lumière, lesdites structures fines ayant au moins une dimension inférieure à la résolution du système optique (3, 5, 6).
PCT/IB2001/000410 2000-03-20 2001-03-19 Procede photolithographique pour semi-conducteurs WO2001071427A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53131700A 2000-03-20 2000-03-20
US09/531,317 2000-03-20

Publications (1)

Publication Number Publication Date
WO2001071427A1 true WO2001071427A1 (fr) 2001-09-27

Family

ID=24117141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2001/000410 WO2001071427A1 (fr) 2000-03-20 2001-03-19 Procede photolithographique pour semi-conducteurs

Country Status (2)

Country Link
TW (1) TW495851B (fr)
WO (1) WO2001071427A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
DE3402653A1 (de) * 1984-01-26 1985-08-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung speziell dotierter bereiche in halbleitermaterial
DE4020076A1 (de) * 1990-06-23 1992-01-09 El Mos Elektronik In Mos Techn Verfahren zur herstellung eines pmos-transistors sowie pmos-transistor
EP0731387A2 (fr) * 1995-02-16 1996-09-11 Samsung Electronics Co., Ltd. Méthodes d'implantation ionique et de fabrication de motifs utilisant un masque à tons gris

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
DE3402653A1 (de) * 1984-01-26 1985-08-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung speziell dotierter bereiche in halbleitermaterial
DE4020076A1 (de) * 1990-06-23 1992-01-09 El Mos Elektronik In Mos Techn Verfahren zur herstellung eines pmos-transistors sowie pmos-transistor
EP0731387A2 (fr) * 1995-02-16 1996-09-11 Samsung Electronics Co., Ltd. Méthodes d'implantation ionique et de fabrication de motifs utilisant un masque à tons gris

Also Published As

Publication number Publication date
TW495851B (en) 2002-07-21

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